Initialise CPU contexts from entry_point_info
Consolidate all BL3-1 CPU context initialization for cold boot, PSCI
and SPDs into two functions:
* The first uses entry_point_info to initialize the relevant
cpu_context for first entry into a lower exception level on a CPU
* The second populates the EL1 and EL2 system registers as needed
from the cpu_context to ensure correct entry into the lower EL
This patch alters the way that BL3-1 determines which exception level
is used when first entering EL1 or EL2 during cold boot - this is now
fully determined by the SPSR value in the entry_point_info for BL3-3,
as set up by the platform code in BL2 (or otherwise provided to BL3-1).
In the situation that EL1 (or svc mode) is selected for a processor
that supports EL2, the context management code will now configure all
essential EL2 register state to ensure correct execution of EL1. This
allows the platform code to run non-secure EL1 payloads directly
without requiring a small EL2 stub or OS loader.
Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
diff --git a/bl31/aarch64/context.S b/bl31/aarch64/context.S
index d0bca64..6667419 100644
--- a/bl31/aarch64/context.S
+++ b/bl31/aarch64/context.S
@@ -43,9 +43,8 @@
.global el3_sysregs_context_save
func el3_sysregs_context_save
- mrs x9, scr_el3
mrs x10, sctlr_el3
- stp x9, x10, [x0, #CTX_SCR_EL3]
+ str x10, [x0, #CTX_SCTLR_EL3]
mrs x11, cptr_el3
stp x11, xzr, [x0, #CTX_CPTR_EL3]
@@ -98,8 +97,7 @@
/* Make sure all the above changes are observed */
isb
- ldp x9, x10, [x0, #CTX_SCR_EL3]
- msr scr_el3, x9
+ ldr x10, [x0, #CTX_SCTLR_EL3]
msr sctlr_el3, x10
isb