feat(msm8916): power on L2 caches for secondary clusters
On platforms with multiple CPU clusters the L2 cache will be only on
for the cluster of the boot CPU. Add the necessary sequence to power it
up for secondary clusters similar to the CPU boot sequence.
No functional change for platforms with a single cluster. The new code
is discarded entirely in this case.
Change-Id: I3d3bce519a8a10ef5278d74d81acf59123e00454
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
diff --git a/plat/qti/msm8916/msm8916_cpu_boot.c b/plat/qti/msm8916/msm8916_cpu_boot.c
index 3668903..d6faa59 100644
--- a/plat/qti/msm8916/msm8916_cpu_boot.c
+++ b/plat/qti/msm8916/msm8916_cpu_boot.c
@@ -26,6 +26,32 @@
#define APC_PWR_GATE_CTL_GHDS_EN BIT_32(0)
#define APC_PWR_GATE_CTL_GHDS_CNT(cnt) ((cnt) << 24)
+#define PWR_CTL_OVERRIDE 0xc
+#define L2_PWR_CTL 0x14
+#define L2_PWR_STATUS 0x18
+#define CORE_CBCR 0x58
+
+#define PWR_CTL_OVERRIDE_PRESETDBG BIT_32(22)
+
+#define L2_PWR_CTL_L2_ARRAY_HS BIT_32(0)
+#define L2_PWR_CTL_SCU_ARRAY_HS BIT_32(1)
+#define L2_PWR_CTL_L2_RST_DIS BIT_32(2)
+#define L2_PWR_CTL_L2_HS_CLAMP BIT_32(8)
+#define L2_PWR_CTL_L2_HS_EN BIT_32(9)
+#define L2_PWR_CTL_L2_HS_RST BIT_32(10)
+#define L2_PWR_CTL_L2_SLEEP_STATE BIT_32(11)
+#define L2_PWR_CTL_SYS_RESET BIT_32(12)
+#define L2_PWR_CTL_L2_RET_SLP BIT_32(13)
+#define L2_PWR_CTL_SCU_ARRAY_HS_CLAMP BIT_32(14)
+#define L2_PWR_CTL_L2_ARRAY_HS_CLAMP BIT_32(15)
+#define L2_PWR_CTL_L2_HS_CNT(cnt) ((cnt) << 16)
+#define L2_PWR_CTL_PMIC_APC_ON BIT_32(28)
+
+#define L2_PWR_STATUS_L2_HS_STS BIT_32(9)
+
+#define CORE_CBCR_CLK_ENABLE BIT_32(0)
+#define CORE_CBCR_HW_CTL BIT_32(1)
+
/* Boot a secondary CPU core for the first time. */
void msm8916_cpu_boot(uintptr_t acs)
{
@@ -65,3 +91,60 @@
mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
dsb();
}
+
+/* Power on cluster L2 cache for the first time. */
+void msm8916_l2_boot(uintptr_t base)
+{
+ uint32_t pwr_ctl, cbcr, ovr;
+
+ /* Skip if cluster L2 is already powered on */
+ if (mmio_read_32(base + L2_PWR_STATUS) & L2_PWR_STATUS_L2_HS_STS) {
+ VERBOSE("PSCI: L2 cache @ 0x%08lx is already powered on\n", base);
+ return;
+ }
+
+ VERBOSE("PSCI: Powering on L2 cache @ 0x%08lx\n", base);
+
+ pwr_ctl = L2_PWR_CTL_L2_HS_CLAMP | L2_PWR_CTL_L2_HS_EN |
+ L2_PWR_CTL_L2_HS_RST | L2_PWR_CTL_SYS_RESET |
+ L2_PWR_CTL_SCU_ARRAY_HS_CLAMP | L2_PWR_CTL_L2_ARRAY_HS_CLAMP |
+ L2_PWR_CTL_L2_HS_CNT(16);
+ mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
+
+ ovr = PWR_CTL_OVERRIDE_PRESETDBG;
+ mmio_write_32(base + PWR_CTL_OVERRIDE, ovr);
+ dsb();
+ udelay(2);
+
+ pwr_ctl &= ~(L2_PWR_CTL_SCU_ARRAY_HS_CLAMP |
+ L2_PWR_CTL_L2_ARRAY_HS_CLAMP);
+ mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
+
+ pwr_ctl |= (L2_PWR_CTL_L2_ARRAY_HS | L2_PWR_CTL_SCU_ARRAY_HS);
+ mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
+ dsb();
+ udelay(2);
+
+ cbcr = CORE_CBCR_CLK_ENABLE;
+ mmio_write_32(base + CORE_CBCR, cbcr);
+
+ pwr_ctl &= ~L2_PWR_CTL_L2_HS_CLAMP;
+ mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
+ dsb();
+ udelay(2);
+
+ ovr &= ~PWR_CTL_OVERRIDE_PRESETDBG;
+ mmio_write_32(base + PWR_CTL_OVERRIDE, ovr);
+
+ pwr_ctl &= ~(L2_PWR_CTL_L2_HS_RST | L2_PWR_CTL_SYS_RESET);
+ mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
+ dsb();
+ udelay(54);
+
+ pwr_ctl |= L2_PWR_CTL_PMIC_APC_ON;
+ mmio_write_32(base + L2_PWR_CTL, pwr_ctl);
+
+ cbcr |= CORE_CBCR_HW_CTL;
+ mmio_write_32(base + CORE_CBCR, cbcr);
+ dsb();
+}
diff --git a/plat/qti/msm8916/msm8916_pm.c b/plat/qti/msm8916/msm8916_pm.c
index 79c670f..7b44d60 100644
--- a/plat/qti/msm8916/msm8916_pm.c
+++ b/plat/qti/msm8916/msm8916_pm.c
@@ -34,6 +34,10 @@
static int msm8916_pwr_domain_on(u_register_t mpidr)
{
+ /* Power on L2 cache and secondary CPU core for the first time */
+ if (PLATFORM_CLUSTER_COUNT > 1) {
+ msm8916_l2_boot(APCS_GLB(MPIDR_APCS_CLUSTER(mpidr)));
+ }
msm8916_cpu_boot(APCS_ALIAS_ACS(MPIDR_APCS_CLUSTER(mpidr),
MPIDR_AFFLVL0_VAL(mpidr)));
return PSCI_E_SUCCESS;
diff --git a/plat/qti/msm8916/msm8916_pm.h b/plat/qti/msm8916/msm8916_pm.h
index 38190a3..f301d3c 100644
--- a/plat/qti/msm8916/msm8916_pm.h
+++ b/plat/qti/msm8916/msm8916_pm.h
@@ -8,5 +8,6 @@
#define MSM8916_PM_H
void msm8916_cpu_boot(uintptr_t acs);
+void msm8916_l2_boot(uintptr_t base);
#endif /* MSM8916_PM_H */