Merge "fix(intel): refactor SDMMC driver for Altera products" into integration
diff --git a/drivers/cadence/emmc/cdns_sdmmc.c b/drivers/cadence/emmc/cdns_sdmmc.c
index d2cd4d6..892d333 100644
--- a/drivers/cadence/emmc/cdns_sdmmc.c
+++ b/drivers/cadence/emmc/cdns_sdmmc.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,35 +19,6 @@
#include <lib/mmio.h>
#include <lib/utils.h>
-/* Card busy and present */
-#define CARD_BUSY 1
-#define CARD_NOT_BUSY 0
-
-/* 500 ms delay to read the RINST register */
-#define DELAY_MS_SRS_READ 500
-#define DELAY_RES 10
-
-/* SRS12 error mask */
-#define SRS12_ERR_MASK 0xFFFF8000
-
-/* Check DV dfi_init val=0 */
-#define IO_MASK_END_DATA 0x0
-
-/* Check DV dfi_init val=2; DDR Mode */
-#define IO_MASK_END_DATA_DDR 0x2
-#define IO_MASK_START_DATA 0x0
-#define DATA_SELECT_OE_END_DATA 0x1
-
-#define TIMEOUT 100000
-
-/* General define */
-#define SDHC_REG_MASK UINT_MAX
-#define SD_HOST_BLOCK_SIZE 0x200
-#define DTCVVAL_DEFAULT_VAL 0xE
-#define CDMMC_DMA_MAX_BUFFER_SIZE 64*1024
-#define CDNSMMC_ADDRESS_MASK U(0x0f)
-#define CONFIG_CDNS_DESC_COUNT 8
-
void cdns_init(void);
int cdns_send_cmd(struct mmc_cmd *cmd);
int cdns_set_ios(unsigned int clk, unsigned int width);
@@ -62,7 +34,8 @@
.read = cdns_read,
.write = cdns_write,
};
-
+void sd_host_adma_prepare(struct cdns_idmac_desc *desc_ptr, uintptr_t buf,
+ size_t size);
struct cdns_sdmmc_params cdns_params;
struct cdns_sdmmc_combo_phy sdmmc_combo_phy_reg;
struct cdns_sdmmc_sdhc sdmmc_sdhc_reg;
@@ -89,45 +62,22 @@
}
} while ((data & (1 << SDMMC_CDN_ICS)) == 0);
- return 0;
-}
-
-int cdns_busy(void)
-{
- unsigned int data;
-
- data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS09);
- return (data & STATUS_DATA_BUSY) ? CARD_BUSY : CARD_NOT_BUSY;
-}
-
-int cdns_vol_reset(void)
-{
- /* Reset embedded card */
- mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP));
- udelay(250);
- mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (0 << SDMMC_CDN_BP));
- udelay(500);
-
- /* Turn on supply voltage */
- /* BVS = 7, BP = 1, BP2 only in UHS2 mode */
- mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP));
- udelay(250);
return 0;
}
void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg,
- struct cdns_sdmmc_sdhc *sdhc_reg)
+ struct cdns_sdmmc_sdhc *sdhc_reg)
{
/* Values are taken by the reference of cadence IP documents */
combo_phy_reg->cp_clk_wr_delay = 0;
combo_phy_reg->cp_clk_wrdqs_delay = 0;
- combo_phy_reg->cp_data_select_oe_end = 0;
+ combo_phy_reg->cp_data_select_oe_end = 1;
combo_phy_reg->cp_dll_bypass_mode = 1;
combo_phy_reg->cp_dll_locked_mode = 0;
- combo_phy_reg->cp_dll_start_point = 0;
+ combo_phy_reg->cp_dll_start_point = 254;
combo_phy_reg->cp_gate_cfg_always_on = 1;
combo_phy_reg->cp_io_mask_always_on = 0;
- combo_phy_reg->cp_io_mask_end = 0;
+ combo_phy_reg->cp_io_mask_end = 5;
combo_phy_reg->cp_io_mask_start = 0;
combo_phy_reg->cp_rd_del_sel = 52;
combo_phy_reg->cp_read_dqs_cmd_delay = 0;
@@ -142,38 +92,58 @@
sdhc_reg->sdhc_extended_rd_mode = 1;
sdhc_reg->sdhc_extended_wr_mode = 1;
- sdhc_reg->sdhc_hcsdclkadj = 0;
+ sdhc_reg->sdhc_hcsdclkadj = 3;
sdhc_reg->sdhc_idelay_val = 0;
sdhc_reg->sdhc_rdcmd_en = 1;
sdhc_reg->sdhc_rddata_en = 1;
- sdhc_reg->sdhc_rw_compensate = 9;
+ sdhc_reg->sdhc_rw_compensate = 10;
sdhc_reg->sdhc_sdcfsh = 0;
- sdhc_reg->sdhc_sdcfsl = 1;
+ sdhc_reg->sdhc_sdcfsl = 0;
sdhc_reg->sdhc_wrcmd0_dly = 1;
sdhc_reg->sdhc_wrcmd0_sdclk_dly = 0;
sdhc_reg->sdhc_wrcmd1_dly = 0;
sdhc_reg->sdhc_wrcmd1_sdclk_dly = 0;
- sdhc_reg->sdhc_wrdata0_dly = 1;
+ sdhc_reg->sdhc_wrdata0_dly = 0;
sdhc_reg->sdhc_wrdata0_sdclk_dly = 0;
sdhc_reg->sdhc_wrdata1_dly = 0;
sdhc_reg->sdhc_wrdata1_sdclk_dly = 0;
}
-static int cdns_program_phy_reg(struct cdns_sdmmc_combo_phy *combo_phy_reg,
- struct cdns_sdmmc_sdhc *sdhc_reg)
+int cdns_program_phy_reg(struct cdns_sdmmc_combo_phy *combo_phy_reg,
+ struct cdns_sdmmc_sdhc *sdhc_reg)
{
uint32_t value = 0;
int ret = 0;
+ uint32_t timeout = 0;
+
+ /* HRS00 - Software Reset */
+ mmio_write_32((cdns_params.reg_base + SDHC_CDNS_HRS00), SDHC_CDNS_HRS00_SWR);
+
+ /* Waiting for SDHC_CDNS_HRS00_SWR reset */
+ timeout = TIMEOUT;
+ do {
+ udelay(250);
+ if (--timeout <= 0) {
+ NOTICE(" SDHC Software Reset failed!!!\n");
+ panic();
+ }
+ } while (((mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS00) &
+ SDHC_CDNS_HRS00_SWR) == 1));
+
+ /* Step 1, switch on DLL_RESET */
+ value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
+ value &= ~SDHC_PHY_SW_RESET;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09, value);
/* program PHY_DQS_TIMING_REG */
value = (CP_USE_EXT_LPBK_DQS(combo_phy_reg->cp_use_ext_lpbk_dqs)) |
(CP_USE_LPBK_DQS(combo_phy_reg->cp_use_lpbk_dqs)) |
(CP_USE_PHONY_DQS(combo_phy_reg->cp_use_phony_dqs)) |
(CP_USE_PHONY_DQS_CMD(combo_phy_reg->cp_use_phony_dqs_cmd));
- ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04,
- COMBO_PHY_REG + PHY_DQS_TIMING_REG, MMC_REG_BASE +
- SDHC_CDNS_HRS05, value);
- if (ret != 0) {
+ ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
+ COMBO_PHY_REG + PHY_DQS_TIMING_REG,
+ cdns_params.reg_base + SDHC_CDNS_HRS05, value);
+ if (ret != 0U) {
return ret;
}
@@ -183,73 +153,90 @@
(CP_RD_DEL_SEL(combo_phy_reg->cp_rd_del_sel)) |
(CP_UNDERRUN_SUPPRESS(combo_phy_reg->cp_underrun_suppress)) |
(CP_GATE_CFG_ALWAYS_ON(combo_phy_reg->cp_gate_cfg_always_on));
- ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04,
- COMBO_PHY_REG + PHY_GATE_LPBK_CTRL_REG, MMC_REG_BASE +
- SDHC_CDNS_HRS05, value);
- if (ret != 0) {
- return ret;
+ ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
+ COMBO_PHY_REG + PHY_GATE_LPBK_CTRL_REG,
+ cdns_params.reg_base + SDHC_CDNS_HRS05, value);
+ if (ret != 0U) {
+ return -ret;
}
/* program PHY_DLL_MASTER_CTRL_REG */
- value = (CP_DLL_BYPASS_MODE(combo_phy_reg->cp_dll_bypass_mode))
- | (CP_DLL_START_POINT(combo_phy_reg->cp_dll_start_point));
- ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04,
- COMBO_PHY_REG + PHY_DLL_MASTER_CTRL_REG, MMC_REG_BASE
- + SDHC_CDNS_HRS05, value);
- if (ret != 0) {
+ value = (CP_DLL_BYPASS_MODE(combo_phy_reg->cp_dll_bypass_mode)) | (2 << 20) |
+ (CP_DLL_START_POINT(combo_phy_reg->cp_dll_start_point));
+ ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
+ COMBO_PHY_REG + PHY_DLL_MASTER_CTRL_REG,
+ cdns_params.reg_base + SDHC_CDNS_HRS05, value);
+ if (ret != 0U) {
return ret;
}
/* program PHY_DLL_SLAVE_CTRL_REG */
- value = (CP_READ_DQS_CMD_DELAY(combo_phy_reg->cp_read_dqs_cmd_delay))
- | (CP_CLK_WRDQS_DELAY(combo_phy_reg->cp_clk_wrdqs_delay))
- | (CP_CLK_WR_DELAY(combo_phy_reg->cp_clk_wr_delay))
- | (CP_READ_DQS_DELAY(combo_phy_reg->cp_read_dqs_delay));
- ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04,
- COMBO_PHY_REG + PHY_DLL_SLAVE_CTRL_REG, MMC_REG_BASE
- + SDHC_CDNS_HRS05, value);
- if (ret != 0) {
+ value = (CP_READ_DQS_CMD_DELAY(combo_phy_reg->cp_read_dqs_cmd_delay)) |
+ (CP_CLK_WRDQS_DELAY(combo_phy_reg->cp_clk_wrdqs_delay)) |
+ (CP_CLK_WR_DELAY(combo_phy_reg->cp_clk_wr_delay)) |
+ (CP_READ_DQS_DELAY(combo_phy_reg->cp_read_dqs_delay));
+ ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
+ COMBO_PHY_REG + PHY_DLL_SLAVE_CTRL_REG,
+ cdns_params.reg_base + SDHC_CDNS_HRS05, value);
+ if (ret != 0U) {
return ret;
}
/* program PHY_CTRL_REG */
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS04, COMBO_PHY_REG
- + PHY_CTRL_REG);
- value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS05);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS04, COMBO_PHY_REG + PHY_CTRL_REG);
+ value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS05);
/* phony_dqs_timing=0 */
value &= ~(CP_PHONY_DQS_TIMING_MASK << CP_PHONY_DQS_TIMING_SHIFT);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS05, value);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS05, value);
/* switch off DLL_RESET */
do {
- value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09);
+ value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
value |= SDHC_PHY_SW_RESET;
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, value);
- value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09, value);
+ value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
/* polling PHY_INIT_COMPLETE */
} while ((value & SDHC_PHY_INIT_COMPLETE) != SDHC_PHY_INIT_COMPLETE);
/* program PHY_DQ_TIMING_REG */
- combo_phy_reg->cp_io_mask_end = 0U;
- value = (CP_IO_MASK_ALWAYS_ON(combo_phy_reg->cp_io_mask_always_on))
- | (CP_IO_MASK_END(combo_phy_reg->cp_io_mask_end))
- | (CP_IO_MASK_START(combo_phy_reg->cp_io_mask_start))
- | (CP_DATA_SELECT_OE_END(combo_phy_reg->cp_data_select_oe_end));
+ value = (CP_IO_MASK_ALWAYS_ON(combo_phy_reg->cp_io_mask_always_on)) |
+ (CP_IO_MASK_END(combo_phy_reg->cp_io_mask_end)) |
+ (CP_IO_MASK_START(combo_phy_reg->cp_io_mask_start)) |
+ (CP_DATA_SELECT_OE_END(combo_phy_reg->cp_data_select_oe_end));
- ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04,
- COMBO_PHY_REG + PHY_DQ_TIMING_REG, MMC_REG_BASE
- + SDHC_CDNS_HRS05, value);
- if (ret != 0) {
+ ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04,
+ COMBO_PHY_REG + PHY_DQ_TIMING_REG,
+ cdns_params.reg_base + SDHC_CDNS_HRS05, value);
+ if (ret != 0U) {
return ret;
}
+
+ value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
+ value |= (HRS_09_EXTENDED_RD_MODE | HRS_09_EXTENDED_WR_MODE |
+ HRS_09_RDCMD_EN | HRS_09_RDDATA_EN);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09, value);
+
+ value = 0;
+ value = SDHC_HCSDCLKADJ(HRS_10_HCSDCLKADJ_VAL);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS10, value);
+
+ value = 0;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS16, value);
+
+ value = (10 << 16);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS07, value);
+
return 0;
}
int cdns_read(int lba, uintptr_t buf, size_t size)
{
- inv_dcache_range(buf, size);
+ return 0;
+}
+int cdns_write(int lba, uintptr_t buf, size_t size)
+{
return 0;
}
@@ -260,120 +247,79 @@
int cdns_prepare(int dma_start_addr, uintptr_t dma_buff, size_t size)
{
- data_cmd = true;
- struct cdns_idmac_desc *desc;
- uint32_t desc_cnt, i;
- uint64_t desc_base;
-
+ struct cdns_idmac_desc *cdns_desc_data;
assert(((dma_buff & CDNSMMC_ADDRESS_MASK) == 0) &&
- (cdns_params.desc_size > 0) &&
- ((MMC_REG_BASE & MMC_BLOCK_MASK) == 0) &&
- ((cdns_params.desc_base & MMC_BLOCK_MASK) == 0) &&
- ((cdns_params.desc_size & MMC_BLOCK_MASK) == 0));
-
- flush_dcache_range(dma_buff, size);
-
- desc_cnt = (size + (CDMMC_DMA_MAX_BUFFER_SIZE) - 1) / (CDMMC_DMA_MAX_BUFFER_SIZE);
- assert(desc_cnt * sizeof(struct cdns_idmac_desc) < cdns_params.desc_size);
-
- if (desc_cnt > CONFIG_CDNS_DESC_COUNT) {
- ERROR("Requested data transfer length %ld is greater than configured length %d",
- size, (CONFIG_CDNS_DESC_COUNT * CDMMC_DMA_MAX_BUFFER_SIZE));
- return -EINVAL;
- }
-
- desc = (struct cdns_idmac_desc *)cdns_params.desc_base;
- desc_base = (uint64_t)desc;
- i = 0;
-
- while ((i + 1) < desc_cnt) {
- desc->attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
- desc->reserved = 0;
- desc->len = MAX_64KB_PAGE;
- desc->addr_lo = (dma_buff & UINT_MAX) + (CDMMC_DMA_MAX_BUFFER_SIZE * i);
-#if CONFIG_DMA_ADDR_T_64BIT == 1
- desc->addr_hi = (dma_buff >> 32) & 0xffffffff;
-#endif
- size -= CDMMC_DMA_MAX_BUFFER_SIZE;
- desc++;
- i++;
- }
+ (cdns_params.desc_size > 0));
- desc->attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA |
- ADMA_DESC_ATTR_END;
- desc->reserved = 0;
- desc->len = size;
-#if CONFIG_DMA_ADDR_T_64BIT == 1
- desc->addr_lo = (dma_buff & UINT_MAX) + (CDMMC_DMA_MAX_BUFFER_SIZE * i);
- desc->addr_hi = (dma_buff >> 32) & UINT_MAX;
-#else
- desc->addr_lo = (dma_buff & UINT_MAX);
-#endif
+ cdns_desc_data = (struct cdns_idmac_desc *)cdns_params.desc_base;
+ sd_host_adma_prepare(cdns_desc_data, dma_buff, size);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS22, (uint32_t)desc_base);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS23, (uint32_t)(desc_base >> 32));
- flush_dcache_range(cdns_params.desc_base,
- desc_cnt * CDMMC_DMA_MAX_BUFFER_SIZE);
-
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS01,
- ((512 << BLOCK_SIZE) | ((size/512) << BLK_COUNT_CT) | SDMA_BUF));
return 0;
}
-static void cdns_host_set_clk(int clk)
+void cdns_host_set_clk(uint32_t clk)
{
uint32_t ret = 0;
uint32_t sdclkfsval = 0;
- uint32_t dtcvval = DTCVVAL_DEFAULT_VAL;
+ uint32_t dtcvval = 0xE;
- sdclkfsval = (cdns_params.clk_rate / 2000) / clk;
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, 0);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) |
- (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE));
+ sdclkfsval = (SD_HOST_CLK / 2) / clk;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, 0);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11,
+ (dtcvval << SDMMC_CDN_DTCV) | (sdclkfsval << SDMMC_CDN_SDCLKFS) |
+ (1 << SDMMC_CDN_ICE));
- ret = cdns_wait_ics(5000, MMC_REG_BASE + SDHC_CDNS_SRS11);
- if (ret != 0U) {
- ERROR("Waiting SDMMC_CDN_ICS timeout");
+ ret = cdns_wait_ics(5000, cdns_params.reg_base + SDHC_CDNS_SRS11);
+ if (ret != 0) {
+ ERROR("Waiting ICS timeout");
}
-
/* Enable DLL reset */
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) &
- ~SDHC_DLL_RESET_MASK);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
+ mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) & ~0x00000001);
/* Set extended_wr_mode */
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, (mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09)
- & SDHC_EXTENDED_WR_MODE_MASK) | (1 << EXTENDED_WR_MODE));
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
+ (mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) & 0xFFFFFFF7) |
+ (1 << EXTENDED_WR_MODE));
/* Release DLL reset */
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE
- + SDHC_CDNS_HRS09) | 1);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE
- + SDHC_CDNS_HRS09) | (3 << RDCMD_EN));
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
+ mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) | PHY_SW_RESET_EN);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09,
+ mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) | RDCMD_EN);
do {
- mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09);
- } while (~mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & (1 << 1));
+ mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09);
+ } while (~mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09) &
+ (PHY_INIT_COMPLETE_BIT));
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) |
- (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE) | (1 << SDMMC_CDN_SDCE));
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS13, UINT_MAX);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) |
+ (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE) |
+ (1 << SDMMC_CDN_SDCE));
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS13, 0xFFFFFFFF);
}
int cdns_set_ios(unsigned int clk, unsigned int width)
{
+ uint32_t _status = 0;
+ _status = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
switch (width) {
case MMC_BUS_WIDTH_1:
- mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), LEDC_OFF);
+ _status &= ~(BIT4);
break;
+
case MMC_BUS_WIDTH_4:
- mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), DTW_4BIT);
+ _status |= BIT4;
break;
+
case MMC_BUS_WIDTH_8:
- mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), EDTW_8BIT);
+ _status |= BIT8;
break;
+
default:
assert(0);
break;
}
+ mmio_write_32((cdns_params.reg_base + SDHC_CDNS_SRS10), _status);
cdns_host_set_clk(clk);
return 0;
@@ -388,6 +334,7 @@
value |= data;
mmio_write_32(addr, value);
value = mmio_read_32(addr);
+
if (value != data) {
ERROR("SD host address is not set properly\n");
return -ENXIO;
@@ -396,429 +343,403 @@
return 0;
}
-int cdns_write(int lba, uintptr_t buf, size_t size)
-{
- return 0;
-}
-static int cdns_init_hrs_io(struct cdns_sdmmc_combo_phy *combo_phy_reg,
- struct cdns_sdmmc_sdhc *sdhc_reg)
+
+void sd_host_oper_mode(enum sd_opr_modes opr_mode)
{
- uint32_t value = 0;
- int ret = 0;
- /* program HRS09, register 42 */
- value = (SDHC_RDDATA_EN(sdhc_reg->sdhc_rddata_en))
- | (SDHC_RDCMD_EN(sdhc_reg->sdhc_rdcmd_en))
- | (SDHC_EXTENDED_WR_MODE(sdhc_reg->sdhc_extended_wr_mode))
- | (SDHC_EXTENDED_RD_MODE(sdhc_reg->sdhc_extended_rd_mode));
- ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS09, value);
- if (ret != 0) {
- ERROR("Program HRS09 failed");
- return ret;
- }
+ uint32_t reg = 0;
- /* program HRS10, register 43 */
- value = (SDHC_HCSDCLKADJ(sdhc_reg->sdhc_hcsdclkadj));
- ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS10, value);
- if (ret != 0) {
- ERROR("Program HRS10 failed");
- return ret;
- }
+ switch (opr_mode) {
+ case SD_HOST_OPR_MODE_HV4E_0_SDMA_32:
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
+ reg &= ~(DMA_SEL_BIT);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
+ reg &= ~(HV4E | BIT_AD_64);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
+ break;
- /* program HRS16, register 48 */
- value = (SDHC_WRDATA1_SDCLK_DLY(sdhc_reg->sdhc_wrdata1_sdclk_dly))
- | (SDHC_WRDATA0_SDCLK_DLY(sdhc_reg->sdhc_wrdata0_sdclk_dly))
- | (SDHC_WRCMD1_SDCLK_DLY(sdhc_reg->sdhc_wrcmd1_sdclk_dly))
- | (SDHC_WRCMD0_SDCLK_DLY(sdhc_reg->sdhc_wrcmd0_sdclk_dly))
- | (SDHC_WRDATA1_DLY(sdhc_reg->sdhc_wrdata1_dly))
- | (SDHC_WRDATA0_DLY(sdhc_reg->sdhc_wrdata0_dly))
- | (SDHC_WRCMD1_DLY(sdhc_reg->sdhc_wrcmd1_dly))
- | (SDHC_WRCMD0_DLY(sdhc_reg->sdhc_wrcmd0_dly));
- ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS16, value);
- if (ret != 0) {
- ERROR("Program HRS16 failed");
- return ret;
- }
+ case SD_HOST_OPR_MODE_HV4E_1_SDMA_32:
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
+ reg &= ~(DMA_SEL_BIT);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
+ reg &= ~(HV4E | BIT_AD_64);
+ reg |= (HV4E);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
+ break;
- /* program HRS07, register 40 */
- value = (SDHC_RW_COMPENSATE(sdhc_reg->sdhc_rw_compensate))
- | (SDHC_IDELAY_VAL(sdhc_reg->sdhc_idelay_val));
- ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS07, value);
- if (ret != 0) {
- ERROR("Program HRS07 failed");
- return ret;
- }
+ case SD_HOST_OPR_MODE_HV4E_1_SDMA_64:
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
+ reg &= ~(DMA_SEL_BIT);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
+ reg |= (HV4E | BIT_AD_64);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
+ break;
- return ret;
+ case SD_HOST_OPR_MODE_HV4E_0_ADMA_32:
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
+ reg &= ~(DMA_SEL_BIT);
+ reg |= DMA_SEL_BIT_2;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
+ reg &= ~(HV4E | BIT_AD_64);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
+ break;
+
+ case SD_HOST_OPR_MODE_HV4E_0_ADMA_64:
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
+ reg &= ~(DMA_SEL_BIT);
+ reg |= DMA_SEL_BIT_3;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
+ reg &= ~(HV4E | BIT_AD_64);
+ reg |= BIT_AD_64;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
+ break;
+
+ case SD_HOST_OPR_MODE_HV4E_1_ADMA_32:
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
+ reg &= ~(DMA_SEL_BIT);
+ reg |= DMA_SEL_BIT_2;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
+ reg &= ~(HV4E | BIT_AD_64);
+ reg |= HV4E;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
+ break;
+
+ case SD_HOST_OPR_MODE_HV4E_1_ADMA_64:
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
+ reg &= ~(DMA_SEL_BIT);
+ reg |= DMA_SEL_BIT_2;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg);
+ reg = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS15);
+ reg |= (HV4E | BIT_AD_64);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS15, reg);
+ break;
+ }
}
-static int cdns_hc_set_clk(struct cdns_sdmmc_params *cdn_sdmmc_dev_mode_params)
+void card_reset(bool power_enable)
{
- uint32_t ret = 0;
- uint32_t dtcvval, sdclkfsval;
+ uint32_t reg_value = 0;
- dtcvval = DTC_VAL;
- sdclkfsval = 0;
+ /* Reading SRS10 value before writing */
+ reg_value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
- if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_DS) ||
- (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR12) ||
- (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_SDR_BC)) {
- sdclkfsval = 4;
- } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_HS) ||
- (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR25) ||
- (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_DDR50) ||
- (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_SDR)) {
- sdclkfsval = 2;
- } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR50) ||
- (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_DDR) ||
- (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS400) ||
- (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS400es)) {
- sdclkfsval = 1;
- } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR104) ||
- (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS200)) {
- sdclkfsval = 0;
+ if (power_enable == true) {
+ reg_value &= ~((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP));
+ reg_value = ((1 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP));
+ } else {
+ reg_value &= ~((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP));
}
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg_value);
+}
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, 0);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) |
- (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE));
- ret = cdns_wait_ics(5000, MMC_REG_BASE + SDHC_CDNS_SRS11);
- if (ret != 0U) {
- ERROR("Waiting SDMMC_CDN_ICS timeout");
- return ret;
- }
+void high_speed_enable(bool mode)
+{
- /* Enable DLL reset */
- mmio_write_32((MMC_REG_BASE + SDHC_CDNS_HRS09), mmio_read_32(MMC_REG_BASE
- + SDHC_CDNS_HRS09) & ~SDHC_DLL_RESET_MASK);
- /* Set extended_wr_mode */
- mmio_write_32((MMC_REG_BASE + SDHC_CDNS_HRS09),
- (mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & SDHC_EXTENDED_WR_MODE_MASK) |
- (1 << EXTENDED_WR_MODE));
- /* Release DLL reset */
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE
- + SDHC_CDNS_HRS09) | 1);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE
- + SDHC_CDNS_HRS09) | (3 << RDCMD_EN));
- do {
- mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09);
- } while (~mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & (1 << 1));
+ uint32_t reg_value = 0;
+ /* Reading SRS10 value before writing */
+ reg_value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) |
- (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE) | (1 << SDMMC_CDN_SDCE));
+ if (mode == true) {
+ reg_value |= HS_EN;
+ } else {
+ reg_value &= ~HS_EN;
+ }
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS13, UINT_MAX);
- return 0;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg_value);
}
int cdns_reset(void)
{
- uint32_t data = 0;
+ volatile uint32_t data = 0;
uint32_t count = 0;
- uint32_t value = 0;
-
- value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS11);
- value &= ~(0xFFFF);
- value |= 0x0;
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, value);
- udelay(500);
/* Software reset */
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS00, 1);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, SRS11_SRFA);
/* Wait status command response ready */
do {
- data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS00);
+ data = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS00);
count++;
- if (count >= 5000) {
+ if (count >= CDNS_TIMEOUT) {
return -ETIMEDOUT;
}
- /* Wait for HRS00.SWR */
- } while ((data & 1) == 1);
-
- /* Step 1, switch on DLL_RESET */
- value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09);
- value &= ~SDHC_PHY_SW_RESET;
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, value);
+ /* Wait for SRS11 */
+ } while (((SRS11_SRFA_CHK(data)) & 1) == 1);
return 0;
}
+void sdmmc_host_init(bool uhs2_enable)
+{
+ uint32_t timeout;
+
+ /* SRS11 - Host Control default value set */
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS11, 0x0);
+
+ /* Waiting for detect card */
+ timeout = TIMEOUT;
+ do {
+ udelay(250);
+ if (--timeout <= 0) {
+ NOTICE(" SDHC Card Detecion failed!!!\n");
+ panic();
+ }
+ } while (((mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS09) & CHECK_CARD) == 0));
+
+ /* UHS2 Host setting */
+ if (uhs2_enable == true) {
+ /** need to implement*/
+ }
+
+ /* Card reset */
+
+ card_reset(1);
+ udelay(2500);
+ card_reset(0);
+ udelay(2500);
+ card_reset(1);
+ udelay(2500);
+
+ /* Enable Interrupt Flags*/
+ mmio_write_32((cdns_params.reg_base + SDHC_CDNS_SRS13), ~0);
+ high_speed_enable(true);
+}
+
int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg,
-struct cdns_sdmmc_sdhc *mmc_sdhc_reg)
+ struct cdns_sdmmc_sdhc *mmc_sdhc_reg)
{
int ret = 0;
ret = cdns_reset();
- if (ret != 0) {
+ if (ret != 0U) {
ERROR("Program phy reg init failed");
return ret;
}
ret = cdns_program_phy_reg(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
- if (ret != 0) {
+ if (ret != 0U) {
ERROR("Program phy reg init failed");
return ret;
}
-
- ret = cdns_init_hrs_io(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
- if (ret != 0) {
- ERROR("Program init for HRS reg is failed");
- return ret;
- }
-
- ret = cdns_sd_card_detect();
- if (ret != 0) {
- ERROR("SD card does not detect");
- return ret;
- }
+ sdmmc_host_init(0);
+ cdns_host_set_clk(100000);
- ret = cdns_vol_reset();
- if (ret != 0) {
- ERROR("eMMC card reset failed");
- return ret;
- }
-
- ret = cdns_hc_set_clk(&cdns_params);
- if (ret != 0) {
- ERROR("hc set clk failed");
- return ret;
- }
+ sd_host_oper_mode(SD_HOST_OPR_MODE_HV4E_0_ADMA_64);
return 0;
}
-void cdns_srs10_value_toggle(uint8_t write_val, uint8_t prev_val)
-{
- uint32_t data_op = 0U;
-
- data_op = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS10);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS10, (data_op & (prev_val << 0)));
- mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS10);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS10, data_op | (write_val << 0));
-}
-
-void cdns_srs11_srs15_config(uint32_t srs11_val, uint32_t srs15_val)
-{
- uint32_t data = 0U;
-
- data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS11);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (data | srs11_val));
- data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS15);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS15, (data | srs15_val));
-}
-
int cdns_send_cmd(struct mmc_cmd *cmd)
{
- uint32_t op = 0, ret = 0;
- uint8_t write_value = 0, prev_val = 0;
- uint32_t value;
- int32_t timeout;
- uint32_t cmd_indx;
- uint32_t status = 0, srs15_val = 0, srs11_val = 0;
+ uint32_t cmd_flags = 0;
+ uint32_t timeout = 0;
uint32_t status_check = 0;
+ uint32_t mode = 0;
+ uint32_t status;
assert(cmd);
- cmd_indx = (cmd->cmd_idx) << COM_IDX;
-
- if (data_cmd) {
- switch (cmd->cmd_idx) {
- case SD_SWITCH:
- op = DATA_PRESENT;
- write_value = ADMA2_32 | DT_WIDTH;
- prev_val = ADMA2_32 | DT_WIDTH;
- cdns_srs10_value_toggle(write_value, prev_val);
- srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE;
- srs15_val = BIT_AD_64 | HV4E | V18SE;
- cdns_srs11_srs15_config(srs11_val, srs15_val);
- break;
- case SD_WRITE_SINGLE_BLOCK:
- case SD_READ_SINGLE_BLOCK:
- op = DATA_PRESENT;
- write_value = ADMA2_32 | HS_EN | DT_WIDTH | LEDC;
- prev_val = ADMA2_32 | HS_EN | DT_WIDTH;
- cdns_srs10_value_toggle(write_value, prev_val);
- srs15_val = PVE | BIT_AD_64 | HV4E | SDR104_MODE | V18SE;
- srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE;
- cdns_srs11_srs15_config(srs11_val, srs15_val);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS00, SAAR);
- break;
+ cmd_flags = CDNS_HOST_CMD_INHIBIT | CDNS_HOST_DATA_INHIBIT;
- case SD_WRITE_MULTIPLE_BLOCK:
- case SD_READ_MULTIPLE_BLOCK:
- op = DATA_PRESENT | AUTO_CMD_EN | MULTI_BLK_READ;
- write_value = ADMA2_32 | HS_EN | DT_WIDTH | LEDC;
- prev_val = ADMA2_32 | HS_EN | DT_WIDTH;
- cdns_srs10_value_toggle(write_value, prev_val);
- srs15_val = PVE | BIT_AD_64 | HV4E | SDR104_MODE | V18SE;
- srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE;
- cdns_srs11_srs15_config(srs11_val, srs15_val);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS00, SAAR);
- break;
+ if ((cmd->cmd_idx == SD_STOP_TRANSMISSION) && (!data_cmd)) {
+ cmd_flags &= ~CDNS_HOST_DATA_INHIBIT;
+ }
- case SD_APP_SEND_SCR:
- op = DATA_PRESENT;
- write_value = ADMA2_32 | LEDC;
- prev_val = LEDC;
- cdns_srs10_value_toggle(write_value, prev_val);
- srs15_val = BIT_AD_64 | HV4E | V18SE;
- srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE;
- cdns_srs11_srs15_config(srs11_val, srs15_val);
- break;
+ timeout = TIMEOUT;
+ do {
+ udelay(100);
+ if (--timeout <= 0) {
+ udelay(50);
+ NOTICE("Timeout occur data and cmd line %x\n",
+ mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS09));
+ panic();
+ }
+ } while ((mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS09) & (cmd_flags)));
- case SD_SEND_IF_COND:
- op = DATA_PRESENT | CMD_IDX_CHK_ENABLE;
- write_value = LEDC;
- prev_val = 0x0;
- cdns_srs10_value_toggle(write_value, prev_val);
- srs15_val = HV4E;
- srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE;
- cdns_srs11_srs15_config(srs11_val, srs15_val);
- break;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS12, 0xFFFFFFFF);
+ cmd_flags = 0;
+ cmd_flags = (cmd->cmd_idx) << COM_IDX;
- default:
- write_value = LEDC;
- prev_val = 0x0;
- cdns_srs10_value_toggle(write_value, prev_val);
- op = 0;
- break;
- }
+ if ((cmd->resp_type & MMC_RSP_136) != 0) {
+ cmd_flags |= RES_TYPE_SEL_136;
+ } else if (((cmd->resp_type & MMC_RSP_48) != 0) &&
+ ((cmd->resp_type & MMC_RSP_BUSY) != 0)) {
+ cmd_flags |= RES_TYPE_SEL_48_B;
+ } else if ((cmd->resp_type & MMC_RSP_48) != 0) {
+ cmd_flags |= RES_TYPE_SEL_48;
} else {
- switch (cmd->cmd_idx) {
- case SD_GO_IDLE_STATE:
- write_value = LEDC;
- prev_val = 0x0;
- cdns_srs10_value_toggle(write_value, prev_val);
- srs15_val = HV4E;
- srs11_val = SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE;
- cdns_srs11_srs15_config(srs11_val, srs15_val);
- break;
+ cmd_flags &= ~RES_TYPE_SEL_NO;
+ }
+
+ if ((cmd->resp_type & MMC_RSP_CRC) != 0) {
+ cmd_flags |= CMD_CHECK_RESP_CRC;
+ }
- case SD_ALL_SEND_CID:
- write_value = LEDC;
- prev_val = 0x0;
- cdns_srs10_value_toggle(write_value, prev_val);
- srs15_val = HV4E | V18SE;
- srs11_val = SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE;
- cdns_srs11_srs15_config(srs11_val, srs15_val);
- break;
+ if ((cmd->resp_type & MMC_RSP_CMD_IDX) != 0) {
+ cmd_flags |= CMD_IDX_CHK_ENABLE;
+ }
+
+ if ((cmd->cmd_idx == MMC_ACMD(51)) || (cmd->cmd_idx == MMC_CMD(17)) ||
+ (cmd->cmd_idx == MMC_CMD(18)) || (cmd->cmd_idx == MMC_CMD(24)) ||
+ (cmd->cmd_idx == MMC_CMD(25))) {
+ mmio_write_8((cdns_params.reg_base + DTCV_OFFSET), DTCV_VAL);
+ cmd_flags |= DATA_PRESENT;
+ mode |= BLK_CNT_EN;
+
+ mode |= (DMA_ENABLED);
+ if ((cmd->cmd_idx == SD_WRITE_MULTIPLE_BLOCK) ||
+ (cmd->cmd_idx == SD_READ_MULTIPLE_BLOCK)) {
+ mode |= (MULTI_BLK_READ);
+ } else {
+ mode &= ~(MULTI_BLK_READ);
+ }
+ if ((cmd->cmd_idx == SD_WRITE_MULTIPLE_BLOCK) ||
+ (cmd->cmd_idx == SD_WRITE_SINGLE_BLOCK)) {
+ mode &= ~CMD_READ;
+ } else {
+ mode |= CMD_READ;
+ }
+ mmio_write_16(cdns_params.reg_base + SDHC_CDNS_SRS03, mode);
- case SD_SEND_IF_COND:
- op = CMD_IDX_CHK_ENABLE;
- write_value = LEDC;
- prev_val = 0x0;
- cdns_srs10_value_toggle(write_value, prev_val);
- srs15_val = HV4E;
- srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE;
- cdns_srs11_srs15_config(srs11_val, srs15_val);
- break;
+ } else {
+ mmio_write_8((cdns_params.reg_base + DTCV_OFFSET), DTCV_VAL);
+ }
- case SD_STOP_TRANSMISSION:
- op = CMD_STOP_ABORT_CMD;
- break;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS02, cmd->cmd_arg);
+ mmio_write_16((cdns_params.reg_base + CICE_OFFSET),
+ SDHCI_MAKE_CMD(cmd->cmd_idx, cmd_flags));
- case SD_SEND_STATUS:
- break;
+ timeout = TIMEOUT;
- case 1:
- cmd->cmd_arg = 0;
- break;
+ do {
+ udelay(CDNS_TIMEOUT);
+ status = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS12);
+ } while (((status & (INT_CMD_DONE | ERROR_INT)) == 0) && (timeout-- > 0));
- case SD_SELECT_CARD:
- op = MULTI_BLK_READ;
- break;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS12, (SRS_12_CC_EN));
+ status_check = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS12) & 0xffff8000;
+ if (status_check != 0U) {
+ timeout = TIMEOUT;
+ ERROR("SD host controller send command failed, SRS12 = %x", status_check);
+ return -1;
+ }
- case SD_APP_CMD:
- default:
- write_value = LEDC;
- prev_val = 0x0;
- cdns_srs10_value_toggle(write_value, prev_val);
- op = 0;
- break;
+ if (!((cmd_flags & RES_TYPE_SEL_NO) == 0)) {
+ cmd->resp_data[0] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS04);
+ if ((cmd_flags & RES_TYPE_SEL_NO) == RES_TYPE_SEL_136) {
+ cmd->resp_data[1] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS05);
+ cmd->resp_data[2] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS06);
+ cmd->resp_data[3] = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS07);
+ /* 136-bit: RTS=01b, Response field R[127:8] - RESP3[23:0],
+ * RESP2[31:0], RESP1[31:0], RESP0[31:0]
+ * Subsystem expects 128 bits response but cadence SDHC sends
+ * 120 bits response from R[127:8]. Bits manupulation to address
+ * the correct responses for the 136 bit response type.
+ */
+ cmd->resp_data[3] = ((cmd->resp_data[3] << 8) |
+ ((cmd->resp_data[2] >> 24) &
+ CDNS_CSD_BYTE_MASK));
+ cmd->resp_data[2] = ((cmd->resp_data[2] << 8) |
+ ((cmd->resp_data[1] >> 24) &
+ CDNS_CSD_BYTE_MASK));
+ cmd->resp_data[1] = ((cmd->resp_data[1] << 8) |
+ ((cmd->resp_data[0] >> 24) &
+ CDNS_CSD_BYTE_MASK));
+ cmd->resp_data[0] = (cmd->resp_data[0] << 8);
}
}
- switch (cmd->resp_type) {
- case MMC_RESPONSE_NONE:
- op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN;
- break;
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS12, (SRS_12_CC_EN));
- case MMC_RESPONSE_R2:
- op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN |
- RES_TYPE_SEL_136 | CMD_CHECK_RESP_CRC;
- break;
+ return 0;
+}
- case MMC_RESPONSE_R3:
- op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN |
- RES_TYPE_SEL_48;
- break;
+void sd_host_adma_prepare(struct cdns_idmac_desc *desc_ptr, uint64_t buf,
+ size_t size)
+{
+ uint32_t full_desc_cnt = 0;
+ uint32_t non_full_desc_cnt = 0;
+ uint64_t desc_address;
+ uint32_t block_count;
+ uint32_t transfer_block_size;
- case MMC_RESPONSE_R1:
- if ((cmd->cmd_idx == SD_WRITE_SINGLE_BLOCK) || (cmd->cmd_idx
- == SD_WRITE_MULTIPLE_BLOCK)) {
- op |= DMA_ENABLED | BLK_CNT_EN | RES_TYPE_SEL_48
- | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE;
- } else {
- op |= DMA_ENABLED | BLK_CNT_EN | CMD_READ | RES_TYPE_SEL_48
- | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE;
+ full_desc_cnt = (size / PAGE_BUFFER_LEN);
+ non_full_desc_cnt = (size % PAGE_BUFFER_LEN);
+ for (int i = 0; i < full_desc_cnt; i++) {
+ desc_ptr->attr = (ADMA_DESC_TRANSFER_DATA | ADMA_DESC_ATTR_VALID);
+ desc_ptr->len = 0; // 0 means 64kb page size it will take
+ desc_ptr->addr_lo = 0;
+#if CONFIG_DMA_ADDR_T_64BIT == 1
+ desc_ptr->addr_hi = (uint32_t)((buf >> 32) & 0xffffffff);
+#endif
+ if (non_full_desc_cnt == 0) {
+ desc_ptr->attr |= (ADMA_DESC_ATTR_END);
}
- break;
-
- default:
- op |= DMA_ENABLED | BLK_CNT_EN | CMD_READ | MULTI_BLK_READ |
- RES_TYPE_SEL_48 | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE;
- break;
+ buf += PAGE_BUFFER_LEN;
}
- timeout = TIMEOUT;
- do {
- udelay(100);
- ret = cdns_busy();
- if (--timeout <= 0) {
- udelay(50);
- panic();
+ if (non_full_desc_cnt != 0) {
+ desc_ptr->attr =
+ (ADMA_DESC_TRANSFER_DATA | ADMA_DESC_ATTR_END | ADMA_DESC_ATTR_VALID);
+ desc_ptr->addr_lo = buf & 0xffffffff;
+ desc_ptr->len = size;
+#if CONFIG_DMA_ADDR_T_64BIT == 1
+ desc_ptr->addr_hi = (uint32_t)((buf >> 32) & 0xffffffff);
+#endif
+ desc_address = (uint64_t)desc_ptr;
+ if (size > MMC_MAX_BLOCK_LEN) {
+ transfer_block_size = MMC_MAX_BLOCK_LEN;
+ } else {
+ transfer_block_size = size;
}
- } while (ret);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS12, UINT_MAX);
+ block_count = (size / transfer_block_size);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS01,
+ ((transfer_block_size << BLOCK_SIZE) | SDMA_BUF |
+ (block_count << BLK_COUNT_CT)));
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS22,
+ (uint32_t)desc_address & 0xFFFFFFFF);
+ mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS23,
+ (uint32_t)(desc_address >> 32 & 0xFFFFFFFF));
+ }
+}
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS02, cmd->cmd_arg);
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS14, 0x00000000);
- if (cmd_indx == 1)
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS03, SDHC_CDNS_SRS03_VALUE);
- else
- mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS03, op | cmd_indx);
+int cdns_mmc_init(struct cdns_sdmmc_params *params,
+ struct mmc_device_info *info)
+{
- timeout = TIMEOUT;
- do {
- udelay(500);
- value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS12);
- } while (((value & (INT_CMD_DONE | ERROR_INT)) == 0) && (timeout-- > 0));
+ int result = 0;
- timeout = TIMEOUT;
+ assert((params != NULL) &&
+ ((params->reg_base & MMC_BLOCK_MASK) == 0) &&
+ ((params->desc_size & MMC_BLOCK_MASK) == 0) &&
+ ((params->reg_pinmux & MMC_BLOCK_MASK) == 0) &&
+ ((params->reg_phy & MMC_BLOCK_MASK) == 0) &&
+ (params->desc_size > 0) &&
+ (params->clk_rate > 0) &&
+ ((params->bus_width == MMC_BUS_WIDTH_1) ||
+ (params->bus_width == MMC_BUS_WIDTH_4) ||
+ (params->bus_width == MMC_BUS_WIDTH_8)));
- if (data_cmd) {
- data_cmd = false;
- do {
- udelay(250);
- } while (((value & TRAN_COMP) == 0) && (timeout-- > 0));
- }
+ memcpy(&cdns_params, params, sizeof(struct cdns_sdmmc_params));
- status_check = value & SRS12_ERR_MASK;
- if (status_check != 0U) {
- ERROR("SD host controller send command failed, SRS12 = %x", status);
- return -1;
+ cdns_set_sdmmc_var(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
+ result = cdns_sd_host_init(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
+ if (result < 0) {
+ return result;
}
- if ((op & RES_TYPE_SEL_48) || (op & RES_TYPE_SEL_136)) {
- cmd->resp_data[0] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS04);
- if (op & RES_TYPE_SEL_136) {
- cmd->resp_data[1] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS05);
- cmd->resp_data[2] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS06);
- cmd->resp_data[3] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS07);
- }
- }
+ cdns_params.cdn_sdmmc_dev_type = info->mmc_dev_type;
+ cdns_params.cdn_sdmmc_dev_mode = SD_DS;
- return 0;
+ result = mmc_init(&cdns_sdmmc_ops, params->clk_rate, params->bus_width,
+ params->flags, info);
+
+ return result;
}
diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h
index 4be7414..f8d616f 100644
--- a/include/drivers/cadence/cdns_sdmmc.h
+++ b/include/drivers/cadence/cdns_sdmmc.h
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,23 +11,26 @@
#include <drivers/cadence/cdns_combo_phy.h>
#include <drivers/mmc.h>
-#include "socfpga_plat_def.h"
#if MMC_DEVICE_TYPE == 0
-#define CONFIG_DMA_ADDR_T_64BIT 0
+#define CONFIG_DMA_ADDR_T_64BIT 0
#endif
-#define MMC_REG_BASE SOCFPGA_MMC_REG_BASE
-#define COMBO_PHY_REG 0x0
-#define SDHC_EXTENDED_WR_MODE_MASK 0xFFFFFFF7
-#define SDHC_DLL_RESET_MASK 0x00000001
+#define MMC_REG_BASE SOCFPGA_MMC_REG_BASE
+#define COMBO_PHY_REG 0x0
+#define SDHC_EXTENDED_WR_MODE_MASK 0xFFFFFFF7
+#define SDHC_DLL_RESET_MASK 0x00000001
+#define MMC_MAX_BLOCK_LEN 512U
+
/* HRS09 */
#define SDHC_PHY_SW_RESET BIT(0)
-#define SDHC_PHY_INIT_COMPLETE BIT(1)
-#define SDHC_EXTENDED_RD_MODE(x) ((x) << 2)
+#define SDHC_PHY_INIT_COMPLETE BIT(1)
+#define SDHC_EXTENDED_RD_MODE(x) ((x) << 2)
#define EXTENDED_WR_MODE 3
-#define SDHC_EXTENDED_WR_MODE(x) ((x) << 3)
-#define RDCMD_EN 15
+#define SDHC_EXTENDED_WR_MODE(x) ((x) << 3)
+#define RDCMD_EN (3 << 15)
+#define PHY_SW_RESET_EN (1 << 0)
+#define PHY_INIT_COMPLETE_BIT (1 << 1)
#define SDHC_RDCMD_EN(x) ((x) << 15)
#define SDHC_RDDATA_EN(x) ((x) << 16)
@@ -38,9 +42,9 @@
/* • 1111b - Reserved */
/* • 1110b - t_sdmclk*2(27+2) */
/* • 1101b - t_sdmclk*2(26+2) */
-#define READ_CLK 0xa << 16
-#define WRITE_CLK 0xe << 16
-#define DTC_VAL 0xE
+#define READ_CLK 0xa << 16
+#define WRITE_CLK 0xe << 16
+#define DTC_VAL 0xE
/* SRS00 */
/* System Address / Argument 2 / 32-bit block count
@@ -49,18 +53,18 @@
* • SDMA system memory address
* • Auto CMD23 Argument
*/
-#define SAAR (1)
+#define SAAR (1)
/* SRS01 */
/* Transfer Block Size
* This field defines block size for block data transfers
*/
-#define BLOCK_SIZE 0
+#define BLOCK_SIZE 0
/* SDMA Buffer Boundary
* System address boundary can be set for SDMA engine.
*/
-#define SDMA_BUF 7 << 12
+#define SDMA_BUF 7 << 12
/* Block Count For Current Transfer
* To set the number of data blocks can be defined for next transfer
@@ -68,93 +72,108 @@
#define BLK_COUNT_CT 16
/* SRS03 */
-#define CMD_START (U(1) << 31)
+#define CMD_START (U(1) << 31)
#define CMD_USE_HOLD_REG (1 << 29)
#define CMD_UPDATE_CLK_ONLY (1 << 21)
#define CMD_SEND_INIT (1 << 15)
#define CMD_STOP_ABORT_CMD (4 << 22)
#define CMD_RESUME_CMD (2 << 22)
#define CMD_SUSPEND_CMD (1 << 22)
-#define DATA_PRESENT (1 << 21)
-#define CMD_IDX_CHK_ENABLE (1 << 20)
-#define CMD_WRITE (0 << 4)
-#define CMD_READ (1 << 4)
+#define DATA_PRESENT (0x20)
+#define CMD_IDX_CHK_ENABLE (0x10)
+#define CMD_WRITE (0 << 4)
+#define CMD_READ (1 << 4)
#define MULTI_BLK_READ (1 << 5)
-#define RESP_ERR (1 << 7)
-#define CMD_CHECK_RESP_CRC (1 << 19)
-#define RES_TYPE_SEL_48 (2 << 16)
-#define RES_TYPE_SEL_136 (1 << 16)
-#define RES_TYPE_SEL_48_B (3 << 16)
-#define RES_TYPE_SEL_NO (0 << 16)
-#define DMA_ENABLED (1 << 0)
-#define BLK_CNT_EN (1 << 1)
-#define AUTO_CMD_EN (2 << 2)
-#define COM_IDX 24
-#define ERROR_INT (1 << 15)
-#define INT_SBE (1 << 13)
-#define INT_HLE (1 << 12)
-#define INT_FRUN (1 << 11)
-#define INT_DRT (1 << 9)
-#define INT_RTO (1 << 8)
-#define INT_DCRC (1 << 7)
-#define INT_RCRC (1 << 6)
-#define INT_RXDR (1 << 5)
-#define INT_TXDR (1 << 4)
-#define INT_DTO (1 << 3)
+#define RESP_ERR (1 << 7)
+#define CMD_CHECK_RESP_CRC (0x08)
+#define RES_TYPE_SEL_48 (0x2)
+#define RES_TYPE_SEL_136 (0x1)
+#define RES_TYPE_SEL_48_B (0x3)
+#define RES_TYPE_SEL_NO (0x3)
+#define DMA_ENABLED (1 << 0)
+#define BLK_CNT_EN (1 << 1)
+#define AUTO_CMD_EN (2 << 2)
+#define COM_IDX 24
+#define ERROR_INT (1 << 15)
+#define INT_SBE (1 << 13)
+#define INT_HLE (1 << 12)
+#define INT_FRUN (1 << 11)
+#define INT_DRT (1 << 9)
+#define INT_RTO (1 << 8)
+#define INT_DCRC (1 << 7)
+#define INT_RCRC (1 << 6)
+#define INT_RXDR (1 << 5)
+#define INT_TXDR (1 << 4)
+#define INT_DTO (1 << 3)
#define INT_CMD_DONE (1 << 0)
-#define TRAN_COMP (1 << 1)
+#define TRAN_COMP (1 << 1)
/* SRS09 */
#define STATUS_DATA_BUSY BIT(2)
+#define CI 16
+#define CHECK_CARD BIT(CI)
/* SRS10 */
+#define BIT1 (0 << 1)
+#define BIT4 (1 << 1)
+#define BIT8 (1 << 5)
+
/* LED Control
* State of this bit directly drives led port of the host
* in order to control the external LED diode
* Default value 0 << 1
*/
-#define LEDC BIT(0)
-#define LEDC_OFF 0 << 1
+#define LEDC BIT(0)
+#define LEDC_OFF (0 << 1)
/* Data Transfer Width
* Bit used to configure DAT bus width to 1 or 4
* Default value 1 << 1
*/
-#define DT_WIDTH BIT(1)
-#define DTW_4BIT 1 << 1
+#define DT_WIDTH BIT(1)
+#define DTW_4BIT (1 << 1)
/* Extended Data Transfer Width
* This bit is to enable/disable 8-bit DAT bus width mode
* Default value 1 << 5
*/
-#define EDTW_8BIT 1 << 5
+#define EDTW_8BIT BIT(5)
/* High Speed Enable
* Selects operating mode to Default Speed (HSE=0) or High Speed (HSE=1)
*/
-#define HS_EN BIT(2)
+#define HS_EN BIT(2)
/* here 0 defines the 64 Kb size */
#define MAX_64KB_PAGE 0
-#define EMMC_DESC_SIZE (1<<20)
-
+#define EMMC_DESC_SIZE (1<<20)
+#define DTCV_OFFSET (0x22E)
+#define DTCV_VAL (0xE)
+#define CICE_OFFSET (0x20E)
+#define SRS_12_CC_EN (1 << 0)
/* SRS11 */
/* Software Reset For All
* When set to 1, the entire slot is reset
* After completing the reset operation, SRFA bit is automatically cleared
*/
-#define SRFA BIT(24)
+#define SRFA BIT(24)
/* Software Reset For CMD Line
* When set to 1, resets the logic related to the command generation and response checking
*/
-#define SRCMD BIT(25)
+#define SRCMD BIT(25)
/* Software Reset For DAT Line
* When set to 1, resets the logic related to the data path,
* including data buffers and the DMA logic
*/
-#define SRDAT BIT(26)
+#define SRDAT BIT(26)
+
+
+/* SRS12 */
+/* Error mask */
+#define SRS12_ERR_MASK 0xFFFF8000U
+#define CDNS_CSD_BYTE_MASK 0x000000FFU
/* SRS15 */
/* UHS Mode Select
@@ -165,40 +184,43 @@
* • 011b - SDR104
* • 100b - DDR50
*/
-#define SDR12_MODE 0 << 16
-#define SDR25_MODE 1 << 16
-#define SDR50_MODE 2 << 16
-#define SDR104_MODE 3 << 16
-#define DDR50_MODE 4 << 16
+#define SDR12_MODE 0 << 16
+#define SDR25_MODE 1 << 16
+#define SDR50_MODE 2 << 16
+#define SDR104_MODE 3 << 16
+#define DDR50_MODE 4 << 16
/* 1.8V Signaling Enable
* • 0 - for Default Speed, High Speed mode
* • 1 - for UHS-I mode
*/
-#define V18SE BIT(19)
+#define V18SE BIT(19)
/* CMD23 Enable
* In result of Card Identification process,
* Host Driver set this bit to 1 if Card supports CMD23
*/
-#define CMD23_EN BIT(27)
+#define CMD23_EN BIT(27)
/* Host Version 4.00 Enable
* • 0 - Version 3.00
* • 1 - Version 4.00
*/
-#define HV4E BIT(28)
+#define HV4E BIT(28)
/* Conf depends on SRS15.HV4E */
-#define SDMA 0 << 3
-#define ADMA2_32 2 << 3
-#define ADMA2_64 3 << 3
+#define SDMA 0 << 3
+#define ADMA2_32 2 << 3
+#define ADMA2_64 3 << 3
+#define DMA_SEL_BIT 3 << 3
+#define DMA_SEL_BIT_2 2 << 3
+#define DMA_SEL_BIT_3 3 << 3
/* Preset Value Enable
* Setting this bit to 1 triggers an automatically update of SRS11
*/
-#define PVE BIT(31)
+#define PVE BIT(31)
-#define BIT_AD_32 0 << 29
-#define BIT_AD_64 1 << 29
+#define BIT_AD_32 0 << 29
+#define BIT_AD_64 1 << 29
/* SW RESET REG*/
#define SDHC_CDNS_HRS00 (0x00)
@@ -206,7 +228,7 @@
/* PHY access port */
#define SDHC_CDNS_HRS04 0x10
-#define SDHC_CDNS_HRS04_ADDR GENMASK(5, 0)
+#define SDHC_CDNS_HRS04_ADDR GENMASK(5, 0)
/* PHY data access port */
#define SDHC_CDNS_HRS05 0x14
@@ -233,14 +255,51 @@
#define SDHC_CDNS_SRS13 0x234
#define SDHC_CDNS_SRS14 0x238
#define SDHC_CDNS_SRS15 0x23c
+#define SDHC_CDNS_SRS16 0x240
#define SDHC_CDNS_SRS21 0x254
#define SDHC_CDNS_SRS22 0x258
#define SDHC_CDNS_SRS23 0x25c
+#define SDHC_CDNS_SRS24 0x260
+#define SDHC_CDNS_SRS25 0x264
+
+/* SRS00 */
+#define SAAR (1)
+
+/* SRS03 */
+#define CMD_START (U(1) << 31)
+#define CMD_USE_HOLD_REG (1 << 29)
+#define CMD_UPDATE_CLK_ONLY (1 << 21)
+#define CMD_SEND_INIT (1 << 15)
+#define CMD_STOP_ABORT_CMD (4 << 22)
+#define CMD_RESUME_CMD (2 << 22)
+#define CMD_SUSPEND_CMD (1 << 22)
+#define DMA_ENABLED (1 << 0)
+#define BLK_CNT_EN (1 << 1)
+#define AUTO_CMD_EN (2 << 2)
+#define COM_IDX 24
+#define ERROR_INT (1 << 15)
+#define INT_SBE (1 << 13)
+#define INT_HLE (1 << 12)
+#define INT_FRUN (1 << 11)
+#define INT_DRT (1 << 9)
+#define INT_RTO (1 << 8)
+#define INT_DCRC (1 << 7)
+#define INT_RCRC (1 << 6)
+#define INT_RXDR (1 << 5)
+#define INT_TXDR (1 << 4)
+#define INT_DTO (1 << 3)
+#define INT_CMD_DONE (1 << 0)
+#define TRAN_COMP (1 << 1)
+#define CDNS_HOST_CMD_INHIBIT (BIT(0))
+#define CDNS_HOST_DATA_INHIBIT (BIT(1))
+#define ACE_CMD_12 (BIT(2))
+
+#define PAGE_BUFFER_LEN (64 * 1024)
/* HRS07 */
#define SDHC_CDNS_HRS07 0x1c
#define SDHC_IDELAY_VAL(x) ((x) << 0)
-#define SDHC_RW_COMPENSATE(x) ((x) << 16)
+#define SDHC_RW_COMPENSATE(x) ((x) << 16)
/* PHY reset port */
#define SDHC_CDNS_HRS09 0x24
@@ -254,49 +313,49 @@
/* Pinmux headers will reomove after ATF driver implementation */
#define PINMUX_SDMMC_SEL 0x0
-#define PIN0SEL 0x00
-#define PIN1SEL 0x04
-#define PIN2SEL 0x08
-#define PIN3SEL 0x0C
-#define PIN4SEL 0x10
-#define PIN5SEL 0x14
-#define PIN6SEL 0x18
-#define PIN7SEL 0x1C
-#define PIN8SEL 0x20
-#define PIN9SEL 0x24
-#define PIN10SEL 0x28
+#define PIN0SEL 0x00
+#define PIN1SEL 0x04
+#define PIN2SEL 0x08
+#define PIN3SEL 0x0C
+#define PIN4SEL 0x10
+#define PIN5SEL 0x14
+#define PIN6SEL 0x18
+#define PIN7SEL 0x1C
+#define PIN8SEL 0x20
+#define PIN9SEL 0x24
+#define PIN10SEL 0x28
/* HRS16 */
#define SDHC_WRCMD0_DLY(x) ((x) << 0)
#define SDHC_WRCMD1_DLY(x) ((x) << 4)
#define SDHC_WRDATA0_DLY(x) ((x) << 8)
#define SDHC_WRDATA1_DLY(x) ((x) << 12)
-#define SDHC_WRCMD0_SDCLK_DLY(x) ((x) << 16)
-#define SDHC_WRCMD1_SDCLK_DLY(x) ((x) << 20)
-#define SDHC_WRDATA0_SDCLK_DLY(x) ((x) << 24)
-#define SDHC_WRDATA1_SDCLK_DLY(x) ((x) << 28)
+#define SDHC_WRCMD0_SDCLK_DLY(x) ((x) << 16)
+#define SDHC_WRCMD1_SDCLK_DLY(x) ((x) << 20)
+#define SDHC_WRDATA0_SDCLK_DLY(x) ((x) << 24)
+#define SDHC_WRDATA1_SDCLK_DLY(x) ((x) << 28)
/* Shared Macros */
#define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \
(SDMMC_CDN_##_reg))
/* MMC Peripheral Definition */
-#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1))
-#define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000)
+#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1))
+#define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000)
#define MMC_RESPONSE_NONE 0
-#define SDHC_CDNS_SRS03_VALUE 0x01020013
+#define SDHC_CDNS_SRS03_VALUE 0x01020013
/* Value randomly chosen for eMMC RCA, it should be > 1 */
-#define MMC_FIX_RCA 6
+#define MMC_FIX_RCA 6
#define RCA_SHIFT_OFFSET 16
-#define CMD_EXTCSD_PARTITION_CONFIG 179
-#define CMD_EXTCSD_BUS_WIDTH 183
-#define CMD_EXTCSD_HS_TIMING 185
+#define CMD_EXTCSD_PARTITION_CONFIG 179
+#define CMD_EXTCSD_BUS_WIDTH 183
+#define CMD_EXTCSD_HS_TIMING 185
#define CMD_EXTCSD_SEC_CNT 212
-#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
-#define PART_CFG_PARTITION1_ACCESS (U(1) << 0)
+#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
+#define PART_CFG_PARTITION1_ACCESS (U(1) << 0)
/* Values in EXT CSD register */
#define MMC_BUS_WIDTH_1 U(0)
@@ -304,8 +363,8 @@
#define MMC_BUS_WIDTH_8 U(2)
#define MMC_BUS_WIDTH_DDR_4 U(5)
#define MMC_BUS_WIDTH_DDR_8 U(6)
-#define MMC_BOOT_MODE_BACKWARD (U(0) << 3)
-#define MMC_BOOT_MODE_HS_TIMING (U(1) << 3)
+#define MMC_BOOT_MODE_BACKWARD (U(0) << 3)
+#define MMC_BOOT_MODE_HS_TIMING (U(1) << 3)
#define MMC_BOOT_MODE_DDR (U(2) << 3)
#define EXTCSD_SET_CMD (U(0) << 24)
@@ -314,14 +373,14 @@
#define EXTCSD_WRITE_BYTES (U(3) << 24)
#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
-#define EXTCSD_CMD_SET_NORMAL U(1)
+#define EXTCSD_CMD_SET_NORMAL U(1)
-#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
-#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
-#define CSD_TRAN_SPEED_MULT_SHIFT 3
+#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
+#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
+#define CSD_TRAN_SPEED_MULT_SHIFT 3
-#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
-#define STATUS_READY_FOR_DATA BIT(8)
+#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
+#define STATUS_READY_FOR_DATA BIT(8)
#define STATUS_SWITCH_ERROR BIT(7)
#define MMC_GET_STATE(x) (((x) >> 9) & 0xf)
#define MMC_STATE_IDLE 0
@@ -342,12 +401,51 @@
#define VHS_2_7_3_6_V BIT(8)
/*ADMA table component*/
-#define ADMA_DESC_ATTR_VALID BIT(0)
+#define ADMA_DESC_ATTR_VALID BIT(0)
#define ADMA_DESC_ATTR_END BIT(1)
#define ADMA_DESC_ATTR_INT BIT(2)
#define ADMA_DESC_ATTR_ACT1 BIT(4)
#define ADMA_DESC_ATTR_ACT2 BIT(5)
-#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
+#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
+
+#define HRS_09_EXTENDED_RD_MODE (1 << 2)
+#define HRS_09_EXTENDED_WR_MODE (1 << 3)
+#define HRS_09_RDCMD_EN (1 << 15)
+#define HRS_09_RDDATA_EN (1 << 16)
+#define HRS_10_HCSDCLKADJ_VAL (3)
+
+#define SRS11_SRFA (1 << 24)
+#define SRS11_SRFA_CHK(x) (x >> 24)
+#define CDNS_TIMEOUT (5000)
+
+#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
+
+/* Card busy and present */
+#define CARD_BUSY 1
+#define CARD_NOT_BUSY 0
+
+/* 500 ms delay to read the RINST register */
+#define DELAY_MS_SRS_READ 500
+#define DELAY_RES 10
+
+/* Check DV dfi_init val=0 */
+#define IO_MASK_END_DATA 0x0
+
+/* Check DV dfi_init val=2; DDR Mode */
+#define IO_MASK_END_DATA_DDR 0x2
+#define IO_MASK_START_DATA 0x0
+#define DATA_SELECT_OE_END_DATA 0x1
+
+#define TIMEOUT 100000
+
+/* General define */
+#define SDHC_REG_MASK UINT_MAX
+#define SD_HOST_BLOCK_SIZE 0x200
+#define DTCVVAL_DEFAULT_VAL 0xE
+#define CDMMC_DMA_MAX_BUFFER_SIZE 64*1024
+#define CDNSMMC_ADDRESS_MASK U(0x0f)
+#define CONFIG_CDNS_DESC_COUNT 8
+#define SD_HOST_CLK 200000000
enum sd_opcode {
SD_GO_IDLE_STATE = 0,
@@ -388,6 +486,16 @@
SD_APP_SEND_SCR = 51,
};
+enum sd_opr_modes {
+ SD_HOST_OPR_MODE_HV4E_0_SDMA_32 = 0,
+ SD_HOST_OPR_MODE_HV4E_1_SDMA_32,
+ SD_HOST_OPR_MODE_HV4E_1_SDMA_64,
+ SD_HOST_OPR_MODE_HV4E_0_ADMA_32,
+ SD_HOST_OPR_MODE_HV4E_0_ADMA_64,
+ SD_HOST_OPR_MODE_HV4E_1_ADMA_32,
+ SD_HOST_OPR_MODE_HV4E_1_ADMA_64,
+};
+
struct cdns_sdmmc_sdhc {
uint32_t sdhc_extended_rd_mode;
uint32_t sdhc_extended_wr_mode;
@@ -439,9 +547,6 @@
uint32_t combophy;
};
-/* read and write API */
-size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size);
-size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size);
struct cdns_idmac_desc {
/*8 bit attribute*/
@@ -467,4 +572,8 @@
struct cdns_sdmmc_sdhc *mmc_sdhc_reg);
void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg,
struct cdns_sdmmc_sdhc *sdhc_reg);
+int cdns_mmc_init(struct cdns_sdmmc_params *params, struct mmc_device_info *info);
+int cdns_program_phy_reg(struct cdns_sdmmc_combo_phy *combo_phy_reg,
+ struct cdns_sdmmc_sdhc *sdhc_reg);
+void cdns_host_set_clk(uint32_t clk);
#endif
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index 94fed3a..22be419 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -35,12 +35,24 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
+/* FIP Setting */
+#define PLAT_FIP_BASE (0)
+#if ARM_LINUX_KERNEL_AS_BL33
+#define PLAT_FIP_MAX_SIZE (0x8000000)
+#else
+#define PLAT_FIP_MAX_SIZE (0x1000000)
+#endif
+
/* SDMMC Setting */
-# if ARM_LINUX_KERNEL_AS_BL33
+#if ARM_LINUX_KERNEL_AS_BL33
+#define PLAT_MMC_DATA_BASE (0x10000000)
+#define PLAT_MMC_DATA_SIZE (0x100000)
#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
-# else
+#else
+#define PLAT_MMC_DATA_BASE (0xffe3c000)
+#define PLAT_MMC_DATA_SIZE (0x2000
#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
-# endif
+#endif
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
@@ -112,7 +124,7 @@
/*******************************************************************************
* SDMMC related pointer function
******************************************************************************/
-#define SDMMC_READ_BLOCKS mmc_read_blocks
+#define SDMMC_READ_BLOCKS sdmmc_read_blocks
#define SDMMC_WRITE_BLOCKS mmc_write_blocks
/*******************************************************************************
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index 21cc6a3..2f0fc17 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -28,6 +28,7 @@
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S \
plat/intel/soc/common/drivers/ccu/ncore_ccu.c \
+ plat/intel/soc/common/drivers/sdmmc/sdmmc.c \
plat/intel/soc/common/lib/sha/sha.c \
plat/intel/soc/common/socfpga_delay_timer.c
diff --git a/plat/intel/soc/agilex5/bl2_plat_setup.c b/plat/intel/soc/agilex5/bl2_plat_setup.c
index 78a4889..fe5dc6e 100644
--- a/plat/intel/soc/agilex5/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl2_plat_setup.c
@@ -103,6 +103,15 @@
/* Configure the pinmux */
config_pinmux(&reverse_handoff_ptr);
+ /* Configure OCRAM to NON SECURE ACCESS */
+ mmio_write_32(OCRAM_REGION_0_REG_BASE, OCRAM_NON_SECURE_ENABLE);
+ mmio_write_32(SOCFPGA_L4_PER_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT,
+ SOCFPGA_SDMMC_SECU_BIT_ENABLE);
+ mmio_write_32(SOCFPGA_L4_SYS_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT,
+ SOCFPGA_SDMMC_SECU_BIT_ENABLE);
+ mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE,
+ SOCFPGA_LWSOC2FPGA_ENABLE);
+
/* Configure the clock manager */
if ((config_clkmgr_handoff(&reverse_handoff_ptr)) != 0) {
ERROR("SOCFPGA: Failed to initialize the clock manager\n");
@@ -157,7 +166,7 @@
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
NOTICE("SDMMC boot\n");
- sdmmc_init(&reverse_handoff_ptr, ¶ms, &mmc_info);
+ cdns_mmc_init(¶ms, &mmc_info);
socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
break;
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
index 3a0aea1..3e98c28 100644
--- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -46,12 +46,24 @@
#define CAD_QSPIDATA_OFST 0x10900000
#define CAD_QSPI_OFFSET 0x108d2000
+/* FIP Setting */
+#define PLAT_FIP_BASE (0)
+#if ARM_LINUX_KERNEL_AS_BL33
+#define PLAT_FIP_MAX_SIZE (0x8000000)
+#else
+#define PLAT_FIP_MAX_SIZE (0x1000000)
+#endif
+
/* SDMMC Setting */
-# if ARM_LINUX_KERNEL_AS_BL33
+#if ARM_LINUX_KERNEL_AS_BL33
+#define PLAT_MMC_DATA_BASE (0x90000000)
+#define PLAT_MMC_DATA_SIZE (0x100000)
#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
-# else
+#else
+#define PLAT_MMC_DATA_BASE (0x0007D000)
+#define PLAT_MMC_DATA_SIZE (0x2000)
#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
-# endif
+#endif
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000
@@ -69,10 +81,22 @@
#define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100
#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200
#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300
+#define SOCFPGA_SDMMC_SECU_BIT 0x40
+#define SOCFPGA_LWSOC2FPGA_ENABLE 0xffe0301
+#define SOCFPGA_SDMMC_SECU_BIT_ENABLE 0x1010001
+
/* Define maximum page size for NAND flash devices */
#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x2000)
+/* OCRAM Register*/
+
+#define OCRAM_REG_BASE 0x108CC400
+#define OCRAM_REGION_0_OFFSET 0x18
+#define OCRAM_REGION_0_REG_BASE (OCRAM_REG_BASE + \
+ OCRAM_REGION_0_OFFSET)
+#define OCRAM_NON_SECURE_ENABLE 0x0
+
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
diff --git a/plat/intel/soc/common/drivers/sdmmc/sdmmc.c b/plat/intel/soc/common/drivers/sdmmc/sdmmc.c
index 48f91eb..62698a9 100644
--- a/plat/intel/soc/common/drivers/sdmmc/sdmmc.c
+++ b/plat/intel/soc/common/drivers/sdmmc/sdmmc.c
@@ -18,53 +18,26 @@
#include <lib/mmio.h>
#include <lib/utils.h>
-#include "agilex5_pinmux.h"
#include "sdmmc.h"
#include "socfpga_mailbox.h"
+#include "wdt/watchdog.h"
static const struct mmc_ops *ops;
static unsigned int mmc_ocr_value;
-static struct mmc_csd_emmc mmc_csd;
-static struct sd_switch_status sd_switch_func_status;
-static unsigned char mmc_ext_csd[512] __aligned(16);
static unsigned int mmc_flags;
-static struct mmc_device_info *mmc_dev_info;
static unsigned int rca;
-static unsigned int scr[2]__aligned(16) = { 0 };
extern const struct mmc_ops cdns_sdmmc_ops;
extern struct cdns_sdmmc_params cdns_params;
extern struct cdns_sdmmc_combo_phy sdmmc_combo_phy_reg;
extern struct cdns_sdmmc_sdhc sdmmc_sdhc_reg;
-static bool is_cmd23_enabled(void)
+bool is_cmd23_enabled(void)
{
return ((mmc_flags & MMC_FLAG_CMD23) != 0U);
}
-static bool is_sd_cmd6_enabled(void)
-{
- return ((mmc_flags & MMC_FLAG_SD_CMD6) != 0U);
-}
-
-/* TODO: Will romove once ATF driver is developed */
-void sdmmc_pin_config(void)
-{
- /* temp use base + addr. Official must change to common method */
- mmio_write_32(AGX5_PINMUX_PIN0SEL+0x00, 0x0);
- mmio_write_32(AGX5_PINMUX_PIN0SEL+0x04, 0x0);
- mmio_write_32(AGX5_PINMUX_PIN0SEL+0x08, 0x0);
- mmio_write_32(AGX5_PINMUX_PIN0SEL+0x0C, 0x0);
- mmio_write_32(AGX5_PINMUX_PIN0SEL+0x10, 0x0);
- mmio_write_32(AGX5_PINMUX_PIN0SEL+0x14, 0x0);
- mmio_write_32(AGX5_PINMUX_PIN0SEL+0x18, 0x0);
- mmio_write_32(AGX5_PINMUX_PIN0SEL+0x1C, 0x0);
- mmio_write_32(AGX5_PINMUX_PIN0SEL+0x20, 0x0);
- mmio_write_32(AGX5_PINMUX_PIN0SEL+0x24, 0x0);
- mmio_write_32(AGX5_PINMUX_PIN0SEL+0x28, 0x0);
-}
-
-static int sdmmc_send_cmd(unsigned int idx, unsigned int arg,
+int sdmmc_send_cmd(unsigned int idx, unsigned int arg,
unsigned int r_type, unsigned int *r_data)
{
struct mmc_cmd cmd;
@@ -94,7 +67,7 @@
return ret;
}
-static int sdmmc_device_state(void)
+int sdmmc_device_state(void)
{
int retries = DEFAULT_SDMMC_MAX_RETRIES;
unsigned int resp_data[4];
@@ -125,521 +98,12 @@
return MMC_GET_STATE(resp_data[0]);
}
-static int sdmmc_set_ext_csd(unsigned int ext_cmd, unsigned int value)
-{
- int ret;
-
- ret = sdmmc_send_cmd(MMC_CMD(6),
- EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) |
- EXTCSD_VALUE(value) | EXTCSD_CMD_SET_NORMAL,
- MMC_RESPONSE_R1B, NULL);
- if (ret != 0) {
- return ret;
- }
-
- do {
- ret = sdmmc_device_state();
- if (ret < 0) {
- return ret;
- }
- } while (ret == MMC_STATE_PRG);
-
- return 0;
-}
-
-static int sdmmc_mmc_sd_switch(unsigned int bus_width)
-{
- int ret;
- int retries = DEFAULT_SDMMC_MAX_RETRIES;
- unsigned int bus_width_arg = 0;
-
- /* CMD55: Application Specific Command */
- ret = sdmmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET,
- MMC_RESPONSE_R5, NULL);
- if (ret != 0) {
- return ret;
- }
-
- ret = ops->prepare(0, (uintptr_t)&scr, sizeof(scr));
- if (ret != 0) {
- return ret;
- }
-
- /* ACMD51: SEND_SCR */
- do {
- ret = sdmmc_send_cmd(MMC_ACMD(51), 0, MMC_RESPONSE_R1, NULL);
- if ((ret != 0) && (retries == 0)) {
- ERROR("ACMD51 failed after %d retries (ret=%d)\n",
- DEFAULT_SDMMC_MAX_RETRIES, ret);
- return ret;
- }
-
- retries--;
- } while (ret != 0);
-
- ret = ops->read(0, (uintptr_t)&scr, sizeof(scr));
- if (ret != 0) {
- return ret;
- }
-
- if (((scr[0] & SD_SCR_BUS_WIDTH_4) != 0U) &&
- (bus_width == MMC_BUS_WIDTH_4)) {
- bus_width_arg = 2;
- }
-
- /* CMD55: Application Specific Command */
- ret = sdmmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET,
- MMC_RESPONSE_R5, NULL);
- if (ret != 0) {
- return ret;
- }
-
- /* ACMD6: SET_BUS_WIDTH */
- ret = sdmmc_send_cmd(MMC_ACMD(6), bus_width_arg, MMC_RESPONSE_R1, NULL);
- if (ret != 0) {
- return ret;
- }
-
- do {
- ret = sdmmc_device_state();
- if (ret < 0) {
- return ret;
- }
- } while (ret == MMC_STATE_PRG);
-
- return 0;
-}
-
-static int sdmmc_set_ios(unsigned int clk, unsigned int bus_width)
-{
- int ret;
- unsigned int width = bus_width;
-
- if (mmc_dev_info->mmc_dev_type != MMC_IS_EMMC) {
- if (width == MMC_BUS_WIDTH_8) {
- WARN("Wrong bus config for SD-card, force to 4\n");
- width = MMC_BUS_WIDTH_4;
- }
- ret = sdmmc_mmc_sd_switch(width);
- if (ret != 0) {
- return ret;
- }
- } else if (mmc_csd.spec_vers == 4U) {
- ret = sdmmc_set_ext_csd(CMD_EXTCSD_BUS_WIDTH,
- (unsigned int)width);
- if (ret != 0) {
- return ret;
- }
- } else {
- VERBOSE("Wrong MMC type or spec version\n");
- }
-
- return ops->set_ios(clk, width);
-}
-
-static int sdmmc_fill_device_info(void)
-{
- unsigned long long c_size;
- unsigned int speed_idx;
- unsigned int nb_blocks;
- unsigned int freq_unit;
- int ret = 0;
- struct mmc_csd_sd_v2 *csd_sd_v2;
-
- switch (mmc_dev_info->mmc_dev_type) {
- case MMC_IS_EMMC:
- mmc_dev_info->block_size = MMC_BLOCK_SIZE;
-
- ret = ops->prepare(0, (uintptr_t)&mmc_ext_csd,
- sizeof(mmc_ext_csd));
- if (ret != 0) {
- return ret;
- }
-
- /* MMC CMD8: SEND_EXT_CSD */
- ret = sdmmc_send_cmd(MMC_CMD(8), 0, MMC_RESPONSE_R1, NULL);
- if (ret != 0) {
- return ret;
- }
-
- ret = ops->read(0, (uintptr_t)&mmc_ext_csd,
- sizeof(mmc_ext_csd));
- if (ret != 0) {
- return ret;
- }
-
- do {
- ret = sdmmc_device_state();
- if (ret < 0) {
- return ret;
- }
- } while (ret != MMC_STATE_TRAN);
-
- nb_blocks = (mmc_ext_csd[CMD_EXTCSD_SEC_CNT] << 0) |
- (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 1] << 8) |
- (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 2] << 16) |
- (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 3] << 24);
-
- mmc_dev_info->device_size = (unsigned long long)nb_blocks *
- mmc_dev_info->block_size;
-
- break;
-
- case MMC_IS_SD:
- /*
- * Use the same mmc_csd struct, as required fields here
- * (READ_BL_LEN, C_SIZE, CSIZE_MULT) are common with eMMC.
- */
- mmc_dev_info->block_size = BIT_32(mmc_csd.read_bl_len);
-
- c_size = ((unsigned long long)mmc_csd.c_size_high << 2U) |
- (unsigned long long)mmc_csd.c_size_low;
- assert(c_size != 0xFFFU);
-
- mmc_dev_info->device_size = (c_size + 1U) *
- BIT_64(mmc_csd.c_size_mult + 2U) *
- mmc_dev_info->block_size;
-
- break;
-
- case MMC_IS_SD_HC:
- assert(mmc_csd.csd_structure == 1U);
-
- mmc_dev_info->block_size = MMC_BLOCK_SIZE;
-
- /* Need to use mmc_csd_sd_v2 struct */
- csd_sd_v2 = (struct mmc_csd_sd_v2 *)&mmc_csd;
- c_size = ((unsigned long long)csd_sd_v2->c_size_high << 16) |
- (unsigned long long)csd_sd_v2->c_size_low;
-
- mmc_dev_info->device_size = (c_size + 1U) << SDMMC_MULT_BY_512K_SHIFT;
-
- break;
-
- default:
- ret = -EINVAL;
- break;
- }
-
- if (ret < 0) {
- return ret;
- }
-
- speed_idx = (mmc_csd.tran_speed & CSD_TRAN_SPEED_MULT_MASK) >>
- CSD_TRAN_SPEED_MULT_SHIFT;
-
- assert(speed_idx > 0U);
-
- if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
- mmc_dev_info->max_bus_freq = tran_speed_base[speed_idx];
- } else {
- mmc_dev_info->max_bus_freq = sd_tran_speed_base[speed_idx];
- }
-
- freq_unit = mmc_csd.tran_speed & CSD_TRAN_SPEED_UNIT_MASK;
- while (freq_unit != 0U) {
- mmc_dev_info->max_bus_freq *= 10U;
- --freq_unit;
- }
-
- mmc_dev_info->max_bus_freq *= 10000U;
-
- return 0;
-}
-
-static int sdmmc_sd_switch(unsigned int mode, unsigned char group,
- unsigned char func)
-{
- unsigned int group_shift = (group - 1U) * 4U;
- unsigned int group_mask = GENMASK(group_shift + 3U, group_shift);
- unsigned int arg;
- int ret;
-
- ret = ops->prepare(0, (uintptr_t)&sd_switch_func_status,
- sizeof(sd_switch_func_status));
- if (ret != 0) {
- return ret;
- }
-
- /* MMC CMD6: SWITCH_FUNC */
- arg = mode | SD_SWITCH_ALL_GROUPS_MASK;
- arg &= ~group_mask;
- arg |= func << group_shift;
- ret = sdmmc_send_cmd(MMC_CMD(6), arg, MMC_RESPONSE_R1, NULL);
- if (ret != 0) {
- return ret;
- }
-
- return ops->read(0, (uintptr_t)&sd_switch_func_status,
- sizeof(sd_switch_func_status));
-}
-
-static int sdmmc_sd_send_op_cond(void)
-{
- int n;
- unsigned int resp_data[4];
-
- for (n = 0; n < SEND_SDMMC_OP_COND_MAX_RETRIES; n++) {
- int ret;
-
- /* CMD55: Application Specific Command */
- ret = sdmmc_send_cmd(MMC_CMD(55), 0, MMC_RESPONSE_R1, NULL);
- if (ret != 0) {
- return ret;
- }
-
- /* ACMD41: SD_SEND_OP_COND */
- ret = sdmmc_send_cmd(MMC_ACMD(41), OCR_HCS |
- mmc_dev_info->ocr_voltage, MMC_RESPONSE_R3,
- &resp_data[0]);
- if (ret != 0) {
- return ret;
- }
-
- if ((resp_data[0] & OCR_POWERUP) != 0U) {
- mmc_ocr_value = resp_data[0];
-
- if ((mmc_ocr_value & OCR_HCS) != 0U) {
- mmc_dev_info->mmc_dev_type = MMC_IS_SD_HC;
- } else {
- mmc_dev_info->mmc_dev_type = MMC_IS_SD;
- }
-
- return 0;
- }
-
- mdelay(10);
- }
-
- ERROR("ACMD41 failed after %d retries\n", SEND_SDMMC_OP_COND_MAX_RETRIES);
-
- return -EIO;
-}
-
-static int sdmmc_reset_to_idle(void)
-{
- int ret;
-
- /* CMD0: reset to IDLE */
- ret = sdmmc_send_cmd(MMC_CMD(0), 0, 0, NULL);
- if (ret != 0) {
- return ret;
- }
-
- mdelay(2);
-
- return 0;
-}
-
-static int sdmmc_send_op_cond(void)
-{
- int ret, n;
- unsigned int resp_data[4];
-
- ret = sdmmc_reset_to_idle();
- if (ret != 0) {
- return ret;
- }
-
- for (n = 0; n < SEND_SDMMC_OP_COND_MAX_RETRIES; n++) {
- ret = sdmmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE |
- OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7,
- MMC_RESPONSE_R3, &resp_data[0]);
- if (ret != 0) {
- return ret;
- }
-
- if ((resp_data[0] & OCR_POWERUP) != 0U) {
- mmc_ocr_value = resp_data[0];
- return 0;
- }
-
- mdelay(10);
- }
-
- ERROR("CMD1 failed after %d retries\n", SEND_SDMMC_OP_COND_MAX_RETRIES);
-
- return -EIO;
-}
-
-static int sdmmc_enumerate(unsigned int clk, unsigned int bus_width)
-{
- int ret;
- unsigned int resp_data[4];
-
- ops->init();
-
- ret = sdmmc_reset_to_idle();
- if (ret != 0) {
- return ret;
- }
-
- if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
- ret = sdmmc_send_op_cond();
- } else {
- /* CMD8: Send Interface Condition Command */
- ret = sdmmc_send_cmd(MMC_CMD(8), VHS_2_7_3_6_V | CMD8_CHECK_PATTERN,
- MMC_RESPONSE_R5, &resp_data[0]);
-
- if ((ret == 0) && ((resp_data[0] & 0xffU) == CMD8_CHECK_PATTERN)) {
- ret = sdmmc_sd_send_op_cond();
- }
- }
- if (ret != 0) {
- return ret;
- }
-
- /* CMD2: Card Identification */
- ret = sdmmc_send_cmd(MMC_CMD(2), 0, MMC_RESPONSE_R2, NULL);
- if (ret != 0) {
- return ret;
- }
-
- /* CMD3: Set Relative Address */
- if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
- rca = MMC_FIX_RCA;
- ret = sdmmc_send_cmd(MMC_CMD(3), rca << RCA_SHIFT_OFFSET,
- MMC_RESPONSE_R1, NULL);
- if (ret != 0) {
- return ret;
- }
- } else {
- ret = sdmmc_send_cmd(MMC_CMD(3), 0,
- MMC_RESPONSE_R6, &resp_data[0]);
- if (ret != 0) {
- return ret;
- }
-
- rca = (resp_data[0] & 0xFFFF0000U) >> 16;
- }
-
- /* CMD9: CSD Register */
- ret = sdmmc_send_cmd(MMC_CMD(9), rca << RCA_SHIFT_OFFSET,
- MMC_RESPONSE_R2, &resp_data[0]);
- if (ret != 0) {
- return ret;
- }
-
- memcpy_s(&mmc_csd, sizeof(mmc_csd) / MBOX_WORD_BYTE,
- &resp_data, sizeof(resp_data) / MBOX_WORD_BYTE);
-
- /* CMD7: Select Card */
- ret = sdmmc_send_cmd(MMC_CMD(7), rca << RCA_SHIFT_OFFSET,
- MMC_RESPONSE_R1, NULL);
- if (ret != 0) {
- return ret;
- }
-
- do {
- ret = sdmmc_device_state();
- if (ret < 0) {
- return ret;
- }
- } while (ret != MMC_STATE_TRAN);
-
- ret = sdmmc_set_ios(clk, bus_width);
- if (ret != 0) {
- return ret;
- }
-
- ret = sdmmc_fill_device_info();
- if (ret != 0) {
- return ret;
- }
-
- if (is_sd_cmd6_enabled() &&
- (mmc_dev_info->mmc_dev_type == MMC_IS_SD_HC)) {
- /* Try to switch to High Speed Mode */
- ret = sdmmc_sd_switch(SD_SWITCH_FUNC_CHECK, 1U, 1U);
- if (ret != 0) {
- return ret;
- }
-
- if ((sd_switch_func_status.support_g1 & BIT(9)) == 0U) {
- /* High speed not supported, keep default speed */
- return 0;
- }
-
- ret = sdmmc_sd_switch(SD_SWITCH_FUNC_SWITCH, 1U, 1U);
- if (ret != 0) {
- return ret;
- }
-
- if ((sd_switch_func_status.sel_g2_g1 & 0x1U) == 0U) {
- /* Cannot switch to high speed, keep default speed */
- return 0;
- }
-
- mmc_dev_info->max_bus_freq = 50000000U;
- ret = ops->set_ios(clk, bus_width);
- }
-
- return ret;
-}
-
size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size)
{
- int ret;
- unsigned int cmd_idx, cmd_arg;
-
- assert((ops != NULL) &&
- (ops->read != NULL) &&
- (size != 0U) &&
- ((size & MMC_BLOCK_MASK) == 0U));
-
- ret = ops->prepare(lba, buf, size);
- if (ret != 0) {
- return 0;
- }
-
- if (is_cmd23_enabled()) {
- /* Set block count */
- ret = sdmmc_send_cmd(MMC_CMD(23), size / MMC_BLOCK_SIZE,
- MMC_RESPONSE_R1, NULL);
- if (ret != 0) {
- return 0;
- }
-
- cmd_idx = MMC_CMD(18);
- } else {
- if (size > MMC_BLOCK_SIZE) {
- cmd_idx = MMC_CMD(18);
- } else {
- cmd_idx = MMC_CMD(17);
- }
- }
-
- if (((mmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE) &&
- (mmc_dev_info->mmc_dev_type != MMC_IS_SD_HC)) {
- cmd_arg = lba * MMC_BLOCK_SIZE;
- } else {
- cmd_arg = lba;
- }
+ mmc_read_blocks(lba, buf, size);
- ret = sdmmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R1, NULL);
- if (ret != 0) {
- return 0;
- }
-
- ret = ops->read(lba, buf, size);
- if (ret != 0) {
- return 0;
- }
-
- /* Wait buffer empty */
- do {
- ret = sdmmc_device_state();
- if (ret < 0) {
- return 0;
- }
- } while ((ret != MMC_STATE_TRAN) && (ret != MMC_STATE_DATA));
-
- if (!is_cmd23_enabled() && (size > MMC_BLOCK_SIZE)) {
- ret = sdmmc_send_cmd(MMC_CMD(12), 0, MMC_RESPONSE_R1B, NULL);
- if (ret != 0) {
- return 0;
- }
- }
+ /* Restart watchdog for reading each chunk byte */
+ watchdog_sw_rst();
return size;
}
@@ -710,64 +174,3 @@
return size;
}
-
-int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
- unsigned int width, unsigned int flags,
- struct mmc_device_info *device_info)
-{
- assert((ops_ptr != NULL) &&
- (ops_ptr->init != NULL) &&
- (ops_ptr->send_cmd != NULL) &&
- (ops_ptr->set_ios != NULL) &&
- (ops_ptr->prepare != NULL) &&
- (ops_ptr->read != NULL) &&
- (ops_ptr->write != NULL) &&
- (device_info != NULL) &&
- (clk != 0) &&
- ((width == MMC_BUS_WIDTH_1) ||
- (width == MMC_BUS_WIDTH_4) ||
- (width == MMC_BUS_WIDTH_8) ||
- (width == MMC_BUS_WIDTH_DDR_4) ||
- (width == MMC_BUS_WIDTH_DDR_8)));
-
- ops = ops_ptr;
- mmc_flags = flags;
- mmc_dev_info = device_info;
-
- return sdmmc_enumerate(clk, width);
-}
-
-int sdmmc_init(handoff *hoff_ptr, struct cdns_sdmmc_params *params, struct mmc_device_info *info)
-{
- int result = 0;
-
- /* SDMMC pin mux configuration */
- sdmmc_pin_config();
- cdns_set_sdmmc_var(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
- result = cdns_sd_host_init(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
- if (result < 0) {
- return result;
- }
-
- assert((params != NULL) &&
- ((params->reg_base & MMC_BLOCK_MASK) == 0) &&
- ((params->desc_base & MMC_BLOCK_MASK) == 0) &&
- ((params->desc_size & MMC_BLOCK_MASK) == 0) &&
- ((params->reg_pinmux & MMC_BLOCK_MASK) == 0) &&
- ((params->reg_phy & MMC_BLOCK_MASK) == 0) &&
- (params->desc_size > 0) &&
- (params->clk_rate > 0) &&
- ((params->bus_width == MMC_BUS_WIDTH_1) ||
- (params->bus_width == MMC_BUS_WIDTH_4) ||
- (params->bus_width == MMC_BUS_WIDTH_8)));
-
- memcpy_s(&cdns_params, sizeof(struct cdns_sdmmc_params) / MBOX_WORD_BYTE,
- params, sizeof(struct cdns_sdmmc_params) / MBOX_WORD_BYTE);
- cdns_params.cdn_sdmmc_dev_type = info->mmc_dev_type;
- cdns_params.cdn_sdmmc_dev_mode = SD_DS;
-
- result = sd_or_mmc_init(&cdns_sdmmc_ops, params->clk_rate, params->bus_width,
- params->flags, info);
-
- return result;
-}
diff --git a/plat/intel/soc/common/drivers/sdmmc/sdmmc.h b/plat/intel/soc/common/drivers/sdmmc/sdmmc.h
index 16c6b04..3f6119c 100644
--- a/plat/intel/soc/common/drivers/sdmmc/sdmmc.h
+++ b/plat/intel/soc/common/drivers/sdmmc/sdmmc.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,10 +34,12 @@
* @hoff_ptr: Pointer to the hand-off data
* Return: 0 on success, a negative errno on failure
*/
-int sdmmc_init(handoff *hoff_ptr, struct cdns_sdmmc_params *params,
- struct mmc_device_info *info);
-int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
- unsigned int width, unsigned int flags,
- struct mmc_device_info *device_info);
void sdmmc_pin_config(void);
+size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size);
+size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size);
+int sdmmc_device_state(void);
+bool is_cmd23_enabled(void);
+int sdmmc_send_cmd(unsigned int idx, unsigned int arg,
+ unsigned int r_type, unsigned int *r_data);
+
#endif
diff --git a/plat/intel/soc/common/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c
index 7679f59..66b5216 100644
--- a/plat/intel/soc/common/socfpga_storage.c
+++ b/plat/intel/soc/common/socfpga_storage.c
@@ -22,22 +22,12 @@
#include <drivers/partition/partition.h>
#include <lib/mmio.h>
#include <tools_share/firmware_image_package.h>
+
#include "drivers/sdmmc/sdmmc.h"
#include "socfpga_private.h"
#include "socfpga_ros.h"
-#define PLAT_FIP_BASE (0)
-# if ARM_LINUX_KERNEL_AS_BL33
-#define PLAT_FIP_MAX_SIZE (0x8000000)
-#define PLAT_MMC_DATA_BASE (0x10000000)
-#define PLAT_MMC_DATA_SIZE (0x100000)
-# else
-#define PLAT_FIP_MAX_SIZE (0x1000000)
-#define PLAT_MMC_DATA_BASE (0xffe3c000)
-#define PLAT_MMC_DATA_SIZE (0x2000)
-# endif
-
static const io_dev_connector_t *fip_dev_con;
static const io_dev_connector_t *boot_dev_con;
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index c477787..1deed84 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -30,12 +30,14 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
+/* FIP Setting */
+#define PLAT_FIP_BASE (0)
+#define PLAT_FIP_MAX_SIZE (0x1000000)
+
/* SDMMC Setting */
-# if ARM_LINUX_KERNEL_AS_BL33
-#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
-# else
+#define PLAT_MMC_DATA_BASE (0xffe3c000)
+#define PLAT_MMC_DATA_SIZE (0x2000)
#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
-# endif
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE U(0xf7000000)
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index cd5b076..015ae12 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -29,12 +29,14 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
+/* FIP Setting */
+#define PLAT_FIP_BASE (0)
+#define PLAT_FIP_MAX_SIZE (0x1000000)
+
/* SDMMC Setting */
-# if ARM_LINUX_KERNEL_AS_BL33
-#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
-# else
+#define PLAT_MMC_DATA_BASE (0xffe3c000)
+#define PLAT_MMC_DATA_SIZE (0x2000)
#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
-# endif
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000