fix(altera): add in support for agilex5 b0 jtag id
Support Agilex5 B0 jtag id for fpga reconfig.
Change-Id: I4efb5a046a0f11009a1f08412ff0e48f376c94e1
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 71a626d..d64ead7 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -790,7 +790,7 @@
int intel_smmu_hps_remapper_config(uint32_t remapper_bypass)
{
/* Read out the JTAG-ID from boot scratch register */
- if (is_agilex5_A5F0() != 0) {
+ if (is_agilex5_A5F0() || is_agilex5_A5F4()) {
if (remapper_bypass == 0x01) {
g_remapper_bypass = remapper_bypass;
mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0);