fix(altera): add in support for agilex5 b0 jtag id
Support Agilex5 B0 jtag id for fpga reconfig.
Change-Id: I4efb5a046a0f11009a1f08412ff0e48f376c94e1
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index ac4bf12..8c86ab1 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -193,12 +193,12 @@
#define A5D0_JTAG_ID 0xD000
#define A5D4_JTAG_ID 0x4000D000
#define A5F0_JTAG_ID 0xC000
-#define A5F4_JTAG_ID 0x4000F000
+#define A5F4_JTAG_ID 0x4000C000
#define A510_JTAG_ID 0x1000
#define A514_JTAG_ID 0x40001000
#define A530_JTAG_ID 0x3000
#define A534_JTAG_ID 0x40003000
-#define JTAG_ID_MASK 0xC000F000
+#define JTAG_ID_MASK 0xF000F000
/* Field Masking */
#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h
index 346cfe1..14e3804 100644
--- a/plat/intel/soc/common/include/socfpga_system_manager.h
+++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,5 +36,6 @@
/* Function Prototype */
uint32_t intel_hps_get_jtag_id(void);
bool is_agilex5_A5F0(void);
+bool is_agilex5_A5F4(void);
#endif /* SOCFPGA_SYSTEMMANAGER_H */
diff --git a/plat/intel/soc/common/soc/socfpga_system_manager.c b/plat/intel/soc/common/soc/socfpga_system_manager.c
index 4223b2b..789c2b6 100644
--- a/plat/intel/soc/common/soc/socfpga_system_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_system_manager.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,7 +15,7 @@
uint32_t intel_hps_get_jtag_id(void)
{
- uint32_t jtag_id = 0x00;
+ uint32_t jtag_id;
jtag_id = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_4)));
@@ -29,3 +29,9 @@
{
return ((intel_hps_get_jtag_id() & JTAG_ID_MASK) == A5F0_JTAG_ID);
}
+
+/* Check for Agilex5 SM4 B0 */
+bool is_agilex5_A5F4(void)
+{
+ return ((intel_hps_get_jtag_id() & JTAG_ID_MASK) == A5F4_JTAG_ID);
+}
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 71a626d..d64ead7 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -790,7 +790,7 @@
int intel_smmu_hps_remapper_config(uint32_t remapper_bypass)
{
/* Read out the JTAG-ID from boot scratch register */
- if (is_agilex5_A5F0() != 0) {
+ if (is_agilex5_A5F0() || is_agilex5_A5F4()) {
if (remapper_bypass == 0x01) {
g_remapper_bypass = remapper_bypass;
mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0);