diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
index a9ab6e1..9a6b497 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
@@ -19,31 +19,6 @@
 #include "pm_common.h"
 #include "pm_ipi.h"
 
-#define PINCTRL_VOLTAGE_STATUS_MASK		U(0x01)
-#define PINCTRL_NUM_MIOS			U(78)
-#define MAX_PIN_PER_REG				U(26)
-#define PINCTRL_BANK_ADDR_STEP			U(28)
-
-#define PINCTRL_DRVSTRN0_REG_OFFSET		U(0)
-#define PINCTRL_DRVSTRN1_REG_OFFSET		U(4)
-#define PINCTRL_SCHCMOS_REG_OFFSET		U(8)
-#define PINCTRL_PULLCTRL_REG_OFFSET		U(12)
-#define PINCTRL_PULLSTAT_REG_OFFSET		U(16)
-#define PINCTRL_SLEWCTRL_REG_OFFSET		U(20)
-#define PINCTRL_VOLTAGE_STAT_REG_OFFSET		U(24)
-
-#define IOU_SLCR_BANK1_CTRL5			U(0XFF180164)
-
-#define PINCTRL_CFG_ADDR_OFFSET(addr, reg, miopin)			\
-	((addr) + 4 * PINCTRL_NUM_MIOS + PINCTRL_BANK_ADDR_STEP *	\
-	((miopin) / MAX_PIN_PER_REG) + (reg))
-
-#define PINCTRL_PIN_OFFSET(_miopin) \
-	((_miopin) - (MAX_PIN_PER_REG * ((_miopin) / MAX_PIN_PER_REG)))
-
-#define PINCTRL_REGVAL_TO_PIN_CONFIG(_pin, _val)			\
-	(((_val) >> PINCTRL_PIN_OFFSET(_pin)) & 0x1)
-
 struct pinctrl_function {
 	char name[FUNCTION_NAME_LEN];
 	uint16_t (*groups)[];
@@ -2700,232 +2675,3 @@
 
 	return PM_RET_SUCCESS;
 }
-
-/**
- * pm_api_pinctrl_set_config() - Set configuration parameter for given pin
- * @pin: Pin for which configuration is to be set
- * @param: Configuration parameter to be set
- * @value: Value to be set for configuration parameter
- *
- * This function sets value of requested configuration parameter for given pin.
- *
- * @return	Returns status, either success or error+reason
- */
-enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin,
-					     unsigned int param,
-					     unsigned int value)
-{
-	enum pm_ret_status ret;
-	unsigned int ctrlreg, mask, val, offset;
-
-	if (param >= PINCTRL_CONFIG_MAX)
-		return PM_RET_ERROR_NOTSUPPORTED;
-
-	if (pin >=  PINCTRL_NUM_MIOS)
-		return PM_RET_ERROR_ARGS;
-
-	mask = 1 << PINCTRL_PIN_OFFSET(pin);
-
-	switch (param) {
-	case PINCTRL_CONFIG_SLEW_RATE:
-		if (value != PINCTRL_SLEW_RATE_FAST &&
-		    value != PINCTRL_SLEW_RATE_SLOW)
-			return PM_RET_ERROR_ARGS;
-
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_SLEWCTRL_REG_OFFSET,
-					      pin);
-		val = value << PINCTRL_PIN_OFFSET(pin);
-		ret = pm_mmio_write(ctrlreg, mask, val);
-		break;
-	case PINCTRL_CONFIG_BIAS_STATUS:
-		if (value != PINCTRL_BIAS_ENABLE &&
-		    value != PINCTRL_BIAS_DISABLE)
-			return PM_RET_ERROR_ARGS;
-
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_PULLSTAT_REG_OFFSET,
-					      pin);
-
-		offset = PINCTRL_PIN_OFFSET(pin);
-		if (ctrlreg == IOU_SLCR_BANK1_CTRL5)
-			offset = (offset < 12U) ?
-					(offset + 14U) : (offset - 12U);
-
-		val = value << offset;
-		mask = 1 << offset;
-		ret = pm_mmio_write(ctrlreg, mask, val);
-		break;
-	case PINCTRL_CONFIG_PULL_CTRL:
-
-		if (value != PINCTRL_BIAS_PULL_DOWN &&
-		    value != PINCTRL_BIAS_PULL_UP)
-			return PM_RET_ERROR_ARGS;
-
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_PULLSTAT_REG_OFFSET,
-					      pin);
-
-		offset = PINCTRL_PIN_OFFSET(pin);
-		if (ctrlreg == IOU_SLCR_BANK1_CTRL5)
-			offset = (offset < 12U) ?
-					(offset + 14U) : (offset - 12U);
-
-		val = PINCTRL_BIAS_ENABLE << offset;
-		ret = pm_mmio_write(ctrlreg, 1 << offset, val);
-		if (ret != PM_RET_SUCCESS)
-			return ret;
-
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_PULLCTRL_REG_OFFSET,
-					      pin);
-		val = value << PINCTRL_PIN_OFFSET(pin);
-		ret = pm_mmio_write(ctrlreg, mask, val);
-		break;
-	case PINCTRL_CONFIG_SCHMITT_CMOS:
-		if (value != PINCTRL_INPUT_TYPE_CMOS &&
-		    value != PINCTRL_INPUT_TYPE_SCHMITT)
-			return PM_RET_ERROR_ARGS;
-
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_SCHCMOS_REG_OFFSET,
-					      pin);
-
-		val = value << PINCTRL_PIN_OFFSET(pin);
-		ret = pm_mmio_write(ctrlreg, mask, val);
-		break;
-	case PINCTRL_CONFIG_DRIVE_STRENGTH:
-		if (value > PINCTRL_DRIVE_STRENGTH_12MA)
-			return PM_RET_ERROR_ARGS;
-
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_DRVSTRN0_REG_OFFSET,
-					      pin);
-		val = (value >> 1) << PINCTRL_PIN_OFFSET(pin);
-		ret = pm_mmio_write(ctrlreg, mask, val);
-		if (ret)
-			return ret;
-
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_DRVSTRN1_REG_OFFSET,
-					      pin);
-		val = (value & 0x01U) << PINCTRL_PIN_OFFSET(pin);
-		ret = pm_mmio_write(ctrlreg, mask, val);
-		break;
-	default:
-		ERROR("Invalid parameter %u\n", param);
-		ret = PM_RET_ERROR_NOTSUPPORTED;
-		break;
-	}
-
-	return ret;
-}
-
-/**
- * pm_api_pinctrl_get_config() - Get configuration parameter value for given pin
- * @pin: Pin for which configuration is to be read
- * @param: Configuration parameter to be read
- * @value: buffer to store value of configuration parameter
- *
- * This function reads value of requested configuration parameter for given pin.
- *
- * @return	Returns status, either success or error+reason
- */
-enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin,
-					     unsigned int param,
-					     unsigned int *value)
-{
-	enum pm_ret_status ret;
-	unsigned int ctrlreg, val;
-
-	if (param >= PINCTRL_CONFIG_MAX)
-		return PM_RET_ERROR_NOTSUPPORTED;
-
-	if (pin >=  PINCTRL_NUM_MIOS)
-		return PM_RET_ERROR_ARGS;
-
-	switch (param) {
-	case PINCTRL_CONFIG_SLEW_RATE:
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_SLEWCTRL_REG_OFFSET,
-					      pin);
-
-		ret = pm_mmio_read(ctrlreg, &val);
-		if (ret != PM_RET_SUCCESS)
-			return ret;
-
-		*value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
-		break;
-	case PINCTRL_CONFIG_BIAS_STATUS:
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_PULLSTAT_REG_OFFSET,
-					      pin);
-
-		ret = pm_mmio_read(ctrlreg, &val);
-		if (ret)
-			return ret;
-
-		if (ctrlreg == IOU_SLCR_BANK1_CTRL5)
-			val = ((val & 0x3FFF) << 12) | ((val >> 14) & 0xFFF);
-
-		*value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
-		break;
-	case PINCTRL_CONFIG_PULL_CTRL:
-
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_PULLCTRL_REG_OFFSET,
-					      pin);
-
-		ret = pm_mmio_read(ctrlreg, &val);
-		if (ret)
-			return ret;
-
-		*value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
-		break;
-	case PINCTRL_CONFIG_SCHMITT_CMOS:
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_SCHCMOS_REG_OFFSET,
-					      pin);
-
-		ret = pm_mmio_read(ctrlreg, &val);
-		if (ret)
-			return ret;
-
-		*value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
-		break;
-	case PINCTRL_CONFIG_DRIVE_STRENGTH:
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_DRVSTRN0_REG_OFFSET,
-					      pin);
-		ret = pm_mmio_read(ctrlreg, &val);
-		if (ret)
-			return ret;
-
-		*value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val) << 1;
-
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_DRVSTRN1_REG_OFFSET,
-					      pin);
-		ret = pm_mmio_read(ctrlreg, &val);
-		if (ret)
-			return ret;
-
-		*value |= PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
-		break;
-	case PINCTRL_CONFIG_VOLTAGE_STATUS:
-		ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
-					      PINCTRL_VOLTAGE_STAT_REG_OFFSET,
-					      pin);
-
-		ret = pm_mmio_read(ctrlreg, &val);
-		if (ret)
-			return ret;
-
-		*value = val & PINCTRL_VOLTAGE_STATUS_MASK;
-		break;
-	default:
-		return PM_RET_ERROR_NOTSUPPORTED;
-	}
-
-	return PM_RET_SUCCESS;
-}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
index 7ce61b0..2b8fca3 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
@@ -709,12 +709,6 @@
 #define	PINCTRL_DRIVE_STRENGTH_8MA 2U
 #define	PINCTRL_DRIVE_STRENGTH_12MA 3U
 
-enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin,
-					     unsigned int param,
-					     unsigned int value);
-enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin,
-					     unsigned int param,
-					     unsigned int *value);
 void pm_api_pinctrl_get_function_name(unsigned int fid, char *name);
 enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid,
 						      unsigned int index,
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
index 1c5d1ac..1ec06f9 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
@@ -726,24 +726,30 @@
 					 unsigned int param,
 					 unsigned int *value)
 {
-	return pm_api_pinctrl_get_config(pin, param, value);
+	uint32_t payload[PAYLOAD_ARG_CNT];
+
+	PM_PACK_PAYLOAD3(payload, PM_PINCTRL_CONFIG_PARAM_GET, pin, param);
+	return pm_ipi_send_sync(primary_proc, payload, value, 1);
 }
 
 /**
- * pm_pinctrl_set_config() - Read value of requested config param for given pin
+ * pm_pinctrl_set_config() - Set value of requested config param for given pin
  * @pin		Pin number
  * @param	Parameter to set
  * @value	Parameter value to set
  *
- * This function provides the configuration parameter value for the given pin.
- *
  * @return	Returns status, either success or error+reason
  */
 enum pm_ret_status pm_pinctrl_set_config(unsigned int pin,
 					 unsigned int param,
 					 unsigned int value)
 {
-	return pm_api_pinctrl_set_config(pin, param, value);
+	uint32_t payload[PAYLOAD_ARG_CNT];
+
+	/* Send request to the PMU */
+	PM_PACK_PAYLOAD4(payload, PM_PINCTRL_CONFIG_PARAM_SET, pin, param,
+			 value);
+	return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
 }
 
 /**