intel: Refactor common platform code [4/5]
Pull out SiP & PSCI service driver into socfpga common directory.
Remove deassert_peripheral_reset from cold reset procedure as it is not
needed.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1a0390fca6db4c89919a2a038de2a9d96c3ae4fd
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index bf8fc36..dc56ac8 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -57,9 +57,9 @@
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/aem_generic.S \
plat/common/plat_psci_common.c \
- plat/intel/soc/agilex/socfpga_sip_svc.c \
+ plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/agilex/bl31_plat_setup.c \
- plat/intel/soc/agilex/socfpga_psci.c \
+ plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/agilex/soc/agilex_reset_manager.c \
diff --git a/plat/intel/soc/agilex/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
similarity index 92%
rename from plat/intel/soc/agilex/socfpga_psci.c
rename to plat/intel/soc/common/socfpga_psci.c
index 4b29159..e298361 100644
--- a/plat/intel/soc/agilex/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -11,13 +11,11 @@
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
-#include "agilex_reset_manager.h"
#include "socfpga_mailbox.h"
+#include "socfpga_plat_def.h"
-#define AGX_RSTMGR_OFST 0xffd11000
-#define AGX_RSTMGR_MPUMODRST_OFST 0x20
-uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
+uintptr_t *socfpga_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
/*******************************************************************************
@@ -50,8 +48,7 @@
*cpuid_release = cpu_id;
/* release core reset */
- mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
+ mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
return PSCI_E_SUCCESS;
}
@@ -81,8 +78,7 @@
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
/* assert core reset */
- mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
+ mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
}
@@ -121,8 +117,7 @@
__func__, i, target_state->pwr_domain_state[i]);
/* release core reset */
- mmio_clrbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
+ mmio_clrbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
}
/*******************************************************************************
@@ -137,9 +132,6 @@
static void __dead2 socfpga_system_reset(void)
{
- INFO("assert Peripheral from Reset\r\n");
-
- deassert_peripheral_reset();
mailbox_reset_cold();
while (1)
@@ -191,7 +183,7 @@
const struct plat_psci_ops **psci_ops)
{
/* Save warm boot entrypoint.*/
- *agilex_sec_entry = sec_entrypoint;
+ *socfpga_sec_entry = sec_entrypoint;
*psci_ops = &socfpga_psci_pm_ops;
return 0;
diff --git a/plat/intel/soc/agilex/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
similarity index 99%
rename from plat/intel/soc/agilex/socfpga_sip_svc.c
rename to plat/intel/soc/common/socfpga_sip_svc.c
index 16e3c03..88750d7 100644
--- a/plat/intel/soc/agilex/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -360,7 +360,7 @@
}
DECLARE_RT_SVC(
- agilex_sip_svc,
+ socfpga_sip_svc,
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_FAST,
@@ -369,7 +369,7 @@
);
DECLARE_RT_SVC(
- agilex_sip_svc_std,
+ socfpga_sip_svc_std,
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_YIELD,
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index 2ed1cb4..5bf8f65 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -55,9 +55,9 @@
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_psci_common.c \
- plat/intel/soc/stratix10/plat_sip_svc.c \
+ plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/stratix10/bl31_plat_setup.c \
- plat/intel/soc/stratix10/plat_psci.c \
+ plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/stratix10/soc/s10_reset_manager.c\