fix(stm32mp1_clk): fix MPU clock rate
MPUDIV dividers are stored in a constant array, under bit shifts form.
They must be used in this way by the clock driver.
Change-Id: If758f7a4048eff956067a10a42ab0983a20a000d
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index d1fc578..9764a9f 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -850,9 +850,7 @@
reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);
clkdiv = reg & RCC_MPUDIV_MASK;
- if (clkdiv != 0U) {
- clock /= stm32mp1_mpu_div[clkdiv];
- }
+ clock >>= stm32mp1_mpu_div[clkdiv];
break;
default:
break;