| commit | 4c7f4da329a7ae8805170109f85f2bb2ab1c4067 | [log] [tgz] |
|---|---|---|
| author | Jit Loon Lim <jit.loon.lim@altera.com> | Fri Mar 07 17:21:23 2025 +0800 |
| committer | Jit Loon Lim <jit.loon.lim@altera.com> | Sat May 17 22:47:58 2025 +0800 |
| tree | 70d0a265790128e4e6ce994ce264495cd73935f8 | |
| parent | 201837641db8de29eb2811e8bd427eaf15a8afbf [diff] [blame] |
feat(intel): update CPUECTLR_EL1 to boost ethernet performance This patch is the workaround for Agilex5 Ethernet for performance boost. Change-Id: I702f0cb0beff8b3ea119205ec41dd4e825e9126b Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h index fbe18c3..782b2b5 100644 --- a/plat/intel/soc/common/include/socfpga_private.h +++ b/plat/intel/soc/common/include/socfpga_private.h
@@ -65,4 +65,6 @@ void plat_secondary_cpus_bl31_entry(void); +void setup_clusterectlr_el1(void); + #endif /* SOCFPGA_PRIVATE_H */