feat(intel): update CPUECTLR_EL1 to boost ethernet performance
This patch is the workaround for Agilex5 Ethernet for performance
boost.
Change-Id: I702f0cb0beff8b3ea119205ec41dd4e825e9126b
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c
index 9cf1e11..66e0ea5 100644
--- a/plat/intel/soc/agilex5/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl31_plat_setup.c
@@ -217,9 +217,11 @@
NOTICE("SOCFPGA: CPU ID = %x\n", cpuid);
INFO("SOCFPGA: Invalidate Data cache\n");
invalidate_dcache_all();
-
/* Invalidate for NS EL2 and EL1 */
invalidate_cache_low_el();
+
+ NOTICE("SOCFPGA: Setting CLUSTERECTRL_EL1\n");
+ setup_clusterectlr_el1();
}
/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
@@ -303,6 +305,22 @@
mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pch_cpu);
}
+void setup_clusterectlr_el1(void)
+{
+ uint64_t value = 0;
+
+ /* Read CLUSTERECTLR_EL1 */
+ asm volatile("mrs %0, S3_0_C15_C3_4" : "=r"(value));
+
+ /* Disable broadcasting atomics */
+ value |= 0x80; /* set bit 7 */
+ /* Disable sending data with clean evicts */
+ value &= 0xFFFFBFFF; /* Mask out bit 14 */
+
+ /* Write CLUSTERECTLR_EL1 */
+ asm volatile("msr S3_0_C15_C3_4, %0" :: "r"(value));
+}
+
void bl31_plat_runtime_setup(void)
{
/* Dummy override function. */