feat(stm32mp1): configure the serial boot load address
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it overlap the OP-TEE final location. So the default value
for DWL_BUFFER_BASE is invalid.
To avoid this conflict the serial boot load address = DWL_BUFFER_BASE
can be modified with a configuration flags.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie27b87c10c57fea5d4c6200ce4f624e775b9a080
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 7203de8..be07a4b 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -121,6 +121,9 @@
STM32MP_USB_PROGRAMMER ?= 0
STM32MP_UART_PROGRAMMER ?= 0
+# Download load address for serial boot devices
+DWL_BUFFER_BASE ?= 0xC7000000
+
# Device tree
ifeq ($(STM32MP13),1)
BL2_DTSI := stm32mp13-bl2.dtsi
@@ -225,6 +228,7 @@
$(eval $(call add_defines,\
$(sort \
+ DWL_BUFFER_BASE \
PLAT_PARTITION_MAX_ENTRIES \
PLAT_XLAT_TABLES_DYNAMIC \
STM32_TF_A_COPIES \