tree f0881455450d68e705244408e423ee886699724c
parent 82a6084860bf5e48b3f77532e135771edffaa4ae
author Sandeep Tripathy <sandeep.tripathy@broadcom.com> 1591374861 +0530
committer Sandeep Tripathy <sandeep.tripathy@broadcom.com> 1592822315 +0530

TF-A GIC driver: Add barrier before eoi

It is desired to have the peripheral writes completed to clear the
interrupt condition and de-assert the interrupt request to GIC before
EOI write. Failing which spurious interrupt will occurred.

A barrier is needed to ensure peripheral register write transfers are
complete before EOI is done.

GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point
of view. However these writes may pass over different interconnects,
bridges, buffers leaving some rare chances for the actual write to
complete out of order.

GICv3 ICC EOI system register writes have no ordering against nGnR(n)E
memory writes as they are over different interfaces.

Hence a dsb can ensure from core no writes are issued before the previous
writes are *complete*.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Change-Id: Ie6362009e2f91955be99dca8ece14ade7b4811d6