tree 5108253f7825bd9135df859d2908c1e38e9018c9
parent 17d07627015c6977139eb2d225f8d22d15a101d1
author Jit Loon Lim <jit.loon.lim@intel.com> 1684297571 +0800
committer Jit Loon Lim <jit.loon.lim@intel.com> 1688523082 +0800

feat(intel): platform enablement for Agilex5 SoC FPGA

This patch is used to enable platform enablement for
Agilex5 SoC FPGA.

New feature:
	1. Added ATF->Zephyr boot option
	2. Added xlat_v2 for MMU
	3. Added ATF->Linux boot option
	4. Added SMP support
	5. Added HPS bridges support
	6. Added EMULATOR support
	7. Added DDR support
	8. Added GICv3 Redistirbution init
	9. Added SDMMC/NAND/Combo Phy support
	10. Updated GIC as secure access
	11. Added CCU driver support
	12. Updated product name -> Agilex5
	13. Updated register address based on y22ww52.2 RTL
	14. Updated system counter freq to 400MHz

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009