commit 4c249f1515c54aae83e35575477e11109f0994e2
author Jit Loon Lim <jit.loon.lim@intel.com> Wed May 17 12:26:11 2023 +0800
committer Jit Loon Lim <jit.loon.lim@intel.com> Wed Jul 05 10:11:22 2023 +0800
tree 5108253f7825bd9135df859d2908c1e38e9018c9
parent 17d07627015c6977139eb2d225f8d22d15a101d1

feat(intel): platform enablement for Agilex5 SoC FPGA

This patch is used to enable platform enablement for
Agilex5 SoC FPGA.

New feature:
	1. Added ATF->Zephyr boot option
	2. Added xlat_v2 for MMU
	3. Added ATF->Linux boot option
	4. Added SMP support
	5. Added HPS bridges support
	6. Added EMULATOR support
	7. Added DDR support
	8. Added GICv3 Redistirbution init
	9. Added SDMMC/NAND/Combo Phy support
	10. Updated GIC as secure access
	11. Added CCU driver support
	12. Updated product name -> Agilex5
	13. Updated register address based on y22ww52.2 RTL
	14. Updated system counter freq to 400MHz

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009

plat/intel/soc/common/include/socfpga_noc.h

diff --git a/plat/intel/soc/common/include/socfpga_noc.h b/plat/intel/soc/common/include/socfpga_noc.h
index e3c0f73..3fc3f81 100644
--- a/plat/intel/soc/common/include/socfpga_noc.h
+++ b/plat/intel/soc/common/include/socfpga_noc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -74,6 +74,10 @@
 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2			0x0070
 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3			0x0074
 #define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP				0x0078
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG4			0x007c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_PWRMGR			0x0080
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_RXECC			0x0084
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_TXECC			0x0088
 #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES			0x0090
 #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS			0x0094