Merge pull request #1748 from antonio-nino-diaz-arm/an/build-flags
build: Support BL-specific build flags
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index cbe272c..4af3e90 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -94,12 +94,16 @@
/* CSSELR definitions */
#define LEVEL_SHIFT U(1)
-/* ID_PFR0 AMU definitions */
+/* ID_MMFR4 definitions */
+#define ID_MMFR4_CNP_SHIFT U(12)
+#define ID_MMFR4_CNP_LENGTH U(4)
+#define ID_MMFR4_CNP_MASK U(0xf)
+
+/* ID_PFR0 definitions */
#define ID_PFR0_AMU_SHIFT U(20)
#define ID_PFR0_AMU_LENGTH U(4)
#define ID_PFR0_AMU_MASK U(0xf)
-/* ID_PFR0 DIT definitions */
#define ID_PFR0_DIT_SHIFT U(24)
#define ID_PFR0_DIT_LENGTH U(4)
#define ID_PFR0_DIT_MASK U(0xf)
@@ -475,6 +479,7 @@
#define DCISW p15, 0, c7, c6, 2
#define CTR p15, 0, c0, c0, 1
#define CNTFRQ p15, 0, c14, c0, 0
+#define ID_MMFR4 p15, 0, c0, c2, 6
#define ID_PFR0 p15, 0, c0, c1, 0
#define ID_PFR1 p15, 0, c0, c1, 1
#define MAIR0 p15, 0, c10, c2, 0
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
new file mode 100644
index 0000000..d934102
--- /dev/null
+++ b/include/arch/aarch32/arch_features.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARCH_FEATURES_H
+#define ARCH_FEATURES_H
+
+#include <stdbool.h>
+
+#include <arch_helpers.h>
+
+static inline bool is_armv8_2_ttcnp_present(void)
+{
+ return ((read_id_mmfr4() >> ID_MMFR4_CNP_SHIFT) &
+ ID_MMFR4_CNP_MASK) != 0U;
+}
+
+#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h
index c2773c1..64ddc86 100644
--- a/include/arch/aarch32/arch_helpers.h
+++ b/include/arch/aarch32/arch_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -214,6 +214,7 @@
******************************************************************************/
DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR)
DEFINE_COPROCR_READ_FUNC(midr, MIDR)
+DEFINE_COPROCR_READ_FUNC(id_mmfr4, ID_MMFR4)
DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0)
DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1)
DEFINE_COPROCR_READ_FUNC(isr, ISR)
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 8a44d83..9e2bffa 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -156,10 +156,6 @@
#define ID_AA64PFR0_GIC_WIDTH U(4)
#define ID_AA64PFR0_GIC_MASK ((ULL(1) << ID_AA64PFR0_GIC_WIDTH) - ULL(1))
-/* ID_AA64MMFR0_EL1 definitions */
-#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
-#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
-
/* ID_AA64ISAR1_EL1 definitions */
#define ID_AA64ISAR1_GPI_SHIFT U(28)
#define ID_AA64ISAR1_GPI_WIDTH U(4)
@@ -179,6 +175,10 @@
#define ID_AA64ISAR1_APA_MASK \
(((ULL(1) << ID_AA64ISAR1_APA_WIDTH) - ULL(1)) << ID_AA64ISAR1_APA_SHIFT)
+/* ID_AA64MMFR0_EL1 definitions */
+#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
+#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
+
#define PARANGE_0000 U(32)
#define PARANGE_0001 U(36)
#define PARANGE_0010 U(40)
@@ -202,6 +202,11 @@
#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
+/* ID_AA64MMFR2_EL1 definitions */
+#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
+#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
+#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
+
/* ID_AA64PFR1_EL1 definitions */
#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
new file mode 100644
index 0000000..2b09ba0
--- /dev/null
+++ b/include/arch/aarch64/arch_features.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARCH_FEATURES_H
+#define ARCH_FEATURES_H
+
+#include <stdbool.h>
+
+#include <arch_helpers.h>
+
+static inline bool is_armv8_2_ttcnp_present(void)
+{
+ return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
+ ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
+}
+
+#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index b912b42..d3f0df7 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -449,6 +449,9 @@
DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
+/* Armv8.2 Registers */
+DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
+
/* Armv8.3 Pointer Authentication Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(apgakeylo_el1, APGAKeyLo_EL1)
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
index 349b6c4..913c86d 100644
--- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
#include <platform_def.h>
#include <arch.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <lib/cassert.h>
#include <lib/utils_def.h>
@@ -219,13 +220,10 @@
/* Set TTBR0 bits as well */
ttbr0 = (uint64_t)(uintptr_t) base_table;
-#if ARM_ARCH_AT_LEAST(8, 2)
- /*
- * Enable CnP bit so as to share page tables with all PEs. This
- * is mandatory for ARMv8.2 implementations.
- */
- ttbr0 |= TTBR_CNP_BIT;
-#endif
+ if (is_armv8_2_ttcnp_present()) {
+ /* Enable CnP bit so as to share page tables with all PEs. */
+ ttbr0 |= TTBR_CNP_BIT;
+ }
/* Now populate MMU configuration */
params[MMU_CFG_MAIR] = mair;
diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
index a803d83..228f751 100644
--- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#include <stdint.h>
#include <arch.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <lib/cassert.h>
#include <lib/utils_def.h>
@@ -266,13 +267,10 @@
/* Set TTBR bits as well */
ttbr0 = (uint64_t) base_table;
-#if ARM_ARCH_AT_LEAST(8, 2)
- /*
- * Enable CnP bit so as to share page tables with all PEs. This
- * is mandatory for ARMv8.2 implementations.
- */
- ttbr0 |= TTBR_CNP_BIT;
-#endif
+ if (is_armv8_2_ttcnp_present()) {
+ /* Enable CnP bit so as to share page tables with all PEs. */
+ ttbr0 |= TTBR_CNP_BIT;
+ }
params[MMU_CFG_MAIR] = mair;
params[MMU_CFG_TCR] = tcr;
diff --git a/maintainers.rst b/maintainers.rst
index 37766ed..f53dda5 100644
--- a/maintainers.rst
+++ b/maintainers.rst
@@ -144,6 +144,13 @@
:F: docs/plat/imx8.rst
:F: plat/imx/
+NXP i.MX8M platform port
+------------------------
+:M: Jacky Bai <ping.bai@nxp.com>
+:G: `JackyBai`_
+:F: doc/plat/imx8m.rst
+:F: plat/imx/imx8m/
+
OP-TEE dispatcher
-----------------
:M: Jens Wiklander <jens.wiklander@linaro.org>
@@ -241,6 +248,7 @@
.. _etienne-lms: https://github.com/etienne-lms
.. _glneo: https://github.com/glneo
.. _hzhuang1: https://github.com/hzhuang1
+.. _JackyBai: https://github.com/JackyBai
.. _jenswi-linaro: https://github.com/jenswi-linaro
.. _ldts: https://github.com/ldts
.. _niej: https://github.com/niej
diff --git a/plat/hisilicon/hikey960/hikey960_def.h b/plat/hisilicon/hikey960/hikey960_def.h
index d977c79..4ea3acd 100644
--- a/plat/hisilicon/hikey960/hikey960_def.h
+++ b/plat/hisilicon/hikey960/hikey960_def.h
@@ -11,7 +11,7 @@
#include <plat/common/common_def.h>
#define DDR_BASE 0x0
-#define DDR_SIZE 0xC0000000
+#define DDR_SIZE 0xE0000000
#define DEVICE_BASE 0xE0000000
#define DEVICE_SIZE 0x20000000
diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h
index 3e2d79d..7c3c102 100644
--- a/plat/hisilicon/hikey960/include/platform_def.h
+++ b/plat/hisilicon/hikey960/include/platform_def.h
@@ -122,11 +122,7 @@
#endif
#ifdef IMAGE_BL2
-#ifdef SPD_opteed
#define MAX_XLAT_TABLES 4
-#else
-#define MAX_XLAT_TABLES 3
-#endif
#endif
#define MAX_MMAP_REGIONS 16
diff --git a/readme.rst b/readme.rst
index e7fbfb4..1f02bf1 100644
--- a/readme.rst
+++ b/readme.rst
@@ -9,7 +9,7 @@
- The `Power State Coordination Interface (PSCI)`_
- Trusted Board Boot Requirements (TBBR, Arm DEN0006C-1)
- `SMC Calling Convention`_
-- `System Control and Management Interface`_
+- `System Control and Management Interface (SCMI)`_
- `Software Delegated Exception Interface (SDEI)`_
Where possible, the code is designed for reuse or porting to other Armv7-A and
@@ -58,7 +58,7 @@
This release provides a suitable starting point for productization of secure
world boot and runtime firmware, in either the AArch32 or AArch64 execution
-state.
+states.
Users are encouraged to do their own security validation, including penetration
testing, on any secure world code derived from TF-A.
@@ -95,13 +95,13 @@
- Secure Monitor library code such as world switching, EL1 context management
and interrupt routing.
When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
- AArch64 EL3 Runtime Software must be integrated with a dispatcher component
- (SPD) to customize the interaction with the SP.
+ AArch64 EL3 Runtime Software must be integrated with a Secure Payload
+ Dispatcher (SPD) component to customize the interaction with the SP.
-- A Test SP/SPD to demonstrate AArch64 Secure Monitor functionality and SP
+- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
interaction with PSCI.
-- SPDs for the `OP-TEE Secure OS`_, `NVidia Trusted Little Kernel`_
+- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_
and `Trusty Secure OS`_.
- A Trusted Board Boot implementation, conforming to all mandatory TBBR
@@ -136,8 +136,8 @@
- Support for the GCC, LLVM and Arm Compiler 6 toolchains.
-- Support combining several libraries into a self-called "romlib" image, that
- may be shared across images to reduce memory footprint. The romlib image
+- Support for combining several libraries into a self-called "romlib" image
+ that may be shared across images to reduce memory footprint. The romlib image
is stored in ROM but is accessed through a jump-table that may be stored
in read-write memory, allowing for the library code to be patched.
@@ -148,8 +148,8 @@
Platforms
~~~~~~~~~
-Various AArch32 and AArch64 builds of this release has been tested on variants
-r0, r1 and r2 of the `Juno Arm Development Platform`_.
+Various AArch32 and AArch64 builds of this release have been tested on r0, r1
+and r2 variants of the `Juno Arm Development Platform`_.
Various AArch64 builds of this release have been tested on the following Arm
Fixed Virtual Platforms (`FVP`_) without shifted affinities that do not
@@ -229,10 +229,10 @@
Get the TF-A source code from `GitHub`_.
-See the `User Guide`_ for instructions on how to install, build and use
-the TF-A with the Arm `FVP`_\ s.
+See the `User Guide`_ for instructions on how to install, build and use TF-A
+with the Arm `FVP`_\ s.
-See the `Firmware Design`_ for information on how the TF-A works.
+See the `Firmware Design`_ for information on how TF-A works.
See the `Porting Guide`_ as well for information about how to use this
software on another Armv7-A or Armv8-A platform.
@@ -267,7 +267,7 @@
.. _Power State Coordination Interface (PSCI): PSCI_
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
-.. _System Control and Management Interface: SCMI_
+.. _System Control and Management Interface (SCMI): SCMI_
.. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
.. _Software Delegated Exception Interface (SDEI): SDEI_
.. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
@@ -276,7 +276,7 @@
.. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms
.. _Linaro Release 18.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease18.04
.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
-.. _NVidia Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
+.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
.. _Trusty Secure OS: https://source.android.com/security/trusty
.. _GitHub: https://www.github.com/ARM-software/arm-trusted-firmware
.. _GitHub issue tracker: https://github.com/ARM-software/tf-issues/issues