Merge "feat(sve): enable SVE for the secure world" into integration
diff --git a/Makefile b/Makefile
index fbc1cc7..c013e35 100644
--- a/Makefile
+++ b/Makefile
@@ -334,7 +334,7 @@
# General warnings
WARNINGS := -Wall -Wmissing-include-dirs -Wunused \
- -Wdisabled-optimization -Wvla -Wshadow \
+ -Wdisabled-optimization -Wvla -Wshadow \
-Wno-unused-parameter -Wredundant-decls
# Additional warnings
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index fc853f3..ab638fb 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -263,6 +263,9 @@
- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77
+ CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
+
For Cortex-A78, the following errata build flags are defined :
- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
diff --git a/drivers/arm/css/scmi/scmi_common.c b/drivers/arm/css/scmi/scmi_common.c
index 5b3724a..ec749fb 100644
--- a/drivers/arm/css/scmi/scmi_common.c
+++ b/drivers/arm/css/scmi/scmi_common.c
@@ -173,12 +173,12 @@
ret = scmi_proto_version(ch, SCMI_PWR_DMN_PROTO_ID, &version);
if (ret != SCMI_E_SUCCESS) {
- WARN("SCMI power domain protocol version message failed");
+ WARN("SCMI power domain protocol version message failed\n");
goto error;
}
if (!is_scmi_version_compatible(SCMI_PWR_DMN_PROTO_VER, version)) {
- WARN("SCMI power domain protocol version 0x%x incompatible with driver version 0x%x",
+ WARN("SCMI power domain protocol version 0x%x incompatible with driver version 0x%x\n",
version, SCMI_PWR_DMN_PROTO_VER);
goto error;
}
@@ -187,12 +187,12 @@
ret = scmi_proto_version(ch, SCMI_SYS_PWR_PROTO_ID, &version);
if ((ret != SCMI_E_SUCCESS)) {
- WARN("SCMI system power protocol version message failed");
+ WARN("SCMI system power protocol version message failed\n");
goto error;
}
if (!is_scmi_version_compatible(SCMI_SYS_PWR_PROTO_VER, version)) {
- WARN("SCMI system power management protocol version 0x%x incompatible with driver version 0x%x",
+ WARN("SCMI system power management protocol version 0x%x incompatible with driver version 0x%x\n",
version, SCMI_SYS_PWR_PROTO_VER);
goto error;
}
diff --git a/drivers/mtd/nor/spi_nor.c b/drivers/mtd/nor/spi_nor.c
index 108f893..8111efd 100644
--- a/drivers/mtd/nor/spi_nor.c
+++ b/drivers/mtd/nor/spi_nor.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -103,7 +103,7 @@
0 : 1;
}
- return (((sr & SR_WIP) != 0U) ? 1 : 0);
+ return (((sr & SR_WIP) == 0U) ? 0 : 1);
}
static int spi_nor_wait_ready(void)
@@ -141,7 +141,7 @@
}
sr |= SR_QUAD_EN_MX;
- ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1, SPI_MEM_DATA_OUT);
+ ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1U, SPI_MEM_DATA_OUT);
if (ret != 0) {
return ret;
}
@@ -168,7 +168,7 @@
return ret;
}
- ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2, SPI_MEM_DATA_OUT);
+ ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2U, SPI_MEM_DATA_OUT);
if (ret != 0) {
return -EINVAL;
}
@@ -230,7 +230,7 @@
}
return spi_nor_reg(nor_dev.bank_write_cmd, &nor_dev.selected_bank,
- 1, SPI_MEM_DATA_OUT);
+ 1U, SPI_MEM_DATA_OUT);
}
static int spi_nor_write_bar(uint32_t offset)
@@ -248,7 +248,7 @@
}
ret = spi_nor_reg(nor_dev.bank_write_cmd, &selected_bank,
- 1, SPI_MEM_DATA_OUT);
+ 1U, SPI_MEM_DATA_OUT);
if (ret != 0) {
return ret;
}
@@ -260,11 +260,11 @@
static int spi_nor_read_bar(void)
{
- uint8_t selected_bank = 0;
+ uint8_t selected_bank = 0U;
int ret;
ret = spi_nor_reg(nor_dev.bank_read_cmd, &selected_bank,
- 1, SPI_MEM_DATA_IN);
+ 1U, SPI_MEM_DATA_IN);
if (ret != 0) {
return ret;
}
@@ -280,7 +280,7 @@
size_t remain_len;
int ret;
- *length_read = 0;
+ *length_read = 0U;
nor_dev.read_op.addr.val = offset;
nor_dev.read_op.data.buf = (void *)buffer;
@@ -324,7 +324,7 @@
int spi_nor_init(unsigned long long *size, unsigned int *erase_size)
{
- int ret = 0;
+ int ret;
uint8_t id;
/* Default read command used */
@@ -339,7 +339,7 @@
return -EINVAL;
}
- assert(nor_dev.size != 0);
+ assert(nor_dev.size != 0U);
if (nor_dev.size > BANK_SIZE) {
nor_dev.flags |= SPI_NOR_USE_BANK;
diff --git a/fdts/tc0.dts b/fdts/tc0.dts
index a4f7a4d..24e2496 100644
--- a/fdts/tc0.dts
+++ b/fdts/tc0.dts
@@ -17,6 +17,7 @@
};
chosen {
+ bootargs = "console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute androidboot.boot_devices=1c050000.mmci ip=dhcp androidboot.selinux=permissive allow_mismatched_32bit_el0";
stdout-path = "serial0:115200n8";
};
@@ -85,6 +86,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <406>;
};
CPU1:cpu@100 {
@@ -94,6 +96,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <406>;
};
CPU2:cpu@200 {
@@ -103,6 +106,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <406>;
};
CPU3:cpu@300 {
@@ -112,6 +116,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <406>;
};
CPU4:cpu@400 {
@@ -121,6 +126,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <912>;
};
CPU5:cpu@500 {
@@ -130,6 +136,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <912>;
};
CPU6:cpu@600 {
@@ -139,6 +146,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <912>;
};
CPU7:cpu@700 {
@@ -148,6 +156,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
};
};
@@ -169,7 +178,7 @@
};
psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
@@ -188,31 +197,32 @@
};
mbox_db_rx: mhu@45010000 {
- compatible = "arm,mhuv2","arm,primecell";
+ compatible = "arm,mhuv2-rx","arm,primecell";
reg = <0x0 0x45010000 0x0 0x1000>;
clocks = <&soc_refclk100mhz>;
clock-names = "apb_pclk";
- #mbox-cells = <1>;
+ #mbox-cells = <2>;
interrupts = <0 317 4>;
interrupt-names = "mhu_rx";
mhu-protocol = "doorbell";
+ arm,mhuv2-protocols = <0 1>;
};
mbox_db_tx: mhu@45000000 {
- compatible = "arm,mhuv2","arm,primecell";
+ compatible = "arm,mhuv2-tx","arm,primecell";
reg = <0x0 0x45000000 0x0 0x1000>;
clocks = <&soc_refclk100mhz>;
clock-names = "apb_pclk";
- #mbox-cells = <1>;
+ #mbox-cells = <2>;
interrupt-names = "mhu_tx";
mhu-protocol = "doorbell";
+ arm,mhuv2-protocols = <0 1>;
};
scmi {
compatible = "arm,scmi";
- method = "mailbox-doorbell";
mbox-names = "tx", "rx";
- mboxes = <&mbox_db_tx 0 &mbox_db_rx 0>;
+ mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index 0a42a5d..5753e90 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,6 +24,12 @@
#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1
+#define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
+
#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0
#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1
#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index 06b23d9..8c8f4d3 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -166,6 +166,34 @@
b cpu_rev_var_ls
endfunc check_errata_1946167
+ /* --------------------------------------------------
+ * Errata Workaround for Cortex A77 Errata #1791578.
+ * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a77_1791578_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_1791578
+ cbz x0, 1f
+
+ /* Set bit 2 in ACTLR2_EL1 */
+ mrs x1, CORTEX_A77_ACTLR2_EL1
+ orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
+ msr CORTEX_A77_ACTLR2_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_a77_1791578_wa
+
+func check_errata_1791578
+ /* Applies to r0p0, r1p0, and r1p1 right now */
+ mov x1, #0x11
+ b cpu_rev_var_ls
+endfunc check_errata_1791578
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A77.
* Shall clobber: x0-x19
@@ -191,6 +219,11 @@
bl errata_a77_1946167_wa
#endif
+#if ERRATA_A77_1791578
+ mov x0, x18
+ bl errata_a77_1791578_wa
+#endif
+
ret x19
endfunc cortex_a77_reset_func
@@ -227,6 +260,7 @@
report_errata ERRATA_A77_1508412, cortex_a77, 1508412
report_errata ERRATA_A77_1925769, cortex_a77, 1925769
report_errata ERRATA_A77_1946167, cortex_a77, 1946167
+ report_errata ERRATA_A77_1791578, cortex_a77, 1791578
ldp x8, x30, [sp], #16
ret
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 541a2a2..b1747af 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -294,6 +294,10 @@
# only to revision <= r1p1 of the Cortex A77 cpu.
ERRATA_A77_1946167 ?=0
+# Flag to apply erratum 1791578 workaround during reset. This erratum applies
+# to revisions r0p0, r1p0, and r1p1, it is still open.
+ERRATA_A77_1791578 ?=0
+
# Flag to apply erratum 1688305 workaround during reset. This erratum applies
# to revisions r0p0 - r1p0 of the A78 cpu.
ERRATA_A78_1688305 ?=0
@@ -597,6 +601,10 @@
$(eval $(call assert_boolean,ERRATA_A77_1946167))
$(eval $(call add_define,ERRATA_A77_1946167))
+# Process ERRATA_A77_1791578 flag
+$(eval $(call assert_boolean,ERRATA_A77_1791578))
+$(eval $(call add_define,ERRATA_A77_1791578))
+
# Process ERRATA_A78_1688305 flag
$(eval $(call assert_boolean,ERRATA_A78_1688305))
$(eval $(call add_define,ERRATA_A78_1688305))