Merge pull request #1813 from oscardagrach/hikey960-iomcu-dma
hikey960: enable IOMCU DMAC
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 728790a..b0ef422 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -969,7 +969,7 @@
fixed sample points at key places in the code.
- To support the QEMU platform port, imported libfdt v1.4.1 from
- https://git.kernel.org/cgit/utils/dtc/dtc.git
+ https://git.kernel.org/pub/scm/utils/dtc/dtc.git
- Updated PSCI support:
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index 40128ed..315457a 100644
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -189,8 +189,8 @@
.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
-.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf
-.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf
+.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
+.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html
.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
.. _Firmware Design guide: firmware-design.rst
.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst
index 5c0a927..74ff2f4 100644
--- a/docs/plat/hikey.rst
+++ b/docs/plat/hikey.rst
@@ -149,7 +149,7 @@
$sudo python hisi-idt.py -d /dev/ttyUSB1 --img1 recovery.bin
-- Update images. All aosp or debian images could be fetched from `link <https://builds.96boards.org/>`__.
+- Update images. All aosp or debian images could be fetched from `link <http://releases.linaro.org/96boards/>`__.
.. code:: shell
@@ -168,4 +168,4 @@
- Reference `link <https://github.com/96boards-hikey/tools-images-hikey960/blob/master/build-from-source/README-ATF-UEFI-build-from-source.md>`__
-.. _link: https://github.com/96boards/documentation/blob/master/ConsumerEdition/HiKey/Quickstart/README.md
+.. _link: https://www.96boards.org/documentation/consumer/hikey/
diff --git a/docs/plat/hikey960.rst b/docs/plat/hikey960.rst
index 7900b6d..7ddb0b1 100644
--- a/docs/plat/hikey960.rst
+++ b/docs/plat/hikey960.rst
@@ -189,4 +189,4 @@
- Reference `link <https://github.com/96boards-hikey/tools-images-hikey960/blob/master/build-from-source/README-ATF-UEFI-build-from-source.md>`__
-.. _link: http://www.96boards.org/documentation/ConsumerEdition/HiKey960/README.md
+.. _link: https://www.96boards.org/documentation/consumer/hikey/hikey960
diff --git a/docs/plat/meson-gxbb.rst b/docs/plat/meson-gxbb.rst
index f909e99..d76149e 100644
--- a/docs/plat/meson-gxbb.rst
+++ b/docs/plat/meson-gxbb.rst
@@ -23,4 +23,4 @@
instructions in the `U-Boot repository`_, replacing the mentioned **bl31.bin**
by the one built from this port.
-.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/board/amlogic/odroid-c2/README
+.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/board/amlogic/odroid-c2/README.odroid-c2
diff --git a/docs/platform-compatibility-policy.rst b/docs/platform-compatibility-policy.rst
index b23d539..6bab447 100644
--- a/docs/platform-compatibility-policy.rst
+++ b/docs/platform-compatibility-policy.rst
@@ -41,5 +41,5 @@
*Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.*
.. _Porting Guide: ./porting-guide.rst
-.. _Release information: https://github.com/ARM-software/arm-trusted-firmware/wiki/TF-A-Release-information#2removal-of-deprecated-interfaces
+.. _Release information: https://github.com/ARM-software/arm-trusted-firmware/wiki/TF-A-Release-information#removal-of-deprecated-interfaces
.. _tf-issue: https://github.com/ARM-software/tf-issues/issues
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 422c340..7c2a4d4 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -2808,5 +2808,5 @@
.. _IMF Design Guide: interrupt-framework-design.rst
.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
-.. _FreeBSD: http://www.freebsd.org
+.. _FreeBSD: https://www.freebsd.org
.. _SCC: http://www.simple-cc.org/
diff --git a/docs/trusted-board-boot.rst b/docs/trusted-board-boot.rst
index 33005e3..1ca6fef 100644
--- a/docs/trusted-board-boot.rst
+++ b/docs/trusted-board-boot.rst
@@ -233,6 +233,6 @@
*Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.*
.. _Firmware Update: firmware-update.rst
-.. _X.509 v3: http://www.ietf.org/rfc/rfc5280.txt
+.. _X.509 v3: https://tools.ietf.org/rfc/rfc5280.txt
.. _User Guide: user-guide.rst
.. _Auth Framework: auth-framework.rst
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 386c28e..4ff1c72 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -2060,11 +2060,11 @@
.. _Linaro: `Linaro Release Notes`_
.. _Linaro Release: `Linaro Release Notes`_
-.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes
-.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/linaro-software-deliverables
+.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
+.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
-.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
+.. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
.. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html
.. _Linux master tree: https://github.com/torvalds/linux/tree/master/
.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
diff --git a/drivers/imx/uart/imx_uart.c b/drivers/imx/uart/imx_uart.c
index 68d31c8..2c9652d 100644
--- a/drivers/imx/uart/imx_uart.c
+++ b/drivers/imx/uart/imx_uart.c
@@ -62,8 +62,8 @@
return mmio_read_32(base + offset);
}
-int console_core_init(uintptr_t base_addr, unsigned int uart_clk,
- unsigned int baud_rate)
+int console_imx_uart_core_init(uintptr_t base_addr, unsigned int uart_clk,
+ unsigned int baud_rate)
{
uint32_t val;
uint8_t clk_idx = 1;
@@ -129,12 +129,12 @@
* Clobber list : r2
* --------------------------------------------------------
*/
-int console_core_putc(int c, uintptr_t base_addr)
+int console_imx_uart_core_putc(int c, uintptr_t base_addr)
{
uint32_t val;
if (c == '\n')
- console_core_putc('\r', base_addr);
+ console_imx_uart_core_putc('\r', base_addr);
/* Write data */
write_reg(base_addr, IMX_UART_TXD_OFFSET, c);
@@ -155,7 +155,7 @@
* Clobber list : r0, r1
* ---------------------------------------------
*/
-int console_core_getc(uintptr_t base_addr)
+int console_imx_uart_core_getc(uintptr_t base_addr)
{
uint32_t val;
@@ -175,7 +175,7 @@
* Clobber list : r0, r1
* ---------------------------------------------
*/
-int console_core_flush(uintptr_t base_addr)
+int console_imx_uart_core_flush(uintptr_t base_addr)
{
return 0;
}
diff --git a/drivers/imx/uart/imx_uart.h b/drivers/imx/uart/imx_uart.h
index c3edbc7..b71504c 100644
--- a/drivers/imx/uart/imx_uart.h
+++ b/drivers/imx/uart/imx_uart.h
@@ -6,6 +6,8 @@
#ifndef IMX_UART_H
#define IMX_UART_H
+#include <drivers/console.h>
+
#define IMX_UART_RXD_OFFSET 0x00
#define IMX_UART_RXD_CHARRDY BIT(15)
#define IMX_UART_RXD_ERR BIT(14)
@@ -150,4 +152,17 @@
#define IMX_UART_TS_RXFULL BIT(3)
#define IMX_UART_TS_SOFTRST BIT(0)
+#ifndef __ASSEMBLY__
+
+typedef struct {
+ console_t console;
+ uintptr_t base;
+} console_imx_uart_t;
+
+int console_imx_uart_register(uintptr_t baseaddr,
+ uint32_t clock,
+ uint32_t baud,
+ console_imx_uart_t *console);
+#endif /*__ASSEMBLY__*/
+
#endif /* IMX_UART_H */
diff --git a/include/lib/cpus/aarch32/aem_generic.h b/include/lib/cpus/aarch32/aem_generic.h
index 5fbdf53..1d40cec 100644
--- a/include/lib/cpus/aarch32/aem_generic.h
+++ b/include/lib/cpus/aarch32/aem_generic.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,9 @@
#ifndef AEM_GENERIC_H
#define AEM_GENERIC_H
+#include <lib/utils_def.h>
+
/* BASE AEM midr for revision 0 */
-#define BASE_AEM_MIDR 0x410FD0F0
+#define BASE_AEM_MIDR U(0x410FD0F0)
#endif /* AEM_GENERIC_H */
diff --git a/include/lib/cpus/aarch32/cortex_a12.h b/include/lib/cpus/aarch32/cortex_a12.h
index 3aa7278..8f6e7b8 100644
--- a/include/lib/cpus/aarch32/cortex_a12.h
+++ b/include/lib/cpus/aarch32/cortex_a12.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,14 +7,16 @@
#ifndef CORTEX_A12_H
#define CORTEX_A12_H
+#include <lib/utils_def.h>
+
/*******************************************************************************
* Cortex-A12 midr with version/revision set to 0
******************************************************************************/
-#define CORTEX_A12_MIDR 0x410FC0C0
+#define CORTEX_A12_MIDR U(0x410FC0C0)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A12_ACTLR_SMP_BIT (1 << 6)
+#define CORTEX_A12_ACTLR_SMP_BIT (U(1) << 6)
#endif /* CORTEX_A12_H */
diff --git a/include/lib/cpus/aarch32/cortex_a15.h b/include/lib/cpus/aarch32/cortex_a15.h
index ca842f6..957afbd 100644
--- a/include/lib/cpus/aarch32/cortex_a15.h
+++ b/include/lib/cpus/aarch32/cortex_a15.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,15 +7,17 @@
#ifndef CORTEX_A15_H
#define CORTEX_A15_H
+#include <lib/utils_def.h>
+
/*******************************************************************************
* Cortex-A15 midr with version/revision set to 0
******************************************************************************/
-#define CORTEX_A15_MIDR 0x410FC0F0
+#define CORTEX_A15_MIDR U(0x410FC0F0)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A15_ACTLR_INV_BTB_BIT (1 << 0)
-#define CORTEX_A15_ACTLR_SMP_BIT (1 << 6)
+#define CORTEX_A15_ACTLR_INV_BTB_BIT (U(1) << 0)
+#define CORTEX_A15_ACTLR_SMP_BIT (U(1) << 6)
#endif /* CORTEX_A15_H */
diff --git a/include/lib/cpus/aarch32/cortex_a17.h b/include/lib/cpus/aarch32/cortex_a17.h
index b5a4a90..4b05216 100644
--- a/include/lib/cpus/aarch32/cortex_a17.h
+++ b/include/lib/cpus/aarch32/cortex_a17.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,14 +7,16 @@
#ifndef CORTEX_A17_H
#define CORTEX_A17_H
+#include <lib/utils_def.h>
+
/*******************************************************************************
* Cortex-A17 midr with version/revision set to 0
******************************************************************************/
-#define CORTEX_A17_MIDR 0x410FC0E0
+#define CORTEX_A17_MIDR U(0x410FC0E0)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A17_ACTLR_SMP_BIT (1 << 6)
+#define CORTEX_A17_ACTLR_SMP_BIT (U(1) << 6)
#endif /* CORTEX_A17_H */
diff --git a/include/lib/cpus/aarch32/cortex_a32.h b/include/lib/cpus/aarch32/cortex_a32.h
index 36322d2..6ddd533 100644
--- a/include/lib/cpus/aarch32/cortex_a32.h
+++ b/include/lib/cpus/aarch32/cortex_a32.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,14 +7,16 @@
#ifndef CORTEX_A32_H
#define CORTEX_A32_H
+#include <lib/utils_def.h>
+
/* Cortex-A32 Main ID register for revision 0 */
-#define CORTEX_A32_MIDR 0x410FD010
+#define CORTEX_A32_MIDR U(0x410FD010)
/*******************************************************************************
* CPU Extended Control register specific definitions.
* CPUECTLR_EL1 is an implementation-specific register.
******************************************************************************/
#define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15
-#define CORTEX_A32_CPUECTLR_SMPEN_BIT (1 << 6)
+#define CORTEX_A32_CPUECTLR_SMPEN_BIT (ULL(1) << 6)
#endif /* CORTEX_A32_H */
diff --git a/include/lib/cpus/aarch32/cortex_a5.h b/include/lib/cpus/aarch32/cortex_a5.h
index 3e58f25..76703b7 100644
--- a/include/lib/cpus/aarch32/cortex_a5.h
+++ b/include/lib/cpus/aarch32/cortex_a5.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,14 +7,16 @@
#ifndef CORTEX_A5_H
#define CORTEX_A5_H
+#include <lib/utils_def.h>
+
/*******************************************************************************
* Cortex-A8 midr with version/revision set to 0
******************************************************************************/
-#define CORTEX_A5_MIDR 0x410FC050
+#define CORTEX_A5_MIDR U(0x410FC050)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A5_ACTLR_SMP_BIT (1 << 6)
+#define CORTEX_A5_ACTLR_SMP_BIT (U(1) << 6)
#endif /* CORTEX_A5_H */
diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h
index a2d7ec0..8dd0192 100644
--- a/include/lib/cpus/aarch32/cortex_a53.h
+++ b/include/lib/cpus/aarch32/cortex_a53.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,30 +7,32 @@
#ifndef CORTEX_A53_H
#define CORTEX_A53_H
+#include <lib/utils_def.h>
+
/* Cortex-A53 midr for revision 0 */
-#define CORTEX_A53_MIDR 0x410FD030
+#define CORTEX_A53_MIDR U(0x410FD030)
/* Retention timer tick definitions */
-#define RETENTION_ENTRY_TICKS_2 0x1
-#define RETENTION_ENTRY_TICKS_8 0x2
-#define RETENTION_ENTRY_TICKS_32 0x3
-#define RETENTION_ENTRY_TICKS_64 0x4
-#define RETENTION_ENTRY_TICKS_128 0x5
-#define RETENTION_ENTRY_TICKS_256 0x6
-#define RETENTION_ENTRY_TICKS_512 0x7
+#define RETENTION_ENTRY_TICKS_2 U(0x1)
+#define RETENTION_ENTRY_TICKS_8 U(0x2)
+#define RETENTION_ENTRY_TICKS_32 U(0x3)
+#define RETENTION_ENTRY_TICKS_64 U(0x4)
+#define RETENTION_ENTRY_TICKS_128 U(0x5)
+#define RETENTION_ENTRY_TICKS_256 U(0x6)
+#define RETENTION_ENTRY_TICKS_512 U(0x7)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A53_ECTLR p15, 1, c15
-#define CORTEX_A53_ECTLR_SMP_BIT (1 << 6)
+#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6)
-#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT 0
-#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
+#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
+#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
-#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT 3
-#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
+#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
+#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
@@ -42,25 +44,26 @@
******************************************************************************/
#define CORTEX_A53_CPUACTLR p15, 0, c15
-#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT 44
-#define CORTEX_A53_CPUACTLR_ENDCCASCI (1 << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT)
-#define CORTEX_A53_CPUACTLR_DTAH (1 << 24)
+#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT U(44)
+#define CORTEX_A53_CPUACTLR_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT)
+#define CORTEX_A53_CPUACTLR_DTAH_SHIFT U(24)
+#define CORTEX_A53_CPUACTLR_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_DTAH_SHIFT)
/*******************************************************************************
* L2 Auxiliary Control register specific definitions.
******************************************************************************/
#define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0
-#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14)
-#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3)
+#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
+#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
/*******************************************************************************
* L2 Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3
-#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT 0
-#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
+#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
+#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h
index 2ac1e17..f7005da 100644
--- a/include/lib/cpus/aarch32/cortex_a57.h
+++ b/include/lib/cpus/aarch32/cortex_a57.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,16 +10,16 @@
#include <lib/utils_def.h>
/* Cortex-A57 midr for revision 0 */
-#define CORTEX_A57_MIDR 0x410FD070
+#define CORTEX_A57_MIDR U(0x410FD070)
/* Retention timer tick definitions */
-#define RETENTION_ENTRY_TICKS_2 0x1
-#define RETENTION_ENTRY_TICKS_8 0x2
-#define RETENTION_ENTRY_TICKS_32 0x3
-#define RETENTION_ENTRY_TICKS_64 0x4
-#define RETENTION_ENTRY_TICKS_128 0x5
-#define RETENTION_ENTRY_TICKS_256 0x6
-#define RETENTION_ENTRY_TICKS_512 0x7
+#define RETENTION_ENTRY_TICKS_2 U(0x1)
+#define RETENTION_ENTRY_TICKS_8 U(0x2)
+#define RETENTION_ENTRY_TICKS_32 U(0x3)
+#define RETENTION_ENTRY_TICKS_64 U(0x4)
+#define RETENTION_ENTRY_TICKS_128 U(0x5)
+#define RETENTION_ENTRY_TICKS_256 U(0x6)
+#define RETENTION_ENTRY_TICKS_512 U(0x7)
/*******************************************************************************
* CPU Extended Control register specific definitions.
@@ -31,7 +31,7 @@
#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
-#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0
+#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0)
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
/*******************************************************************************
@@ -61,19 +61,19 @@
******************************************************************************/
#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
-#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
-#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
+#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
+#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
-#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
-#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
+#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
+#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
/*******************************************************************************
* L2 Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
-#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0
-#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
+#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0)
+#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
diff --git a/include/lib/cpus/aarch32/cortex_a7.h b/include/lib/cpus/aarch32/cortex_a7.h
index 03fc118..730fdb5 100644
--- a/include/lib/cpus/aarch32/cortex_a7.h
+++ b/include/lib/cpus/aarch32/cortex_a7.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,14 +7,16 @@
#ifndef CORTEX_A7_H
#define CORTEX_A7_H
+#include <lib/utils_def.h>
+
/*******************************************************************************
* Cortex-A7 midr with version/revision set to 0
******************************************************************************/
-#define CORTEX_A7_MIDR 0x410FC070
+#define CORTEX_A7_MIDR U(0x410FC070)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A7_ACTLR_SMP_BIT (1 << 6)
+#define CORTEX_A7_ACTLR_SMP_BIT (U(1) << 6)
#endif /* CORTEX_A7_H */
diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h
index 95402d0..4b1af61 100644
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,7 @@
#include <lib/utils_def.h>
/* Cortex-A72 midr for revision 0 */
-#define CORTEX_A72_MIDR 0x410FD080
+#define CORTEX_A72_MIDR U(0x410FD080)
/*******************************************************************************
* CPU Extended Control register specific definitions.
@@ -43,12 +43,12 @@
******************************************************************************/
#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
-#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
-#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
+#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
+#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
-#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
-#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
-#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
diff --git a/include/lib/cpus/aarch32/cortex_a9.h b/include/lib/cpus/aarch32/cortex_a9.h
index a9e86ef..1fb0a92 100644
--- a/include/lib/cpus/aarch32/cortex_a9.h
+++ b/include/lib/cpus/aarch32/cortex_a9.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,16 +7,18 @@
#ifndef CORTEX_A9_H
#define CORTEX_A9_H
+#include <lib/utils_def.h>
+
/*******************************************************************************
* Cortex-A9 midr with version/revision set to 0
******************************************************************************/
-#define CORTEX_A9_MIDR 0x410FC090
+#define CORTEX_A9_MIDR U(0x410FC090)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A9_ACTLR_SMP_BIT (1 << 6)
-#define CORTEX_A9_ACTLR_FLZW_BIT (1 << 3)
+#define CORTEX_A9_ACTLR_SMP_BIT (U(1) << 6)
+#define CORTEX_A9_ACTLR_FLZW_BIT (U(1) << 3)
/*******************************************************************************
* CPU Power Control Register
diff --git a/include/lib/cpus/aarch64/aem_generic.h b/include/lib/cpus/aarch64/aem_generic.h
index 1edef84..6bb30a2 100644
--- a/include/lib/cpus/aarch64/aem_generic.h
+++ b/include/lib/cpus/aarch64/aem_generic.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,10 +7,12 @@
#ifndef AEM_GENERIC_H
#define AEM_GENERIC_H
+#include <lib/utils_def.h>
+
/* BASE AEM midr for revision 0 */
-#define BASE_AEM_MIDR 0x410FD0F0
+#define BASE_AEM_MIDR U(0x410FD0F0)
/* Foundation AEM midr for revision 0 */
-#define FOUNDATION_AEM_MIDR 0x410FD000
+#define FOUNDATION_AEM_MIDR U(0x410FD000)
#endif /* AEM_GENERIC_H */
diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h
index 2363198..0678804 100644
--- a/include/lib/cpus/aarch64/cortex_a35.h
+++ b/include/lib/cpus/aarch64/cortex_a35.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,14 +7,16 @@
#ifndef CORTEX_A35_H
#define CORTEX_A35_H
+#include <lib/utils_def.h>
+
/* Cortex-A35 Main ID register for revision 0 */
-#define CORTEX_A35_MIDR 0x410FD040
+#define CORTEX_A35_MIDR U(0x410FD040)
/*******************************************************************************
* CPU Extended Control register specific definitions.
* CPUECTLR_EL1 is an implementation-specific register.
******************************************************************************/
#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1
-#define CORTEX_A35_CPUECTLR_SMPEN_BIT (1 << 6)
+#define CORTEX_A35_CPUECTLR_SMPEN_BIT (ULL(1) << 6)
#endif /* CORTEX_A35_H */
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 4b7d238..09db12b 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,8 @@
#ifndef CORTEX_A53_H
#define CORTEX_A53_H
+#include <lib/utils_def.h>
+
/* Cortex-A53 midr for revision 0 */
#define CORTEX_A53_MIDR U(0x410FD030)
@@ -24,13 +26,13 @@
******************************************************************************/
#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1
-#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6)
+#define CORTEX_A53_ECTLR_SMP_BIT (ULL(1) << 6)
#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
-#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
+#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
-#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
+#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
@@ -43,13 +45,13 @@
#define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0
#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44)
-#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27)
-#define CORTEX_A53_CPUACTLR_EL1_RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25)
-#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24)
-#define CORTEX_A53_CPUACTLR_EL1_DTAH (U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
/*******************************************************************************
* L2 Auxiliary Control register specific definitions.
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h
index 763b7cb..8b21e16 100644
--- a/include/lib/cpus/aarch64/cortex_a55.h
+++ b/include/lib/cpus/aarch64/cortex_a55.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,16 +7,18 @@
#ifndef CORTEX_A55_H
#define CORTEX_A55_H
+#include <lib/utils_def.h>
+
/* Cortex-A55 MIDR for revision 0 */
-#define CORTEX_A55_MIDR 0x410fd050
+#define CORTEX_A55_MIDR U(0x410fd050)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
-#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4
/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
-#define CORTEX_A55_CORE_PWRDN_EN_MASK 0x1
+#define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1)
#endif /* CORTEX_A55_H */
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index 5b6c9dd..1e68f21 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,13 +26,13 @@
******************************************************************************/
#define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1
-#define CORTEX_A57_ECTLR_SMP_BIT (U(1) << 6)
-#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (U(1) << 38)
-#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (U(0x3) << 35)
-#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (U(0x3) << 32)
+#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
+#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
+#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
+#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0)
-#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
+#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index 60b6c61..4a444c6 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,7 @@
#include <lib/utils_def.h>
/* Cortex-A72 midr for revision 0 */
-#define CORTEX_A72_MIDR 0x410FD080
+#define CORTEX_A72_MIDR U(0x410FD080)
/*******************************************************************************
* CPU Extended Control register specific definitions.
@@ -50,12 +50,12 @@
******************************************************************************/
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
-#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
-#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
+#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
+#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
-#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
-#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
-#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h
index 77ea205..3b40180 100644
--- a/include/lib/cpus/aarch64/cortex_a73.h
+++ b/include/lib/cpus/aarch64/cortex_a73.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,15 +7,17 @@
#ifndef CORTEX_A73_H
#define CORTEX_A73_H
+#include <lib/utils_def.h>
+
/* Cortex-A73 midr for revision 0 */
-#define CORTEX_A73_MIDR 0x410FD090
+#define CORTEX_A73_MIDR U(0x410FD090)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
-#define CORTEX_A73_CPUECTLR_SMP_BIT (1 << 6)
+#define CORTEX_A73_CPUECTLR_SMP_BIT (ULL(1) << 6)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
@@ -27,6 +29,6 @@
******************************************************************************/
#define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0
-#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (1 << 3)
+#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3)
#endif /* CORTEX_A73_H */
diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index fabc1af..204bfdd 100644
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,12 +23,12 @@
******************************************************************************/
#define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0
-#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (1 << 35)
+#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 35)
/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
#define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1)
-#define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4)
+#define CORTEX_A75_ACTLR_AMEN_BIT (ULL(1) << 4)
/*
* The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h
index 4dea64b..5779d7b 100644
--- a/include/lib/cpus/aarch64/cortex_a76.h
+++ b/include/lib/cpus/aarch64/cortex_a76.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,23 +7,25 @@
#ifndef CORTEX_A76_H
#define CORTEX_A76_H
+#include <lib/utils_def.h>
+
/* Cortex-A76 MIDR for revision 0 */
-#define CORTEX_A76_MIDR 0x410fd0b0
+#define CORTEX_A76_MIDR U(0x410fd0b0)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
-#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (1 << 16)
+#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
-#define CORTEX_A76_CORE_PWRDN_EN_MASK 0x1
+#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1)
#endif /* CORTEX_A76_H */
diff --git a/include/lib/cpus/aarch64/cortex_deimos.h b/include/lib/cpus/aarch64/cortex_deimos.h
index 694fb15..9d024b6 100644
--- a/include/lib/cpus/aarch64/cortex_deimos.h
+++ b/include/lib/cpus/aarch64/cortex_deimos.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,8 @@
#ifndef CORTEX_DEIMOS_H
#define CORTEX_DEIMOS_H
+#include <lib/utils_def.h>
+
#define CORTEX_DEIMOS_MIDR U(0x410FD0D0)
/*******************************************************************************
diff --git a/include/lib/cpus/aarch64/cortex_helios.h b/include/lib/cpus/aarch64/cortex_helios.h
index 571ea9d..0c11a9a 100644
--- a/include/lib/cpus/aarch64/cortex_helios.h
+++ b/include/lib/cpus/aarch64/cortex_helios.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,8 @@
#ifndef CORTEX_HELIOS_H
#define CORTEX_HELIOS_H
+#include <lib/utils_def.h>
+
#define CORTEX_HELIOS_MIDR U(0x410FD060)
/*******************************************************************************
diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h
index aa8b1b1..b7ba28a 100644
--- a/include/lib/cpus/aarch64/dsu_def.h
+++ b/include/lib/cpus/aarch64/dsu_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,6 +28,6 @@
/********************************************************************
* Masks applied for DSU errata workarounds *
********************************************************************/
-#define DSU_ERRATA_936184_MASK (ULL(0x3) << 15)
+#define DSU_ERRATA_936184_MASK (U(0x3) << 15)
#endif /* DSU_DEF_H */
diff --git a/plat/imx/common/aarch32/imx_uart_console.S b/plat/imx/common/aarch32/imx_uart_console.S
new file mode 100644
index 0000000..e526d9c
--- /dev/null
+++ b/plat/imx/common/aarch32/imx_uart_console.S
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#define USE_FINISH_CONSOLE_REG_2
+#include <console_macros.S>
+#include <assert_macros.S>
+#include "imx_uart.h"
+
+ .globl console_imx_uart_register
+ .globl console_imx_uart_putc
+ .globl console_imx_uart_getc
+ .globl console_imx_uart_flush
+
+func console_imx_uart_register
+ push {r4, lr}
+ mov r4, r3
+ cmp r4, #0
+ beq register_fail
+ str r0, [r4, #CONSOLE_T_DRVDATA]
+
+ bl console_imx_uart_core_init
+ cmp r0, #0
+ bne register_fail
+
+ mov r0, r4
+ pop {r4, lr}
+ finish_console_register imx_uart putc=1, getc=1, flush=1
+
+register_fail:
+ pop {r4, pc}
+endfunc console_imx_uart_register
+
+func console_imx_uart_putc
+ ldr r1, [r1, #CONSOLE_T_DRVDATA]
+ b console_imx_uart_core_putc
+endfunc console_imx_uart_putc
+
+func console_imx_uart_getc
+ ldr r0, [r0, #CONSOLE_T_DRVDATA]
+ b console_imx_uart_core_getc
+endfunc console_imx_uart_getc
+
+func console_imx_uart_flush
+ ldr r0, [r0, #CONSOLE_T_DRVDATA]
+ b console_imx_uart_core_flush
+endfunc console_imx_uart_flush
diff --git a/plat/imx/imx7/warp7/platform.mk b/plat/imx/imx7/warp7/platform.mk
index f29f779..6cd7566 100644
--- a/plat/imx/imx7/warp7/platform.mk
+++ b/plat/imx/imx7/warp7/platform.mk
@@ -59,6 +59,7 @@
plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c \
plat/imx/imx7/warp7/warp7_io_storage.c \
plat/imx/imx7/warp7/warp7_image_load.c \
+ plat/imx/common/aarch32/imx_uart_console.S \
${XLAT_TABLES_LIB_SRCS}
ifneq (${TRUSTED_BOARD_BOOT},0)
@@ -118,6 +119,9 @@
# Use Coherent memory
USE_COHERENT_MEM := 1
+# Use multi console API
+MULTI_CONSOLE_API := 1
+
# PLAT_WARP7_UART
PLAT_WARP7_UART :=1
$(eval $(call add_define,PLAT_WARP7_UART))
diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
index 08baf19..0eedd21 100644
--- a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
+++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
@@ -258,6 +258,8 @@
uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT;
uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT;
uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1;
+ static console_imx_uart_t console;
+ int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME;
/* Initialize the AIPS */
imx_aips_init();
@@ -278,8 +280,12 @@
warp7_setup_pinmux();
/* Init UART, storage and friends */
- console_init(PLAT_WARP7_BOOT_UART_BASE, PLAT_WARP7_BOOT_UART_CLK_IN_HZ,
- PLAT_WARP7_CONSOLE_BAUDRATE);
+ console_imx_uart_register(PLAT_WARP7_BOOT_UART_BASE,
+ PLAT_WARP7_BOOT_UART_CLK_IN_HZ,
+ PLAT_WARP7_CONSOLE_BAUDRATE,
+ &console);
+ console_set_scope(&console.console, console_scope);
+
warp7_usdhc_setup();
/* Open handles to persistent storage */
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
index 4a33d34..df0b794 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
@@ -95,7 +95,7 @@
hdr->seq = info.seq;
hdr->type = msg_type;
hdr->host = info.desc.host_id;
- hdr->flags = msg_flags;
+ hdr->flags = msg_flags | TI_SCI_FLAG_REQ_ACK_ON_PROCESSED;
xfer->tx_message.buf = tx_buf;
xfer->tx_message.len = tx_message_size;
@@ -143,6 +143,9 @@
return -EINVAL;
}
+ if (!(hdr->flags & TI_SCI_FLAG_RESP_GENERIC_ACK))
+ return -ENODEV;
+
return 0;
}
@@ -214,20 +217,6 @@
}
/**
- * ti_sci_is_response_ack() - Generic ACK/NACK message check
- *
- * @r: pointer to response buffer
- *
- * Return: true if the response was an ACK, else returns false
- */
-static inline bool ti_sci_is_response_ack(void *r)
-{
- struct ti_sci_msg_hdr *hdr = r;
-
- return hdr->flags & TI_SCI_FLAG_RESP_GENERIC_ACK ? true : false;
-}
-
-/**
* ti_sci_device_set_state() - Set device state
*
* @id: Device identifier
@@ -236,7 +225,7 @@
*
* Return: 0 if all goes well, else appropriate error message
*/
-int ti_sci_device_set_state(uint32_t id, uint32_t flags, uint8_t state)
+static int ti_sci_device_set_state(uint32_t id, uint32_t flags, uint8_t state)
{
struct ti_sci_msg_req_set_device_state req;
struct ti_sci_msg_hdr resp;
@@ -244,8 +233,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SET_DEVICE_STATE,
- flags | TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SET_DEVICE_STATE, flags,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -263,9 +251,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
@@ -280,8 +265,9 @@
*
* Return: 0 if all goes well, else appropriate error message
*/
-int ti_sci_device_get_state(uint32_t id, uint32_t *clcnt, uint32_t *resets,
- uint8_t *p_state, uint8_t *c_state)
+static int ti_sci_device_get_state(uint32_t id, uint32_t *clcnt,
+ uint32_t *resets, uint8_t *p_state,
+ uint8_t *c_state)
{
struct ti_sci_msg_req_get_device_state req;
struct ti_sci_msg_resp_get_device_state resp;
@@ -309,9 +295,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
if (clcnt)
*clcnt = resp.context_loss_count;
if (resets)
@@ -333,12 +316,31 @@
* usage count by balancing get_device with put_device. No refcounting is
* managed by driver for that purpose.
*
- * NOTE: The request is for exclusive access for the processor.
- *
* Return: 0 if all goes well, else appropriate error message
*/
int ti_sci_device_get(uint32_t id)
{
+ return ti_sci_device_set_state(id, 0, MSG_DEVICE_SW_STATE_ON);
+}
+
+/**
+ * ti_sci_device_get_exclusive() - Exclusive request for device managed by TISCI
+ *
+ * @id: Device Identifier
+ *
+ * Request for the device - NOTE: the client MUST maintain integrity of
+ * usage count by balancing get_device with put_device. No refcounting is
+ * managed by driver for that purpose.
+ *
+ * NOTE: This _exclusive version of the get API is for exclusive access to the
+ * device. Any other host in the system will fail to get this device after this
+ * call until exclusive access is released with device_put or a non-exclusive
+ * set call.
+ *
+ * Return: 0 if all goes well, else appropriate error message
+ */
+int ti_sci_device_get_exclusive(uint32_t id)
+{
return ti_sci_device_set_state(id,
MSG_FLAG_DEVICE_EXCLUSIVE,
MSG_DEVICE_SW_STATE_ON);
@@ -357,6 +359,27 @@
*/
int ti_sci_device_idle(uint32_t id)
{
+ return ti_sci_device_set_state(id, 0, MSG_DEVICE_SW_STATE_RETENTION);
+}
+
+/**
+ * ti_sci_device_idle_exclusive() - Exclusive idle a device managed by TISCI
+ *
+ * @id: Device Identifier
+ *
+ * Request for the device - NOTE: the client MUST maintain integrity of
+ * usage count by balancing get_device with put_device. No refcounting is
+ * managed by driver for that purpose.
+ *
+ * NOTE: This _exclusive version of the idle API is for exclusive access to
+ * the device. Any other host in the system will fail to get this device after
+ * this call until exclusive access is released with device_put or a
+ * non-exclusive set call.
+ *
+ * Return: 0 if all goes well, else appropriate error message
+ */
+int ti_sci_device_idle_exclusive(uint32_t id)
+{
return ti_sci_device_set_state(id,
MSG_FLAG_DEVICE_EXCLUSIVE,
MSG_DEVICE_SW_STATE_RETENTION);
@@ -379,6 +402,53 @@
}
/**
+ * ti_sci_device_put_no_wait() - Release a device without requesting or waiting
+ * for a response.
+ *
+ * @id: Device Identifier
+ *
+ * Request for the device - NOTE: the client MUST maintain integrity of
+ * usage count by balancing get_device with put_device. No refcounting is
+ * managed by driver for that purpose.
+ *
+ * Return: 0 if all goes well, else appropriate error message
+ */
+int ti_sci_device_put_no_wait(uint32_t id)
+{
+ struct ti_sci_msg_req_set_device_state req;
+ struct ti_sci_msg_hdr *hdr;
+ struct k3_sec_proxy_msg tx_message;
+ int ret;
+
+ /* Ensure we have sane transfer size */
+ if (sizeof(req) > info.desc.max_msg_size)
+ return -ERANGE;
+
+ hdr = (struct ti_sci_msg_hdr *)&req;
+ hdr->seq = info.seq;
+ hdr->type = TI_SCI_MSG_SET_DEVICE_STATE;
+ hdr->host = info.desc.host_id;
+ /* Setup with NORESPONSE flag to keep response queue clean */
+ hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE;
+
+ req.id = id;
+ req.state = MSG_DEVICE_SW_STATE_AUTO_OFF;
+
+ tx_message.buf = (uint8_t *)&req;
+ tx_message.len = sizeof(req);
+
+ /* Send message */
+ ret = k3_sec_proxy_send(SP_HIGH_PRIORITY, &tx_message);
+ if (ret) {
+ ERROR("Message sending failed (%d)\n", ret);
+ return ret;
+ }
+
+ /* Return without waiting for response */
+ return 0;
+}
+
+/**
* ti_sci_device_is_valid() - Is the device valid
*
* @id: Device Identifier
@@ -532,8 +602,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SET_DEVICE_RESETS,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SET_DEVICE_RESETS, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -551,9 +620,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
@@ -591,8 +657,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SET_CLOCK_STATE,
- flags | TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SET_CLOCK_STATE, flags,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -611,9 +676,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
@@ -642,8 +704,7 @@
if (!programmed_state && !current_state)
return -EINVAL;
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_GET_CLOCK_STATE,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TI_SCI_MSG_GET_CLOCK_STATE, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -661,9 +722,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
if (programmed_state)
*programmed_state = resp.programmed_state;
if (current_state)
@@ -848,8 +906,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SET_CLOCK_PARENT,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SET_CLOCK_PARENT, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -868,9 +925,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
@@ -893,8 +947,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_GET_CLOCK_PARENT,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TI_SCI_MSG_GET_CLOCK_PARENT, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -912,9 +965,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
*parent_id = resp.parent_id;
return 0;
@@ -940,8 +990,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_GET_NUM_CLOCK_PARENTS,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -959,9 +1008,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
*num_parents = resp.num_parents;
return 0;
@@ -996,8 +1042,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_QUERY_CLOCK_FREQ,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TI_SCI_MSG_QUERY_CLOCK_FREQ, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1018,9 +1063,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
*match_freq = resp.freq_hz;
return 0;
@@ -1053,8 +1095,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SET_CLOCK_FREQ,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SET_CLOCK_FREQ, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1074,9 +1115,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
@@ -1099,8 +1137,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_GET_CLOCK_FREQ,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TI_SCI_MSG_GET_CLOCK_FREQ, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1118,9 +1155,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
*freq = resp.freq_hz;
return 0;
@@ -1139,8 +1173,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SYS_RESET,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SYS_RESET, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1155,9 +1188,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
@@ -1176,8 +1206,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_REQUEST,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_REQUEST, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1194,9 +1223,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
@@ -1215,8 +1241,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_RELEASE,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_RELEASE, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1233,9 +1258,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
@@ -1256,8 +1278,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_HANDOVER,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_HANDOVER, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1275,9 +1296,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
@@ -1300,8 +1318,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TISCI_MSG_SET_PROC_BOOT_CONFIG,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TISCI_MSG_SET_PROC_BOOT_CONFIG, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1323,9 +1340,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
@@ -1347,8 +1361,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TISCI_MSG_SET_PROC_BOOT_CTRL,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TISCI_MSG_SET_PROC_BOOT_CTRL, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1367,9 +1380,55 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
+ return 0;
+}
+
+/**
+ * ti_sci_proc_set_boot_ctrl_no_wait() - Set the processor boot control flags
+ * without requesting or waiting for a
+ * response.
+ *
+ * @proc_id: Processor ID this request is for
+ * @control_flags_set: Control flags to be set
+ * @control_flags_clear: Control flags to be cleared
+ *
+ * Return: 0 if all goes well, else appropriate error message
+ */
+int ti_sci_proc_set_boot_ctrl_no_wait(uint8_t proc_id,
+ uint32_t control_flags_set,
+ uint32_t control_flags_clear)
+{
+ struct ti_sci_msg_req_set_proc_boot_ctrl req;
+ struct ti_sci_msg_hdr *hdr;
+ struct k3_sec_proxy_msg tx_message;
+ int ret;
+
+ /* Ensure we have sane transfer size */
+ if (sizeof(req) > info.desc.max_msg_size)
+ return -ERANGE;
+
+ hdr = (struct ti_sci_msg_hdr *)&req;
+ hdr->seq = info.seq;
+ hdr->type = TISCI_MSG_SET_PROC_BOOT_CTRL;
+ hdr->host = info.desc.host_id;
+ /* Setup with NORESPONSE flag to keep response queue clean */
+ hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE;
+
+ req.processor_id = proc_id;
+ req.control_flags_set = control_flags_set;
+ req.control_flags_clear = control_flags_clear;
+
+ tx_message.buf = (uint8_t *)&req;
+ tx_message.len = sizeof(req);
+ /* Send message */
+ ret = k3_sec_proxy_send(SP_HIGH_PRIORITY, &tx_message);
+ if (ret) {
+ ERROR("Message sending failed (%d)\n", ret);
+ return ret;
+ }
+
+ /* Return without waiting for response */
return 0;
}
@@ -1390,8 +1449,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_AUTH_BOOT_IMIAGE,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_AUTH_BOOT_IMIAGE, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1411,9 +1469,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
@@ -1435,8 +1490,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TISCI_MSG_GET_PROC_BOOT_STATUS,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TISCI_MSG_GET_PROC_BOOT_STATUS, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1453,9 +1507,6 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
*bv = (resp.bootvector_low & TISCI_ADDR_LOW_MASK) |
(((uint64_t)resp.bootvector_high << TISCI_ADDR_HIGH_SHIFT) &
TISCI_ADDR_HIGH_MASK);
@@ -1515,8 +1566,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TISCI_MSG_WAIT_PROC_BOOT_STATUS,
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+ ret = ti_sci_setup_one_xfer(TISCI_MSG_WAIT_PROC_BOOT_STATUS, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
@@ -1541,91 +1591,92 @@
return ret;
}
- if (!ti_sci_is_response_ack(&resp))
- return -ENODEV;
-
return 0;
}
/**
- * ti_sci_proc_shutdown() - Shutdown Processor without waiting for ACKs
+ * ti_sci_proc_wait_boot_status_no_wait() - Wait for a processor boot status
+ * without requesting or waiting for
+ * a response.
*
- * @proc_id: Processor ID this request is for
- * @dev_id: Device identifier this request is for
+ * @proc_id: Processor ID this request is for
+ * @num_wait_iterations Total number of iterations we will check before
+ * we will timeout and give up
+ * @num_match_iterations How many iterations should we have continued
+ * status to account for status bits glitching.
+ * This is to make sure that match occurs for
+ * consecutive checks. This implies that the
+ * worst case should consider that the stable
+ * time should at the worst be num_wait_iterations
+ * num_match_iterations to prevent timeout.
+ * @delay_per_iteration_us Specifies how long to wait (in micro seconds)
+ * between each status checks. This is the minimum
+ * duration, and overhead of register reads and
+ * checks are on top of this and can vary based on
+ * varied conditions.
+ * @delay_before_iterations_us Specifies how long to wait (in micro seconds)
+ * before the very first check in the first
+ * iteration of status check loop. This is the
+ * minimum duration, and overhead of register
+ * reads and checks are.
+ * @status_flags_1_set_all_wait If non-zero, Specifies that all bits of the
+ * status matching this field requested MUST be 1.
+ * @status_flags_1_set_any_wait If non-zero, Specifies that at least one of the
+ * bits matching this field requested MUST be 1.
+ * @status_flags_1_clr_all_wait If non-zero, Specifies that all bits of the
+ * status matching this field requested MUST be 0.
+ * @status_flags_1_clr_any_wait If non-zero, Specifies that at least one of the
+ * bits matching this field requested MUST be 0.
*
* Return: 0 if all goes well, else appropriate error message
*/
-int ti_sci_proc_shutdown(uint8_t proc_id, uint32_t dev_id)
+int ti_sci_proc_wait_boot_status_no_wait(uint8_t proc_id,
+ uint8_t num_wait_iterations,
+ uint8_t num_match_iterations,
+ uint8_t delay_per_iteration_us,
+ uint8_t delay_before_iterations_us,
+ uint32_t status_flags_1_set_all_wait,
+ uint32_t status_flags_1_set_any_wait,
+ uint32_t status_flags_1_clr_all_wait,
+ uint32_t status_flags_1_clr_any_wait)
{
- struct ti_sci_msg_req_wait_proc_boot_status wait_req;
- struct ti_sci_msg_req_set_device_state set_req;
- /*
- * We will not be waiting for this response, but declare one anyway
- * to pass to the setup function so the checks will still pass
- */
- struct ti_sci_msg_hdr resp;
-
- struct ti_sci_xfer xfer;
+ struct ti_sci_msg_req_wait_proc_boot_status req;
+ struct ti_sci_msg_hdr *hdr;
+ struct k3_sec_proxy_msg tx_message;
int ret;
- /* Start by sending wait command */
+ /* Ensure we have sane transfer size */
+ if (sizeof(req) > info.desc.max_msg_size)
+ return -ERANGE;
+ hdr = (struct ti_sci_msg_hdr *)&req;
+ hdr->seq = info.seq;
+ hdr->type = TISCI_MSG_WAIT_PROC_BOOT_STATUS;
+ hdr->host = info.desc.host_id;
/* Setup with NORESPONSE flag to keep response queue clean */
- ret = ti_sci_setup_one_xfer(TISCI_MSG_WAIT_PROC_BOOT_STATUS,
- TI_SCI_FLAG_REQ_GENERIC_NORESPONSE,
- &wait_req, sizeof(wait_req),
- &resp, sizeof(resp),
- &xfer);
- if (ret) {
- ERROR("Message alloc failed (%d)\n", ret);
- return ret;
- }
-
- wait_req.processor_id = proc_id;
- /*
- * Wait maximum time to give us the best chance to get
- * to WFI before this command timeouts
- */
- wait_req.delay_before_iterations_us = UINT8_MAX;
- wait_req.num_wait_iterations = UINT8_MAX;
- wait_req.delay_per_iteration_us = UINT8_MAX; /* TODO: optimize time */
- wait_req.num_match_iterations = 2;
- wait_req.status_flags_1_set_all_wait = 0;
- /* Wait for either WFE or WFI */
- wait_req.status_flags_1_set_any_wait = PROC_BOOT_STATUS_FLAG_ARMV8_WFE |
- PROC_BOOT_STATUS_FLAG_ARMV8_WFI;
- wait_req.status_flags_1_clr_all_wait = 0;
- wait_req.status_flags_1_clr_any_wait = 0;
-
- /* Send wait message */
- ret = k3_sec_proxy_send(SP_HIGH_PRIORITY, &xfer.tx_message);
- if (ret) {
- ERROR("Message sending failed (%d)\n", ret);
- return ret;
- }
+ hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE;
- /* Now queue up the shutdown request */
- ret = ti_sci_setup_one_xfer(TI_SCI_MSG_SET_DEVICE_STATE,
- TI_SCI_FLAG_REQ_GENERIC_NORESPONSE,
- &set_req, sizeof(set_req),
- &resp, sizeof(resp),
- &xfer);
- if (ret) {
- ERROR("Message alloc failed (%d)\n", ret);
- return ret;
- }
+ req.processor_id = proc_id;
+ req.num_wait_iterations = num_wait_iterations;
+ req.num_match_iterations = num_match_iterations;
+ req.delay_per_iteration_us = delay_per_iteration_us;
+ req.delay_before_iterations_us = delay_before_iterations_us;
+ req.status_flags_1_set_all_wait = status_flags_1_set_all_wait;
+ req.status_flags_1_set_any_wait = status_flags_1_set_any_wait;
+ req.status_flags_1_clr_all_wait = status_flags_1_clr_all_wait;
+ req.status_flags_1_clr_any_wait = status_flags_1_clr_any_wait;
- set_req.id = dev_id;
- set_req.state = MSG_DEVICE_SW_STATE_AUTO_OFF;
+ tx_message.buf = (uint8_t *)&req;
+ tx_message.len = sizeof(req);
- /* Send shutdown message */
- ret = k3_sec_proxy_send(SP_HIGH_PRIORITY, &xfer.tx_message);
+ /* Send message */
+ ret = k3_sec_proxy_send(SP_HIGH_PRIORITY, &tx_message);
if (ret) {
ERROR("Message sending failed (%d)\n", ret);
return ret;
}
- /* Return without waiting for responses */
+ /* Return without waiting for response */
return 0;
}
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.h b/plat/ti/k3/common/drivers/ti_sci/ti_sci.h
index d07ee61..c7b09b3 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.h
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.h
@@ -16,17 +16,12 @@
/**
* Device control operations
*
- * - ti_sci_device_set_state - Set device state helper
- * @flags: flags to setup for the device
- * @state: State to move the device to
- * - ti_sci_device_get_state - Get device state helper
- * @clcnt: Pointer to Context Loss Count
- * @resets: pointer to resets
- * @p_state: pointer to p_state
- * @c_state: pointer to c_state
* - ti_sci_device_get - command to request for device managed by TISCI
+ * - ti_sci_device_get_exclusive - exclusively request a device
* - ti_sci_device_idle - Command to idle a device managed by TISCI
+ * - ti_sci_device_idle_exclusive - exclusively idle a device
* - ti_sci_device_put - command to release a device managed by TISCI
+ * - ti_sci_device_put_no_wait - release a device without waiting for response
* - ti_sci_device_is_valid - Is the device valid
* - ti_sci_device_get_clcnt - Get context loss counter
* @count: Pointer to Context Loss counter to populate
@@ -54,12 +49,12 @@
* usage count by balancing get_device with put_device. No refcounting is
* managed by driver for that purpose.
*/
-int ti_sci_device_set_state(uint32_t id, uint32_t flags, uint8_t state);
-int ti_sci_device_get_state(uint32_t id, uint32_t *clcnt, uint32_t *resets,
- uint8_t *p_state, uint8_t *c_state);
int ti_sci_device_get(uint32_t id);
+int ti_sci_device_get_exclusive(uint32_t id);
int ti_sci_device_idle(uint32_t id);
+int ti_sci_device_idle_exclusive(uint32_t id);
int ti_sci_device_put(uint32_t id);
+int ti_sci_device_put_no_wait(uint32_t id);
int ti_sci_device_is_valid(uint32_t id);
int ti_sci_device_get_clcnt(uint32_t id, uint32_t *count);
int ti_sci_device_is_idle(uint32_t id, bool *r_state);
@@ -72,12 +67,6 @@
/**
* Clock control operations
*
- * - ti_sci_clock_set_state - Set clock state helper
- * @flags: Header flags as needed
- * @state: State to request for the clock.
- * - ti_sci_clock_get_state - Get clock state helper
- * @programmed_state: State requested for clock to move to
- * @current_state: State that the clock is currently in
* - ti_sci_clock_get - Get control of a clock from TI SCI
* @needs_ssc: 'true' iff Spread Spectrum clock is desired
* @can_change_freq: 'true' iff frequency change is desired
@@ -123,10 +112,6 @@
* usage count by balancing get_clock with put_clock. No refcounting is
* managed by driver for that purpose.
*/
-int ti_sci_clock_set_state(uint32_t dev_id, uint8_t clk_id,
- uint32_t flags, uint8_t state);
-int ti_sci_clock_get_state(uint32_t dev_id, uint8_t clk_id,
- uint8_t *programmed_state, uint8_t *current_state);
int ti_sci_clock_get(uint32_t dev_id, uint8_t clk_id,
bool needs_ssc, bool can_change_freq,
bool enable_input_term);
@@ -175,11 +160,13 @@
* - ti_sci_proc_set_boot_ctrl - Command to set the processor boot control flags
* @control_flags_set: Control flags to be set
* @control_flags_clear: Control flags to be cleared
+ * - ti_sci_proc_set_boot_ctrl_no_wait - Same as above without waiting for response
* - ti_sci_proc_auth_boot_image - Command to authenticate and load the image
* and then set the processor configuration flags.
* @cert_addr: Memory address at which payload image certificate is located.
* - ti_sci_proc_get_boot_status - Command to get the processor boot status
* - ti_sci_proc_wait_boot_status - Command to wait for a processor boot status
+ * - ti_sci_proc_wait_boot_status_no_wait - Same as above without waiting for response
*
* NOTE: for all these functions, the following are generic in nature:
* @proc_id: Processor ID
@@ -193,6 +180,9 @@
uint32_t config_flags_clear);
int ti_sci_proc_set_boot_ctrl(uint8_t proc_id, uint32_t control_flags_set,
uint32_t control_flags_clear);
+int ti_sci_proc_set_boot_ctrl_no_wait(uint8_t proc_id,
+ uint32_t control_flags_set,
+ uint32_t control_flags_clear);
int ti_sci_proc_auth_boot_image(uint8_t proc_id, uint64_t cert_addr);
int ti_sci_proc_get_boot_status(uint8_t proc_id, uint64_t *bv,
uint32_t *cfg_flags,
@@ -206,7 +196,15 @@
uint32_t status_flags_1_set_any_wait,
uint32_t status_flags_1_clr_all_wait,
uint32_t status_flags_1_clr_any_wait);
-int ti_sci_proc_shutdown(uint8_t proc_id, uint32_t dev_id);
+int ti_sci_proc_wait_boot_status_no_wait(uint8_t proc_id,
+ uint8_t num_wait_iterations,
+ uint8_t num_match_iterations,
+ uint8_t delay_per_iteration_us,
+ uint8_t delay_before_iterations_us,
+ uint32_t status_flags_1_set_all_wait,
+ uint32_t status_flags_1_set_any_wait,
+ uint32_t status_flags_1_clr_all_wait,
+ uint32_t status_flags_1_clr_any_wait);
/**
* ti_sci_init() - Basic initialization
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index 235e639..f66f12a 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -13,6 +13,7 @@
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
+#include <ti_sci_protocol.h>
#include <k3_gicv3.h>
#include <ti_sci.h>
@@ -70,12 +71,6 @@
return PSCI_E_INTERN_FAIL;
}
- ret = ti_sci_proc_release(proc);
- if (ret) {
- /* this is not fatal */
- WARN("Could not release processor control: %d\n", ret);
- }
-
return PSCI_E_SUCCESS;
}
@@ -90,9 +85,24 @@
proc = PLAT_PROC_START_ID + core_id;
device = PLAT_PROC_DEVICE_START_ID + core_id;
- ret = ti_sci_proc_shutdown(proc, device);
+ /* Start by sending wait for WFI command */
+ ret = ti_sci_proc_wait_boot_status_no_wait(proc,
+ /*
+ * Wait maximum time to give us the best chance to get
+ * to WFI before this command timeouts
+ */
+ UINT8_MAX, 100, UINT8_MAX, UINT8_MAX,
+ /* Wait for WFI */
+ PROC_BOOT_STATUS_FLAG_ARMV8_WFI, 0, 0, 0);
+ if (ret) {
+ ERROR("Sending wait for WFI failed (%d)\n", ret);
+ return;
+ }
+
+ /* Now queue up the core shutdown request */
+ ret = ti_sci_device_put_no_wait(device);
if (ret) {
- ERROR("Request to stop core failed: %d\n", ret);
+ ERROR("Sending core shutdown message failed (%d)\n", ret);
return;
}
}
diff --git a/services/spd/tlkd/tlkd.mk b/services/spd/tlkd/tlkd.mk
index 3010035..56de0a6 100644
--- a/services/spd/tlkd/tlkd.mk
+++ b/services/spd/tlkd/tlkd.mk
@@ -4,7 +4,9 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+ifeq (${ERROR_DEPRECATED},0)
SPD_INCLUDES := -Iinclude/bl32/payloads
+endif
SPD_SOURCES := services/spd/tlkd/tlkd_common.c \
services/spd/tlkd/tlkd_helpers.S \
diff --git a/services/spd/tlkd/tlkd_main.c b/services/spd/tlkd/tlkd_main.c
index f6f2af5..3cfc52d 100644
--- a/services/spd/tlkd/tlkd_main.c
+++ b/services/spd/tlkd/tlkd_main.c
@@ -13,12 +13,13 @@
* handle the request locally or delegate it to the Secure Payload. It is also
* responsible for initialising and maintaining communication with the SP.
******************************************************************************/
-#include <arch_helpers.h>
#include <assert.h>
#include <errno.h>
#include <stddef.h>
+#include <arch_helpers.h>
#include <bl31/bl31.h>
+#include <bl32/payloads/tlk.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
@@ -26,7 +27,6 @@
#include <plat/common/platform.h>
#include <tools_share/uuid.h>
-#include <tlk.h>
#include "tlkd_private.h"
extern const spd_pm_ops_t tlkd_pm_ops;
diff --git a/services/spd/tlkd/tlkd_pm.c b/services/spd/tlkd/tlkd_pm.c
index de34bf6..7d1959b 100644
--- a/services/spd/tlkd/tlkd_pm.c
+++ b/services/spd/tlkd/tlkd_pm.c
@@ -7,11 +7,11 @@
#include <assert.h>
#include <arch_helpers.h>
+#include <bl32/payloads/tlk.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/psci/psci.h>
-#include <tlk.h>
#include "tlkd_private.h"
diff --git a/services/spd/tspd/tspd.mk b/services/spd/tspd/tspd.mk
index 1457360..bda8338 100644
--- a/services/spd/tspd/tspd.mk
+++ b/services/spd/tspd/tspd.mk
@@ -5,7 +5,10 @@
#
TSPD_DIR := services/spd/tspd
+
+ifeq (${ERROR_DEPRECATED},0)
SPD_INCLUDES := -Iinclude/bl32/tsp
+endif
SPD_SOURCES := services/spd/tspd/tspd_common.c \
services/spd/tspd/tspd_helpers.S \