feat(mt8196): add APU power on/off functions
1. Add APU power on/off functions
2. Refine the APU power on/off interface for mt8188
3. Add dcm setup function to support mt8196
Change-Id: Ie1caca40f89de71caac037fabe7e7455ff2a1872
diff --git a/plat/mediatek/drivers/apusys/apusys.c b/plat/mediatek/drivers/apusys/apusys.c
index ee4fe5a..5eccb3c 100644
--- a/plat/mediatek/drivers/apusys/apusys.c
+++ b/plat/mediatek/drivers/apusys/apusys.c
@@ -30,10 +30,10 @@
switch (request_ops) {
case MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON:
- ret = apusys_kernel_apusys_pwr_top_on();
+ ret = apusys_kernel_apusys_rv_pwr_ctrl(APU_PWR_ON);
break;
case MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF:
- ret = apusys_kernel_apusys_pwr_top_off();
+ ret = apusys_kernel_apusys_rv_pwr_ctrl(APU_PWR_OFF);
break;
case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_REVISER:
ret = apusys_kernel_apusys_rv_setup_reviser();
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
index f8059ba..4dbf950 100644
--- a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
@@ -99,6 +99,8 @@
(PREDEFINE_CACHE << PREDEF_2G_OFS) | (PREDEFINE_CACHE << PREDEF_3G_OFS) |
(PREDEFINE_CACHE << PREDEF_4G_OFS));
+ apusys_infra_dcm_setup();
+
spin_unlock(&apusys_rv_lock);
return 0;
}
@@ -206,3 +208,8 @@
spin_unlock(&apusys_rv_lock);
return 0;
}
+
+int apusys_kernel_apusys_rv_pwr_ctrl(enum APU_PWR_OP op)
+{
+ return apusys_rv_pwr_ctrl(op);
+}
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
index b57fc4d..3700783 100644
--- a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
@@ -88,7 +88,13 @@
#define WDT_INT_W1C (1)
#define WDT_EN BIT(31)
+enum APU_PWR_OP {
+ APU_PWR_OFF = 0,
+ APU_PWR_ON = 1,
+};
+
void apusys_rv_mbox_mpu_init(void);
+int apusys_infra_dcm_setup(void);
int apusys_kernel_apusys_rv_setup_reviser(void);
int apusys_kernel_apusys_rv_reset_mp(void);
int apusys_kernel_apusys_rv_setup_boot(void);
@@ -100,5 +106,6 @@
int apusys_kernel_apusys_rv_cg_gating(void);
int apusys_kernel_apusys_rv_cg_ungating(void);
int apusys_kernel_apusys_rv_setup_apummu(void);
+int apusys_kernel_apusys_rv_pwr_ctrl(enum APU_PWR_OP op);
#endif /* APUSYS_RV_H */
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
index 0a2781b..746c81f 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_power.c
@@ -1,9 +1,10 @@
/*
- * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2023-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <errno.h>
#include <inttypes.h>
/* TF-A system header */
@@ -18,6 +19,7 @@
#include "apusys.h"
#include "apusys_power.h"
#include "apusys_rv.h"
+#include "apusys_rv_pwr_ctrl.h"
#include <mtk_mmap_pool.h>
static spinlock_t apu_lock;
@@ -118,7 +120,7 @@
mmio_write_32(APU_MBOX0_BASE + PWR_FLOW_SYNC_REG, (cfg & 0x1));
}
-int apusys_kernel_apusys_pwr_top_on(void)
+static int apusys_kernel_apusys_pwr_top_on(void)
{
int ret;
@@ -184,7 +186,7 @@
udelay(100);
}
-int apusys_kernel_apusys_pwr_top_off(void)
+static int apusys_kernel_apusys_pwr_top_off(void)
{
int ret;
@@ -221,6 +223,19 @@
return ret;
}
+int apusys_rv_pwr_ctrl(enum APU_PWR_OP op)
+{
+ if (op != APU_PWR_OFF && op != APU_PWR_ON) {
+ ERROR(MODULE_TAG "%s unknown request_ops = %d\n", __func__, op);
+ return -EINVAL;
+ }
+
+ if (op == APU_PWR_ON)
+ return apusys_kernel_apusys_pwr_top_on();
+
+ return apusys_kernel_apusys_pwr_top_off();
+}
+
static void get_pll_pcw(const uint32_t clk_rate, uint32_t *r1, uint32_t *r2)
{
unsigned int fvco = clk_rate;
@@ -481,3 +496,10 @@
return ret;
}
+
+int apusys_infra_dcm_setup(void)
+{
+ WARN(MODULE_TAG "%s not support\n", __func__);
+
+ return -EOPNOTSUPP;
+}
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_power.h b/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
index 460cc50..e1ce4a4 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_power.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2023-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -242,7 +242,5 @@
#define CG_CLR (0xffffffff)
int apusys_power_init(void);
-int apusys_kernel_apusys_pwr_top_on(void);
-int apusys_kernel_apusys_pwr_top_off(void);
#endif /* APUSYS_POWER_H */
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_rv_pwr_ctrl.h b/plat/mediatek/drivers/apusys/mt8188/apusys_rv_pwr_ctrl.h
index b1d43ff..329eadf 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_rv_pwr_ctrl.h
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_rv_pwr_ctrl.h
@@ -7,6 +7,8 @@
#ifndef APUSYS_RV_PWR_CTL_H
#define APUSYS_RV_PWR_CTL_H
+#include "apusys_rv.h"
+
/* APU MBOX */
#define MBOX_FUNC_CFG (0xb0)
#define MBOX_DOMAIN_CFG (0xe0)
@@ -26,6 +28,6 @@
#define HW_SEM_TIMEOUT (0)
-int apusys_rv_pwr_ctrl(uint32_t op);
+int apusys_rv_pwr_ctrl(enum APU_PWR_OP op);
#endif /* APUSYS_RV_PWR_CTL_H */
diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c
new file mode 100644
index 0000000..632af52
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2024, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include "apusys_power.h"
+#include "apusys_rv.h"
+#include "apusys_rv_pwr_ctrl.h"
+
+#define RPC_POWER_OFF_TIMEOUT_CNT (100000) /* 100ms */
+
+static int wait_for_state_ready(uint32_t reg, uint32_t mask, uint32_t expect,
+ uint32_t retry_times, uint32_t set_reg, uint32_t set_val)
+{
+ uint32_t count = 0;
+
+ while ((mmio_read_32(reg) & mask) != expect) {
+ if (count > retry_times) {
+ ERROR("%s: timed out, reg = %x, mask = %x, expect = %x\n",
+ __func__, reg, mask, expect);
+ return -EBUSY;
+ }
+ count += 1;
+
+ if (set_reg)
+ mmio_write_32(set_reg, set_val);
+ udelay(1);
+ }
+
+ return 0;
+}
+
+int apu_hw_sema_ctl_per_mbox(uint32_t sem_ctrl_addr, uint32_t sem_sta_addr,
+ uint8_t usr_bit, enum apu_hw_sem_op ctl, uint32_t timeout,
+ uint8_t bypass)
+{
+ int ret;
+ uint8_t ctl_bit = 0;
+
+ if (ctl == HW_SEM_GET)
+ ctl_bit = 0x1;
+ else if (ctl == HW_SEM_PUT)
+ ctl_bit = 0x2;
+ else
+ return -EINVAL;
+
+ /* return fail if semaphore is currently not held by this user */
+ if (ctl == HW_SEM_PUT && ((mmio_read_32(sem_sta_addr) & BIT(usr_bit)) == 0)
+ && !bypass) {
+ ERROR("%s release error: usr_bit:%d ctl:%d (sem_addr(0x%08x) = 0x%08x)\n",
+ __func__, usr_bit, ctl, sem_sta_addr, mmio_read_32(sem_sta_addr));
+ return -EINVAL;
+ }
+
+ mmio_write_32(sem_ctrl_addr, ctl_bit);
+
+ if (ctl == HW_SEM_PUT)
+ return 0;
+
+ ret = wait_for_state_ready(sem_sta_addr, BIT(usr_bit), BIT(usr_bit), timeout,
+ sem_ctrl_addr, ctl_bit);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int apusys_rv_pwr_ctrl(enum APU_PWR_OP op)
+{
+ int ret;
+ uint32_t global_ref_cnt;
+
+ ret = apu_hw_sema_ctl_per_mbox(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA0_CTRL,
+ APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA0_STA,
+ APU_HW_SEM_SYS_APMCU, HW_SEM_GET, HW_SEM_TIMEOUT, 0);
+
+ if (ret) {
+ ERROR("%s(%d): sem acquire timeout\n", __func__, op);
+ return ret;
+ }
+
+ global_ref_cnt = mmio_read_32(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_DUMMY);
+
+ if (global_ref_cnt > 2) {
+ ERROR("%s: global_ref_cnt(%d) > 2\n", __func__, global_ref_cnt);
+ } else if (op == APU_PWR_OFF) {
+ global_ref_cnt--;
+ mmio_write_32(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_DUMMY, global_ref_cnt);
+ if (global_ref_cnt == 0)
+ mmio_write_32(APU_MBOX_WKUP_CFG(11), 0);
+ } else if (op == APU_PWR_ON) {
+ global_ref_cnt++;
+ mmio_write_32(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_DUMMY, global_ref_cnt);
+ if (global_ref_cnt == 1)
+ mmio_write_32(APU_MBOX_WKUP_CFG(11), 1);
+ }
+
+ ret = apu_hw_sema_ctl_per_mbox(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA0_CTRL,
+ APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA0_STA,
+ APU_HW_SEM_SYS_APMCU, HW_SEM_PUT, HW_SEM_TIMEOUT, 0);
+
+ if (ret)
+ ERROR("%s(%d): sem release timeout\n", __func__, op);
+
+ return ret;
+}
+
+int rv_iommu_hw_sem_trylock(void)
+{
+ return apu_hw_sema_ctl_per_mbox(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_CTRL,
+ APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_STA,
+ APU_HW_SEM_SYS_APMCU, HW_SEM_GET, 0, 0);
+}
+
+int rv_iommu_hw_sem_unlock(void)
+{
+ return apu_hw_sema_ctl_per_mbox(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_CTRL,
+ APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_STA,
+ APU_HW_SEM_SYS_APMCU, HW_SEM_PUT, 0, 0);
+}
+
+int apu_hw_sema_ctl(uint32_t sem_addr, uint8_t usr_bit, uint8_t ctl, uint32_t timeout,
+ uint8_t bypass)
+{
+ int ret;
+ uint8_t ctl_bit = 0;
+
+ if (ctl == HW_SEM_GET)
+ ctl_bit = usr_bit;
+ else if (ctl == HW_SEM_PUT)
+ ctl_bit = usr_bit + HW_SEM_PUT_BIT_SHIFT;
+ else
+ return -EINVAL;
+
+ if (ctl == HW_SEM_PUT && ((mmio_read_32(sem_addr) & BIT(ctl_bit)) == 0) && !bypass) {
+ ERROR("%s release error: usr_bit:%d ctl:%d (sem_addr(0x%08x) = 0x%08x)\n",
+ __func__, usr_bit, ctl, sem_addr, mmio_read_32(sem_addr));
+ return -EINVAL;
+ }
+
+ mmio_write_32(sem_addr, BIT(ctl_bit));
+
+ if (ctl == HW_SEM_PUT)
+ goto end;
+
+ ret = wait_for_state_ready(sem_addr, BIT(ctl_bit), BIT(ctl_bit), timeout,
+ sem_addr, BIT(ctl_bit));
+ if (ret)
+ return ret;
+
+end:
+ VERBOSE("%s: sem_addr = 0x%x, usr_bit: %d, ctl: %d, sem_addr = 0x%08x\n",
+ __func__, sem_addr, usr_bit, ctl, mmio_read_32(sem_addr));
+
+ return 0;
+}
+
+int apusys_infra_dcm_setup(void)
+{
+ mmio_write_32(APU_REG_AO_GLUE_CONFG,
+ mmio_read_32(APU_REG_AO_GLUE_CONFG) | BIT(24) | BIT(26));
+
+ return 0;
+}
diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h
index 12a1459..b5a48e2 100644
--- a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h
@@ -9,6 +9,8 @@
#include <platform_def.h>
+#include "apusys_rv.h"
+
#define SUPPORT_APU_CLEAR_MBOX_DUMMY (1)
enum apu_hw_sem_sys_id {
@@ -18,7 +20,7 @@
APU_HW_SEM_SYS_APMCU = 11UL, /* mbox11 */
};
-int apusys_rv_pwr_ctrl(uint32_t op);
+int apusys_rv_pwr_ctrl(enum APU_PWR_OP op);
int rv_iommu_hw_sem_unlock(void);
int rv_iommu_hw_sem_trylock(void);
int apu_hw_sema_ctl(uint32_t sem_addr, uint8_t usr_bit, uint8_t ctl, uint32_t timeout,
@@ -57,6 +59,12 @@
#define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG)
#define APU_MBOX_WKUP_CFG(i) (APU_MBOX(i) + MBOX_WKUP_CFG)
+enum apu_hw_sem_op {
+ HW_SEM_PUT = 0,
+ HW_SEM_GET = 1,
+};
+
+#define HW_SEM_PUT_BIT_SHIFT (16)
/* bypass mbox register Dump for secure master */
#define APU_MBOX_DBG_EN (0x190f2380)
@@ -75,7 +83,11 @@
#define APU_INFRA_DISABLE (APU_INFRA_BASE + 0xC18)
#define APU_INFRA_ENABLE (APU_INFRA_BASE + 0xC14)
#define APU_INFRA_STATUS (APU_INFRA_BASE + 0xC10)
+#define APU_INFRA_STATUS_MASK (0x1fffe)
#define APU_INFRA_HW_SEM (APUSYS_CE_BASE + 0xE00)
#define APU_RPC_STATUS (0x190f0044)
+#define APU_INFRA_BIT_OFF (16)
+#define APU_RPC_STATUS_BIT BIT(0)
+
#endif /* APUSYS_RV_PWR_CTL_H */
diff --git a/plat/mediatek/drivers/apusys/mt8196/rules.mk b/plat/mediatek/drivers/apusys/mt8196/rules.mk
index 348051a..4ffaf73 100644
--- a/plat/mediatek/drivers/apusys/mt8196/rules.mk
+++ b/plat/mediatek/drivers/apusys/mt8196/rules.mk
@@ -16,6 +16,7 @@
LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_ammu.c
LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_devapc.c
LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_power.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_rv_pwr_ctrl.c
LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_security_ctrl_plat.c
LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_security_ctrl_perm_plat.c