Tegra186: delete 'Video Memory Carveout' handling
This patch removes duplicate code from the platform's SiP handler
routine for processing Video Memory Carveout region requests and
uses the common SiP handler instead.
Change-Id: Ib307de017fd88d5ed3c816288327cae750a67806
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
index 9f48ddd..8e33718 100644
--- a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
@@ -114,32 +114,6 @@
return 0;
- case TEGRA_SIP_NEW_VIDEOMEM_REGION:
- /* clean up the high bits */
- x1 = (uint32_t)x1;
- x2 = (uint32_t)x2;
-
- /*
- * Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
- * or falls outside of the valid DRAM range
- */
- mce_ret = bl31_check_ns_address(x1, x2);
- if (mce_ret)
- return -ENOTSUP;
-
- /*
- * Check if Video Memory is aligned to 1MB.
- */
- if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
- ERROR("Unaligned Video Memory base address!\n");
- return -ENOTSUP;
- }
-
- /* new video memory carveout settings */
- tegra_memctrl_videomem_setup(x1, x2);
-
- return 0;
-
case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE:
/* clean up the high bits */