FVP: make usage of Trusted DRAM optional at build time
This patch groups the current contents of the Trusted DRAM region at
address 0x00_0600_0000 (entrypoint mailboxes and BL3-1 parameters) in
a single shared memory area that may be allocated to Trusted SRAM
(default) or Trusted DRAM at build time by setting the
FVP_SHARED_DATA_LOCATION make variable. The size of this shared
memory is 4096 bytes.
The combination 'Shared data in Trusted SRAM + TSP in Trusted DRAM'
is not currently supported due to restrictions in the maximum number
of mmu tables that can be created.
Documentation has been updated to reflect these changes.
Fixes ARM-software/tf-issues#100
Change-Id: I26ff04d33ce4cacf8d770d1a1e24132b4fc53ff0
diff --git a/plat/fvp/aarch64/fvp_helpers.S b/plat/fvp/aarch64/fvp_helpers.S
index 4eecd4c..922329c 100644
--- a/plat/fvp/aarch64/fvp_helpers.S
+++ b/plat/fvp/aarch64/fvp_helpers.S
@@ -140,7 +140,7 @@
* its safe to read it here with SO attributes
* ---------------------------------------------
*/
- ldr x10, =FVP_TRUSTED_DRAM_BASE + MBOX_OFF
+ ldr x10, =MBOX_BASE
bl platform_get_core_pos
lsl x0, x0, #CACHE_WRITEBACK_SHIFT
ldr x0, [x10, x0]
@@ -153,8 +153,8 @@
/* -----------------------------------------------------
* void platform_mem_init (void);
*
- * Zero out the mailbox registers in the TZDRAM. The
- * mmu is turned off right now and only the primary can
+ * Zero out the mailbox registers in the shared memory.
+ * The mmu is turned off right now and only the primary can
* ever execute this code. Secondaries will read the
* mailboxes using SO accesses. In short, BL31 will
* update the mailboxes after mapping the tzdram as
@@ -163,7 +163,7 @@
* -----------------------------------------------------
*/
func platform_mem_init
- ldr x0, =FVP_TRUSTED_DRAM_BASE + MBOX_OFF
+ ldr x0, =MBOX_BASE
mov w1, #PLATFORM_CORE_COUNT
loop:
str xzr, [x0], #CACHE_WRITEBACK_GRANULE