Merge "Revert workaround for A77 erratum 1800714" into integration
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 5f3d699..c0fda78 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -254,9 +254,6 @@
- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
-- ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
- CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
-
- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index ed84c0f..0a42a5d 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -17,7 +17,6 @@
******************************************************************************/
#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
-#define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
/*******************************************************************************
* CPU Power Control register specific definitions.
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index 04a610e..e3a6f5f 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -86,35 +86,6 @@
endfunc check_errata_1508412_0
/* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1800714.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1800714_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1800714
- cbz x0, 1f
-
- /* Disable allocation of splintered pages in the L2 TLB */
- mrs x1, CORTEX_A77_CPUECTLR_EL1
- orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
- msr CORTEX_A77_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1800714_wa
-
-func check_errata_1800714
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1800714
-
- /* --------------------------------------------------
* Errata Workaround for Cortex A77 Errata #1925769.
* This applies to revision <= r1p1 of Cortex A77.
* Inputs:
@@ -158,11 +129,6 @@
bl errata_a77_1508412_wa
#endif
-#if ERRATA_A77_1800714
- mov x0, x18
- bl errata_a77_1800714_wa
-#endif
-
#if ERRATA_A77_1925769
mov x0, x18
bl errata_a77_1925769_wa
@@ -202,7 +168,6 @@
* checking functions of each errata.
*/
report_errata ERRATA_A77_1508412, cortex_a77, 1508412
- report_errata ERRATA_A77_1800714, cortex_a77, 1800714
report_errata ERRATA_A77_1925769, cortex_a77, 1925769
ldp x8, x30, [sp], #16
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 7575051..4126105 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -282,10 +282,6 @@
# only to revision <= r1p0 of the Cortex A77 cpu.
ERRATA_A77_1508412 ?=0
-# Flag to apply erratum 1800714 workaround during reset. This erratum applies
-# only to revision <= r1p1 of the Cortex A77 cpu.
-ERRATA_A77_1800714 ?=0
-
# Flag to apply erratum 1925769 workaround during reset. This erratum applies
# only to revision <= r1p1 of the Cortex A77 cpu.
ERRATA_A77_1925769 ?=0
@@ -563,10 +559,6 @@
$(eval $(call assert_boolean,ERRATA_A77_1508412))
$(eval $(call add_define,ERRATA_A77_1508412))
-# Process ERRATA_A77_1800714 flag
-$(eval $(call assert_boolean,ERRATA_A77_1800714))
-$(eval $(call add_define,ERRATA_A77_1800714))
-
# Process ERRATA_A77_1925769 flag
$(eval $(call assert_boolean,ERRATA_A77_1925769))
$(eval $(call add_define,ERRATA_A77_1925769))