diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md
index 5d34409..94d05d5 100644
--- a/docs/cpu-specific-build-macros.md
+++ b/docs/cpu-specific-build-macros.md
@@ -66,6 +66,9 @@
 *   `ERRATA_A57_828024`: This applies errata 828024 workaround to Cortex-A57
      CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
 
+*   `ERRATA_A57_829520`: This applies errata 829520 workaround to Cortex-A57
+     CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
+
 3.  CPU Specific optimizations
 ------------------------------
 
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index 68d0821..95c1f56 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -67,6 +67,7 @@
 #define CPUACTLR_DCC_AS_DCCI		(1 << 44)
 #define CPUACTLR_DIS_STREAMING		(3 << 27)
 #define CPUACTLR_DIS_L1_STREAMING	(3 << 25)
+#define CPUACTLR_DIS_INDIRECT_PREDICTOR	(1 << 4)
 
 /*******************************************************************************
  * L2 Control register specific definitions.
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index ec32ce7..25def1c 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -225,6 +225,32 @@
 	ret
 endfunc errata_a57_828024_wa
 
+	/* ---------------------------------------------------
+	 * Errata Workaround for Cortex A57 Errata #829520.
+	 * This applies only to revision <= r1p2 of Cortex A57.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Clobbers : x0 - x5
+	 * ---------------------------------------------------
+	 */
+func errata_a57_829520_wa
+	/*
+	 * Compare x0 against revision r1p2
+	 */
+	cmp	x0, #0x12
+	b.ls	apply_829520
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+	b	print_revision_warning
+#else
+	ret
+#endif
+apply_829520:
+	mrs	x1, CPUACTLR_EL1
+	orr	x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR
+	msr	CPUACTLR_EL1, x1
+	ret
+endfunc errata_a57_829520_wa
+
 	/* -------------------------------------------------
 	 * The CPU Ops reset function for Cortex-A57.
 	 * Clobbers: x0-x5, x15, x19, x30
@@ -267,6 +293,12 @@
 	mov	x0, x15
 	bl	errata_a57_828024_wa
 #endif
+
+#if ERRATA_A57_829520
+	mov	x0, x15
+	bl	errata_a57_829520_wa
+#endif
+
 	/* ---------------------------------------------
 	 * Enable the SMP bit.
 	 * ---------------------------------------------
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 7d9f2b7..62de70f 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -82,6 +82,10 @@
 # only to revision <= r1p1 of the Cortex A57 cpu.
 ERRATA_A57_828024	?=0
 
+# Flag to apply erratum 829520 workaround during reset. This erratum applies
+# only to revision <= r1p2 of the Cortex A57 cpu.
+ERRATA_A57_829520	?=0
+
 # Process ERRATA_A53_826319 flag
 $(eval $(call assert_boolean,ERRATA_A53_826319))
 $(eval $(call add_define,ERRATA_A53_826319))
@@ -105,3 +109,7 @@
 # Process ERRATA_A57_828024 flag
 $(eval $(call assert_boolean,ERRATA_A57_828024))
 $(eval $(call add_define,ERRATA_A57_828024))
+
+# Process ERRATA_A57_829520 flag
+$(eval $(call assert_boolean,ERRATA_A57_829520))
+$(eval $(call add_define,ERRATA_A57_829520))