Merge "fix(spm-mm): carve out NS buffer TZC400 region" into integration
diff --git a/changelog.yaml b/changelog.yaml
index 6f2458e..7d8760e 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -241,6 +241,9 @@
- title: RD-N2
scope: rdn2
+ - title: RD-Fremont
+ scope: rdfremont
+
deprecated:
- board/rdn2
diff --git a/docs/plat/arm/fvp/fvp-support.rst b/docs/plat/arm/fvp/fvp-support.rst
index cc1b500..c805c78 100644
--- a/docs/plat/arm/fvp/fvp-support.rst
+++ b/docs/plat/arm/fvp/fvp-support.rst
@@ -15,7 +15,7 @@
- ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21)
- ``FVP_Base_AEMvA``
- ``FVP_Base_AEMvA-AEMvA``
-- ``FVP_Base_Cortex-A32x4`` (Version 11.12/38)
+- ``FVP_Base_Cortex-A32x4``
- ``FVP_Base_Cortex-A35x4``
- ``FVP_Base_Cortex-A53x4``
- ``FVP_Base_Cortex-A55``
diff --git a/docs/resources/diagrams/secure_sw_stack_sp.png b/docs/resources/diagrams/secure_sw_stack_sp.png
index 5cb2ca7..dc18cb4 100644
--- a/docs/resources/diagrams/secure_sw_stack_sp.png
+++ b/docs/resources/diagrams/secure_sw_stack_sp.png
Binary files differ
diff --git a/docs/resources/diagrams/secure_sw_stack_tos.png b/docs/resources/diagrams/secure_sw_stack_tos.png
index 1f2d555..2b42019 100644
--- a/docs/resources/diagrams/secure_sw_stack_tos.png
+++ b/docs/resources/diagrams/secure_sw_stack_tos.png
Binary files differ
diff --git a/drivers/arm/rse/rse_comms.mk b/drivers/arm/rse/rse_comms.mk
index a1abc6a..3b87fe2 100644
--- a/drivers/arm/rse/rse_comms.mk
+++ b/drivers/arm/rse/rse_comms.mk
@@ -31,4 +31,5 @@
endif
PLAT_INCLUDES += -Idrivers/arm/rse \
- -Idrivers/arm/mhu
+ -Idrivers/arm/mhu \
+ -Iinclude/lib/psa
diff --git a/drivers/st/clk/clk-stm32-core.c b/drivers/st/clk/clk-stm32-core.c
index 9fe8c8c..6787d50 100644
--- a/drivers/st/clk/clk-stm32-core.c
+++ b/drivers/st/clk/clk-stm32-core.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -28,7 +28,7 @@
return stm32_clock_data;
}
-static void stm32mp1_clk_lock(struct spinlock *lock)
+static void _clk_lock(struct spinlock *lock)
{
if (stm32mp_lock_available()) {
/* Assume interrupts are masked */
@@ -36,21 +36,21 @@
}
}
-static void stm32mp1_clk_unlock(struct spinlock *lock)
+static void _clk_unlock(struct spinlock *lock)
{
if (stm32mp_lock_available()) {
spin_unlock(lock);
}
}
-void stm32mp1_clk_rcc_regs_lock(void)
+void clk_stm32_rcc_regs_lock(void)
{
- stm32mp1_clk_lock(®_lock);
+ _clk_lock(®_lock);
}
-void stm32mp1_clk_rcc_regs_unlock(void)
+void clk_stm32_rcc_regs_unlock(void)
{
- stm32mp1_clk_unlock(®_lock);
+ _clk_unlock(®_lock);
}
#define TIMEOUT_US_1S U(1000000)
@@ -224,6 +224,15 @@
return NULL;
}
+static const struct stm32_clk_ops *_clk_get_ops(struct stm32_clk_priv *priv, int id)
+{
+ const struct clk_stm32 *clk = _clk_get(priv, id);
+
+ assert(clk->ops != NO_OPS);
+
+ return priv->ops_array[clk->ops];
+}
+
#define clk_div_mask(_width) GENMASK(((_width) - 1U), 0U)
static unsigned int _get_table_div(const struct clk_div_table *table,
@@ -377,7 +386,7 @@
int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int clk_id)
{
- const struct clk_stm32 *clk = _clk_get(priv, clk_id);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, clk_id);
const struct parent_cfg *parent;
uint16_t mux_id;
int sel;
@@ -394,8 +403,8 @@
mux_id &= MUX_PARENT_MASK;
parent = &priv->parents[mux_id];
- if (clk->ops->get_parent != NULL) {
- sel = clk->ops->get_parent(priv, clk_id);
+ if (ops->get_parent != NULL) {
+ sel = ops->get_parent(priv, clk_id);
} else {
sel = clk_mux_get_parent(priv, mux_id);
}
@@ -464,7 +473,7 @@
unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id)
{
- const struct clk_stm32 *clk = _clk_get(priv, id);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
int parent;
if ((unsigned int)id >= priv->num) {
@@ -476,14 +485,14 @@
return 0UL;
}
- if (clk->ops->recalc_rate != NULL) {
+ if (ops->recalc_rate != NULL) {
unsigned long prate = 0UL;
if (parent != CLK_IS_ROOT) {
prate = _clk_stm32_get_rate(priv, parent);
}
- return clk->ops->recalc_rate(priv, id, prate);
+ return ops->recalc_rate(priv, id, prate);
}
if (parent == CLK_IS_ROOT) {
@@ -520,10 +529,10 @@
int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id)
{
- const struct clk_stm32 *clk = _clk_get(priv, id);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
- if (clk->ops->enable != NULL) {
- clk->ops->enable(priv, id);
+ if (ops->enable != NULL) {
+ ops->enable(priv, id);
}
return 0;
@@ -550,7 +559,7 @@
priv->gate_refcounts[id]++;
- if (priv->gate_refcounts[id] == UINT_MAX) {
+ if (priv->gate_refcounts[id] == UINT8_MAX) {
ERROR("%s: %d max enable count !", __func__, id);
panic();
}
@@ -562,19 +571,19 @@
{
int ret;
- stm32mp1_clk_lock(&refcount_lock);
+ _clk_lock(&refcount_lock);
ret = _clk_stm32_enable_core(priv, id);
- stm32mp1_clk_unlock(&refcount_lock);
+ _clk_unlock(&refcount_lock);
return ret;
}
void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id)
{
- const struct clk_stm32 *clk = _clk_get(priv, id);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
- if (clk->ops->disable != NULL) {
- clk->ops->disable(priv, id);
+ if (ops->disable != NULL) {
+ ops->disable(priv, id);
}
}
@@ -610,19 +619,19 @@
void _clk_stm32_disable(struct stm32_clk_priv *priv, int id)
{
- stm32mp1_clk_lock(&refcount_lock);
+ _clk_lock(&refcount_lock);
_clk_stm32_disable_core(priv, id);
- stm32mp1_clk_unlock(&refcount_lock);
+ _clk_unlock(&refcount_lock);
}
bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id)
{
- const struct clk_stm32 *clk = _clk_get(priv, id);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, id);
- if (clk->ops->is_enabled != NULL) {
- return clk->ops->is_enabled(priv, id);
+ if (ops->is_enabled != NULL) {
+ return ops->is_enabled(priv, id);
}
return priv->gate_refcounts[id];
@@ -957,6 +966,10 @@
{
struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
+ if (osc_data->frequency == 0UL) {
+ return 0;
+ }
+
_clk_stm32_gate_enable(priv, osc_data->gate_id);
if (_clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, true) != 0U) {
@@ -971,6 +984,10 @@
{
struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
+ if (osc_data->frequency == 0UL) {
+ return;
+ }
+
_clk_stm32_gate_disable(priv, osc_data->gate_id);
if (_clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, false) != 0U) {
@@ -1073,12 +1090,10 @@
priv->base = base;
for (i = 0U; i < priv->num; i++) {
- const struct clk_stm32 *clk = _clk_get(priv, i);
-
- assert(clk->ops != NULL);
+ const struct stm32_clk_ops *ops = _clk_get_ops(priv, i);
- if (clk->ops->init != NULL) {
- clk->ops->init(priv, i);
+ if (ops->init != NULL) {
+ ops->init(priv, i);
}
}
diff --git a/drivers/st/clk/clk-stm32-core.h b/drivers/st/clk/clk-stm32-core.h
index 8bfb513..bfb5f11 100644
--- a/drivers/st/clk/clk-stm32-core.h
+++ b/drivers/st/clk/clk-stm32-core.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -21,23 +21,23 @@
};
struct clk_div_table {
- unsigned int val;
- unsigned int div;
+ uint16_t val;
+ uint16_t div;
};
struct div_cfg {
+ const struct clk_div_table *table;
uint16_t offset;
uint8_t shift;
uint8_t width;
uint8_t flags;
uint8_t bitrdy;
- const struct clk_div_table *table;
};
struct parent_cfg {
- uint8_t num_parents;
const uint16_t *id_parents;
struct mux_cfg *mux;
+ uint8_t num_parents;
};
struct stm32_clk_priv;
@@ -56,9 +56,9 @@
struct clk_stm32 {
uint16_t binding;
uint16_t parent;
+ uint8_t ops;
uint8_t flags;
void *clock_cfg;
- const struct stm32_clk_ops *ops;
};
struct stm32_clk_priv {
@@ -73,8 +73,9 @@
const uint32_t nb_div;
struct clk_oscillator_data *osci_data;
const uint32_t nb_osci_data;
- uint32_t *gate_refcounts;
+ uint8_t *gate_refcounts;
void *pdata;
+ const struct stm32_clk_ops **ops_array;
};
struct stm32_clk_bypass {
@@ -97,18 +98,14 @@
struct clk_oscillator_data {
const char *name;
- uint16_t id_clk;
- unsigned long frequency;
- uint16_t gate_id;
- uint16_t gate_rdy_id;
struct stm32_clk_bypass *bypass;
struct stm32_clk_css *css;
struct stm32_clk_drive *drive;
-};
+ unsigned long frequency;
+ uint16_t id_clk;
+ uint16_t gate_id;
+ uint16_t gate_rdy_id;
-struct clk_fixed_rate {
- const char *name;
- unsigned long fixed_rate;
};
struct clk_gate_cfg {
@@ -144,6 +141,9 @@
#define MASK_WIDTH_SHIFT(_width, _shift) \
GENMASK(((_width) + (_shift) - 1U), (_shift))
+void clk_stm32_rcc_regs_lock(void);
+void clk_stm32_rcc_regs_unlock(void);
+
int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base);
void clk_stm32_enable_critical_clocks(void);
@@ -218,7 +218,7 @@
#endif
struct clk_stm32_div_cfg {
- int id;
+ uint8_t id;
};
#define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \
@@ -229,11 +229,11 @@
.clock_cfg = &(struct clk_stm32_div_cfg){\
.id = (_div_id),\
},\
- .ops = &clk_stm32_divider_ops,\
+ .ops = STM32_DIVIDER_OPS,\
}
struct clk_stm32_gate_cfg {
- int id;
+ uint8_t id;
};
#define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \
@@ -244,12 +244,12 @@
.clock_cfg = &(struct clk_stm32_gate_cfg){\
.id = (_gate_id),\
},\
- .ops = &clk_stm32_gate_ops,\
+ .ops = STM32_GATE_OPS,\
}
struct fixed_factor_cfg {
- unsigned int mult;
- unsigned int div;
+ uint8_t mult;
+ uint8_t div;
};
unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv,
@@ -263,7 +263,7 @@
.mult = (_mult),\
.div = (_div),\
},\
- .ops = &clk_fixed_factor_ops,\
+ .ops = FIXED_FACTOR_OPS,\
}
#define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \
@@ -275,7 +275,7 @@
.offset = (_offset),\
.bit_idx = (_bit_idx),\
},\
- .ops = &clk_gate_ops,\
+ .ops = GATE_OPS,\
}
#define STM32_MUX(idx, _binding, _mux_id, _flags) \
@@ -284,7 +284,7 @@
.parent = (MUX(_mux_id)),\
.flags = (_flags),\
.clock_cfg = NULL,\
- .ops = (&clk_mux_ops),\
+ .ops = STM32_MUX_OPS\
}
struct clk_timer_cfg {
@@ -301,7 +301,7 @@
.apbdiv = (_apbdiv),\
.timpre = (_timpre),\
},\
- .ops = &clk_timer_ops,\
+ .ops = STM32_TIMER_OPS,\
}
struct clk_stm32_fixed_rate_cfg {
@@ -315,7 +315,7 @@
.clock_cfg = &(struct clk_stm32_fixed_rate_cfg){\
.rate = (_rate),\
},\
- .ops = &clk_stm32_fixed_rate_ops,\
+ .ops = STM32_FIXED_RATE_OPS,\
}
#define BYPASS(_offset, _bit_byp, _bit_digbyp) &(struct stm32_clk_bypass){\
@@ -355,7 +355,7 @@
void clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id);
struct stm32_osc_cfg {
- int osc_id;
+ uint8_t osc_id;
};
#define CLK_OSC(idx, _idx, _parent, _osc_id) \
@@ -366,7 +366,7 @@
.clock_cfg = &(struct stm32_osc_cfg){\
.osc_id = (_osc_id),\
},\
- .ops = &clk_stm32_osc_ops,\
+ .ops = STM32_OSC_OPS,\
}
#define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \
@@ -377,7 +377,7 @@
.clock_cfg = &(struct stm32_osc_cfg){\
.osc_id = (_osc_id),\
},\
- .ops = &clk_stm32_osc_nogate_ops,\
+ .ops = STM32_OSC_NOGATE_OPS,\
}
extern const struct stm32_clk_ops clk_mux_ops;
@@ -390,4 +390,19 @@
extern const struct stm32_clk_ops clk_stm32_osc_ops;
extern const struct stm32_clk_ops clk_stm32_osc_nogate_ops;
+enum {
+ NO_OPS,
+ FIXED_FACTOR_OPS,
+ GATE_OPS,
+ STM32_MUX_OPS,
+ STM32_DIVIDER_OPS,
+ STM32_GATE_OPS,
+ STM32_TIMER_OPS,
+ STM32_FIXED_RATE_OPS,
+ STM32_OSC_OPS,
+ STM32_OSC_NOGATE_OPS,
+
+ STM32_LAST_OPS
+};
+
#endif /* CLK_STM32_CORE_H */
diff --git a/drivers/st/clk/clk-stm32mp13.c b/drivers/st/clk/clk-stm32mp13.c
index 01d1764..fd62049 100644
--- a/drivers/st/clk/clk-stm32mp13.c
+++ b/drivers/st/clk/clk-stm32mp13.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -186,65 +186,7 @@
_MCE,
_FMC_K,
_QSPI_K,
-#if defined(IMAGE_BL32)
- _LTDC,
- _DMA1,
- _DMA2,
- _MDMA,
- _ETH1MAC,
- _USBH,
- _TIM2,
- _TIM3,
- _TIM4,
- _TIM5,
- _TIM6,
- _TIM7,
- _LPTIM1_K,
- _SPI2_K,
- _SPI3_K,
- _SPDIF_K,
- _TIM1,
- _TIM8,
- _SPI1_K,
- _SAI1_K,
- _SAI2_K,
- _DFSDM,
- _FDCAN_K,
- _TIM13,
- _TIM14,
- _TIM16,
- _TIM17,
- _SPI4_K,
- _SPI5_K,
- _I2C1_K,
- _I2C2_K,
- _ADFSDM,
- _LPTIM2_K,
- _LPTIM3_K,
- _LPTIM4_K,
- _LPTIM5_K,
- _VREF,
- _DTS,
- _PMBCTRL,
- _HDP,
- _STGENRO,
- _DCMIPP_K,
- _DMAMUX1,
- _DMAMUX2,
- _DMA3,
- _ADC1_K,
- _ADC2_K,
- _TSC,
- _AXIMC,
- _ETH1CK,
- _ETH1TX,
- _ETH1RX,
- _CRC1,
- _ETH2CK,
- _ETH2TX,
- _ETH2RX,
- _ETH2MAC,
-#endif
+
CK_LAST
};
@@ -947,7 +889,7 @@
#endif
/* RCC clock device driver private */
-static unsigned int refcounts_mp13[CK_LAST];
+static uint8_t refcounts_mp13[CK_LAST];
static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx);
@@ -1007,6 +949,11 @@
return;
}
+ /* Do not reconfigure LSE if already enabled */
+ if (_clk_stm32_gate_is_enabled(priv, osc_data->gate_id)) {
+ return;
+ }
+
clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass);
clk_oscillator_set_drive(priv, _CK_LSE, drive);
@@ -1027,8 +974,8 @@
timeout = timeout_init_us(HSIDIV_TIMEOUT);
while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) {
if (timeout_elapsed(timeout)) {
- ERROR("HSIDIV failed @ 0x%lx: 0x%x\n",
- address, mmio_read_32(address));
+ EARLY_ERROR("HSIDIV failed @ 0x%lx: 0x%x\n",
+ address, mmio_read_32(address));
return -ETIMEDOUT;
}
}
@@ -1050,7 +997,7 @@
}
if (hsidiv == 4U) {
- ERROR("Invalid clk-hsi frequency\n");
+ EARLY_ERROR("Invalid clk-hsi frequency\n");
return -EINVAL;
}
@@ -1292,7 +1239,7 @@
uint32_t value = 0;
if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) {
- ERROR("Invalid Vref clock !\n");
+ EARLY_ERROR("Invalid Vref clock !\n");
panic();
}
@@ -1352,6 +1299,123 @@
return &pdata->pll[pll_idx];
}
+/* Define characteristic for PLL1 : PLL_2000 */
+#define POST_DIVM_MIN 8000000U
+#define POST_DIVM_MAX 16000000U
+#define DIVM_MIN 0U
+#define DIVM_MAX 63U
+#define DIVN_MIN 24U
+#define DIVN_MAX 99U
+#define DIVP_MIN 0U
+#define DIVP_MAX 127U
+#define FRAC_MAX 8192U
+#define VCO_MIN 992000000U
+#define VCO_MAX 2000000000U
+
+static int clk_compute_pll1_settings(uint32_t freq_khz)
+{
+ struct stm32_clk_priv *priv = clk_stm32_get_priv();
+ struct stm32_pll_dt_cfg *pll1 = clk_stm32_pll_get_pdata(_PLL1);
+ struct stm32_pll_dt_cfg *pll2 = clk_stm32_pll_get_pdata(_PLL2);
+ unsigned long long best_diff = ULLONG_MAX;
+ unsigned int divm;
+ unsigned long input_freq = 0UL;
+ uint32_t src = pll2->vco.src;
+
+ /* PLL1 share the same clock source than PLL2 */
+ switch (src) {
+ case CLK_PLL12_HSI:
+ input_freq = _clk_stm32_get_rate(priv, _CK_HSI);
+ break;
+ case CLK_PLL12_HSE:
+ input_freq = _clk_stm32_get_rate(priv, _CK_HSE);
+ break;
+ default:
+ break;
+ }
+
+ if (input_freq == 0UL) {
+ panic();
+ }
+
+ /* Following parameters have always the same value */
+ pll1->output.output[PLL_CFG_Q] = 0U;
+ pll1->output.output[PLL_CFG_R] = 0U;
+
+ for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) {
+ unsigned long post_divm = input_freq / divm;
+ unsigned int divp;
+
+ if ((post_divm < POST_DIVM_MIN) || (post_divm > POST_DIVM_MAX)) {
+ continue;
+ }
+
+ for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
+ unsigned long long output_freq = freq_khz * 1000ULL;
+ unsigned long long freq;
+ unsigned long long divn;
+ unsigned long long frac;
+ unsigned int i;
+
+ freq = output_freq * divm * (divp + 1U);
+
+ divn = (freq / input_freq) - 1U;
+ if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) {
+ continue;
+ }
+
+ frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX);
+
+ /* 2 loops to refine the fractional part */
+ for (i = 2U; i != 0U; i--) {
+ unsigned long long diff;
+ unsigned long long vco;
+
+ if (frac > FRAC_MAX) {
+ break;
+ }
+
+ vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX);
+
+ if ((vco < (VCO_MIN / 2U)) || (vco > (VCO_MAX / 2U))) {
+ frac++;
+ continue;
+ }
+
+ freq = vco / (divp + 1U);
+ if (output_freq < freq) {
+ diff = freq - output_freq;
+ } else {
+ diff = output_freq - freq;
+ }
+
+ if (diff < best_diff) {
+ pll1->vco.src = src;
+ pll1->vco.status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_PLLON;
+ pll1->vco.div_mn[PLL_CFG_M] = divm - 1U;
+ pll1->vco.div_mn[PLL_CFG_N] = (uint32_t)divn;
+ pll1->vco.frac = (uint32_t)frac;
+ pll1->output.output[PLL_CFG_P] = divp;
+
+ if (diff == 0U) {
+ return 0;
+ }
+
+ best_diff = diff;
+ }
+
+ frac++;
+ }
+ }
+ }
+
+ if (best_diff == ULLONG_MAX) {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
{
uintptr_t pll_base = priv->base + pll->reg_pllxcr;
@@ -1388,8 +1452,8 @@
/* Wait PLL lock */
while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) == 0U) {
if (timeout_elapsed(timeout)) {
- ERROR("%d clock start failed @ 0x%x: 0x%x\n",
- pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base));
+ ERROR("PLL%d start failed @ 0x%x: 0x%x\n",
+ pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base));
return -EINVAL;
}
}
@@ -1406,8 +1470,8 @@
/* Wait PLL lock */
while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) != 0U) {
if (timeout_elapsed(timeout)) {
- ERROR("%d clock stop failed @ 0x%x: 0x%x\n",
- pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base));
+ ERROR("PLL%d stop failed @ 0x%x: 0x%x\n",
+ pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base));
return -EINVAL;
}
}
@@ -1629,7 +1693,7 @@
}
struct stm32_pll_cfg {
- int pll_id;
+ uint8_t pll_id;
};
static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id,
@@ -1711,12 +1775,12 @@
.clock_cfg = &(struct stm32_pll_cfg) {\
.pll_id = _pll_id,\
},\
- .ops = &clk_stm32_pll_ops,\
+ .ops = STM32_PLL_OPS,\
}
struct clk_stm32_composite_cfg {
- int gate_id;
- int div_id;
+ uint8_t gate_id;
+ uint8_t div_id;
};
static unsigned long clk_stm32_composite_recalc_rate(struct stm32_clk_priv *priv,
@@ -1768,9 +1832,32 @@
.gate_id = (_gate_id),\
.div_id = (_div_id),\
},\
- .ops = &clk_stm32_composite_ops,\
+ .ops = STM32_COMPOSITE_OPS,\
}
+enum {
+ STM32_PLL_OPS = STM32_LAST_OPS,
+ STM32_COMPOSITE_OPS,
+
+ MP13_LAST_OPS
+};
+
+static const struct stm32_clk_ops *ops_array_mp13[MP13_LAST_OPS] = {
+ [NO_OPS] = NULL,
+ [FIXED_FACTOR_OPS] = &clk_fixed_factor_ops,
+ [GATE_OPS] = &clk_gate_ops,
+ [STM32_MUX_OPS] = &clk_mux_ops,
+ [STM32_DIVIDER_OPS] = &clk_stm32_divider_ops,
+ [STM32_GATE_OPS] = &clk_stm32_gate_ops,
+ [STM32_TIMER_OPS] = &clk_timer_ops,
+ [STM32_FIXED_RATE_OPS] = &clk_stm32_fixed_rate_ops,
+ [STM32_OSC_OPS] = &clk_stm32_osc_ops,
+ [STM32_OSC_NOGATE_OPS] = &clk_stm32_osc_nogate_ops,
+
+ [STM32_PLL_OPS] = &clk_stm32_pll_ops,
+ [STM32_COMPOSITE_OPS] = &clk_stm32_composite_ops
+};
+
static const struct clk_stm32 stm32mp13_clk[CK_LAST] = {
/* ROOT CLOCKS */
CLK_FIXED_RATE(_CK_OFF, _NO_ID, 0),
@@ -1882,7 +1969,6 @@
STM32_GATE(_SDMMC2_K, SDMMC2_K, MUX(MUX_SDMMC2), 0, GATE_SDMMC2),
STM32_GATE(_DBGCK, CK_DBG, _CKAXI, 0, GATE_DBGCK),
-/* TODO: CHECK CLOCK FOR BL2/BL32 AND IF ONLY FOR TEST OR NOT */
STM32_GATE(_USART3_K, USART3_K, MUX(MUX_UART35), 0, GATE_USART3),
STM32_GATE(_UART4_K, UART4_K, MUX(MUX_UART4), 0, GATE_UART4),
STM32_GATE(_UART5_K, UART5_K, MUX(MUX_UART35), 0, GATE_UART5),
@@ -1896,61 +1982,6 @@
STM32_COMPOSITE(_MCO1_K, CK_MCO1, MUX(MUX_MCO1), 0, GATE_MCO1, DIV_MCO1),
STM32_COMPOSITE(_MCO2_K, CK_MCO2, MUX(MUX_MCO2), 0, GATE_MCO2, DIV_MCO2),
STM32_COMPOSITE(_TRACECK, CK_TRACE, _CKAXI, 0, GATE_TRACECK, DIV_TRACE),
-
-#if defined(IMAGE_BL32)
- STM32_GATE(_TIM2, TIM2_K, _CKTIMG1, 0, GATE_TIM2),
- STM32_GATE(_TIM3, TIM3_K, _CKTIMG1, 0, GATE_TIM3),
- STM32_GATE(_TIM4, TIM4_K, _CKTIMG1, 0, GATE_TIM4),
- STM32_GATE(_TIM5, TIM5_K, _CKTIMG1, 0, GATE_TIM5),
- STM32_GATE(_TIM6, TIM6_K, _CKTIMG1, 0, GATE_TIM6),
- STM32_GATE(_TIM7, TIM7_K, _CKTIMG1, 0, GATE_TIM7),
- STM32_GATE(_TIM13, TIM13_K, _CKTIMG3, 0, GATE_TIM13),
- STM32_GATE(_TIM14, TIM14_K, _CKTIMG3, 0, GATE_TIM14),
- STM32_GATE(_LPTIM1_K, LPTIM1_K, MUX(MUX_LPTIM1), 0, GATE_LPTIM1),
- STM32_GATE(_SPI2_K, SPI2_K, MUX(MUX_SPI23), 0, GATE_SPI2),
- STM32_GATE(_SPI3_K, SPI3_K, MUX(MUX_SPI23), 0, GATE_SPI3),
- STM32_GATE(_SPDIF_K, SPDIF_K, MUX(MUX_SPDIF), 0, GATE_SPDIF),
- STM32_GATE(_TIM1, TIM1_K, _CKTIMG2, 0, GATE_TIM1),
- STM32_GATE(_TIM8, TIM8_K, _CKTIMG2, 0, GATE_TIM8),
- STM32_GATE(_TIM16, TIM16_K, _CKTIMG3, 0, GATE_TIM16),
- STM32_GATE(_TIM17, TIM17_K, _CKTIMG3, 0, GATE_TIM17),
- STM32_GATE(_SPI1_K, SPI1_K, MUX(MUX_SPI1), 0, GATE_SPI1),
- STM32_GATE(_SPI4_K, SPI4_K, MUX(MUX_SPI4), 0, GATE_SPI4),
- STM32_GATE(_SPI5_K, SPI5_K, MUX(MUX_SPI5), 0, GATE_SPI5),
- STM32_GATE(_SAI1_K, SAI1_K, MUX(MUX_SAI1), 0, GATE_SAI1),
- STM32_GATE(_SAI2_K, SAI2_K, MUX(MUX_SAI2), 0, GATE_SAI2),
- STM32_GATE(_DFSDM, DFSDM_K, MUX(MUX_SAI1), 0, GATE_DFSDM),
- STM32_GATE(_FDCAN_K, FDCAN_K, MUX(MUX_FDCAN), 0, GATE_FDCAN),
- STM32_GATE(_USBH, USBH, _CKAXI, 0, GATE_USBH),
- STM32_GATE(_I2C1_K, I2C1_K, MUX(MUX_I2C12), 0, GATE_I2C1),
- STM32_GATE(_I2C2_K, I2C2_K, MUX(MUX_I2C12), 0, GATE_I2C2),
- STM32_GATE(_ADFSDM, ADFSDM_K, MUX(MUX_SAI1), 0, GATE_ADFSDM),
- STM32_GATE(_LPTIM2_K, LPTIM2_K, MUX(MUX_LPTIM2), 0, GATE_LPTIM2),
- STM32_GATE(_LPTIM3_K, LPTIM3_K, MUX(MUX_LPTIM3), 0, GATE_LPTIM3),
- STM32_GATE(_LPTIM4_K, LPTIM4_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM4),
- STM32_GATE(_LPTIM5_K, LPTIM5_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM5),
- STM32_GATE(_VREF, VREF, _PCLK3, 0, GATE_VREF),
- STM32_GATE(_DTS, TMPSENS, _PCLK3, 0, GATE_DTS),
- STM32_GATE(_PMBCTRL, PMBCTRL, _PCLK3, 0, GATE_HDP),
- STM32_GATE(_HDP, HDP, _PCLK3, 0, GATE_PMBCTRL),
- STM32_GATE(_STGENRO, STGENRO, _PCLK4, 0, GATE_DCMIPP),
- STM32_GATE(_DCMIPP_K, DCMIPP_K, MUX(MUX_DCMIPP), 0, GATE_DCMIPP),
- STM32_GATE(_DMAMUX1, DMAMUX1, _CKAXI, 0, GATE_DMAMUX1),
- STM32_GATE(_DMAMUX2, DMAMUX2, _CKAXI, 0, GATE_DMAMUX2),
- STM32_GATE(_DMA3, DMA3, _CKAXI, 0, GATE_DMAMUX2),
- STM32_GATE(_ADC1_K, ADC1_K, MUX(MUX_ADC1), 0, GATE_ADC1),
- STM32_GATE(_ADC2_K, ADC2_K, MUX(MUX_ADC2), 0, GATE_ADC2),
- STM32_GATE(_TSC, TSC, _CKAXI, 0, GATE_TSC),
- STM32_GATE(_AXIMC, AXIMC, _CKAXI, 0, GATE_AXIMC),
- STM32_GATE(_CRC1, CRC1, _CKAXI, 0, GATE_ETH1TX),
- STM32_GATE(_ETH1CK, ETH1CK_K, MUX(MUX_ETH1), 0, GATE_ETH1CK),
- STM32_GATE(_ETH1TX, ETH1TX, _CKAXI, 0, GATE_ETH1TX),
- STM32_GATE(_ETH1RX, ETH1RX, _CKAXI, 0, GATE_ETH1RX),
- STM32_GATE(_ETH2CK, ETH2CK_K, MUX(MUX_ETH2), 0, GATE_ETH2CK),
- STM32_GATE(_ETH2TX, ETH2TX, _CKAXI, 0, GATE_ETH2TX),
- STM32_GATE(_ETH2RX, ETH2RX, _CKAXI, 0, GATE_ETH2RX),
- STM32_GATE(_ETH2MAC, ETH2MAC, _CKAXI, 0, GATE_ETH2MAC),
-#endif
};
static struct stm32_pll_dt_cfg mp13_pll[_PLL_NB];
@@ -1986,6 +2017,7 @@
.nb_osci_data = ARRAY_SIZE(stm32mp13_osc_data),
.gate_refcounts = refcounts_mp13,
.pdata = &stm32mp13_clock_pdata,
+ .ops_array = ops_array_mp13,
};
static int stm32mp1_init_clock_tree(void)
@@ -2072,8 +2104,6 @@
return 0;
}
-#define LSEDRV_MEDIUM_HIGH 2
-
static int clk_stm32_parse_oscillator_fdt(void *fdt, int node, const char *name,
struct stm32_osci_dt_cfg *osci)
{
@@ -2241,7 +2271,8 @@
{
size_t i = 0U;
- for (i = _PLL1; i < pdata->npll; i++) {
+ /* PLL1 is not configurable with device tree */
+ for (i = _PLL2; i < pdata->npll; i++) {
struct stm32_pll_dt_cfg *pll = &pdata->pll[i];
char name[RCC_PLL_NAME_SIZE];
int subnode = 0;
@@ -2301,32 +2332,47 @@
return 0;
}
-int stm32mp1_clk_init(void)
+void stm32mp1_clk_rcc_regs_lock(void)
{
- return 0;
+ clk_stm32_rcc_regs_lock();
}
-int stm32mp1_clk_probe(void)
+void stm32mp1_clk_rcc_regs_unlock(void)
{
- uintptr_t base = RCC_BASE;
+ clk_stm32_rcc_regs_unlock();
+}
+
+int stm32mp1_clk_init(void)
+{
int ret;
- ret = stm32_clk_parse_fdt(&stm32mp13_clock_pdata);
+ /* compute the PLL1 settings, not read in device tree */
+ ret = clk_compute_pll1_settings(PLL1_NOMINAL_FREQ_IN_KHZ);
if (ret != 0) {
return ret;
}
- ret = clk_stm32_init(&stm32mp13_clock_data, base);
+ ret = stm32mp1_init_clock_tree();
if (ret != 0) {
return ret;
}
- ret = stm32mp1_init_clock_tree();
+ clk_stm32_enable_critical_clocks();
+
+ return 0;
+}
+
+int stm32mp1_clk_probe(void)
+{
+ uintptr_t base = RCC_BASE;
+ int ret;
+
+ ret = stm32_clk_parse_fdt(&stm32mp13_clock_pdata);
if (ret != 0) {
return ret;
}
- clk_stm32_enable_critical_clocks();
+ ret = clk_stm32_init(&stm32mp13_clock_data, base);
- return 0;
+ return ret;
}
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index 818fd85..3d352af 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -27,6 +27,71 @@
#include <platform_def.h>
+enum stm32mp1_pllcfg {
+ PLLCFG_M,
+ PLLCFG_N,
+ PLL_DIV_MN_NB,
+ PLLCFG_P = PLL_DIV_MN_NB,
+ PLLCFG_Q,
+ PLLCFG_R,
+ PLLCFG_O,
+ PLLCFG_NB
+};
+
+#define PLL_DIV_MN_NB 2
+#define PLL_DIV_PQR_NB 3
+
+enum stm32mp1_pllcsg {
+ PLLCSG_MOD_PER,
+ PLLCSG_INC_STEP,
+ PLLCSG_SSCG_MODE,
+ PLLCSG_NB
+};
+
+struct stm32_pll_dt_cfg {
+ bool status;
+ uint32_t src;
+ uint32_t cfg[PLLCFG_NB];
+ uint32_t frac;
+ bool csg_enabled;
+ uint32_t csg[PLLCSG_NB];
+};
+
+struct stm32_clk_platdata {
+ uint32_t npll;
+ struct stm32_pll_dt_cfg *pll;
+ uint32_t nclksrc;
+ uint32_t *clksrc;
+ uint32_t nclkdiv;
+ uint32_t *clkdiv;
+ bool lse_css;
+};
+
+struct stm32_clk_priv {
+ uintptr_t base;
+ const struct mux_cfg *parents;
+ const uint32_t nb_parents;
+ const struct div_cfg *div;
+ const uint32_t nb_div;
+ void *pdata;
+};
+
+static struct stm32_clk_priv *stm32_clock_data;
+
+static struct stm32_clk_priv *clk_stm32_get_priv(void)
+{
+ return stm32_clock_data;
+}
+
+static int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base)
+{
+ stm32_clock_data = priv;
+
+ priv->base = base;
+
+ return 0;
+}
+
#define MAX_HSI_HZ 64000000
#define USB_PHY_48_MHZ 48000000
@@ -39,6 +104,199 @@
#define HSIDIV_TIMEOUT TIMEOUT_US_200MS
#define OSCRDY_TIMEOUT TIMEOUT_US_1S
+struct mux_cfg {
+ uint16_t offset;
+ uint8_t shift;
+ uint8_t width;
+ uint8_t bitrdy;
+};
+
+struct div_cfg {
+ uint16_t offset;
+ uint8_t shift;
+ uint8_t width;
+ uint8_t bitrdy;
+};
+
+#define DIV_NO_BIT_RDY UINT8_MAX
+
+#define DIV_CFG(_id, _offset, _shift, _width, _bitrdy)\
+ [(_id)] = {\
+ .offset = (_offset),\
+ .shift = (_shift),\
+ .width = (_width),\
+ .bitrdy = (_bitrdy),\
+ }
+
+static const struct div_cfg dividers_mp15[] = {
+ DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 31),
+ DIV_CFG(DIV_AXI, RCC_AXIDIVR, 0, 3, 31),
+ DIV_CFG(DIV_MCU, RCC_MCUDIVR, 0, 4, 31),
+ DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 31),
+ DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 31),
+ DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 31),
+ DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 31),
+ DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 31),
+ DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, DIV_NO_BIT_RDY),
+ DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, DIV_NO_BIT_RDY),
+ DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, DIV_NO_BIT_RDY),
+ DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, DIV_NO_BIT_RDY),
+ DIV_CFG(DIV_ETHPTP, RCC_ETHCKSELR, 4, 4, DIV_NO_BIT_RDY),
+};
+
+/*
+ * MUX CONFIG
+ */
+
+#define MUX_NO_BIT_RDY UINT8_MAX
+
+#define MUXRDY_CFG(_id, _offset, _shift, _width, _bitrdy)\
+ [(_id)] = {\
+ .offset = (_offset),\
+ .shift = (_shift),\
+ .width = (_width),\
+ .bitrdy = (_bitrdy),\
+ }
+
+#define MUX_CFG(_id, _offset, _shift, _width)\
+ MUXRDY_CFG(_id, _offset, _shift, _width, MUX_NO_BIT_RDY)
+
+static const struct mux_cfg parent_mp15[MUX_NB] = {
+ MUX_CFG(MUX_PLL12, RCC_RCK12SELR, 0, 2),
+ MUX_CFG(MUX_PLL3, RCC_RCK3SELR, 0, 2),
+ MUX_CFG(MUX_PLL4, RCC_RCK4SELR, 0, 2),
+ MUX_CFG(MUX_CKPER, RCC_CPERCKSELR, 0, 2),
+ MUXRDY_CFG(MUX_MPU, RCC_MPCKSELR, 0, 2, 31),
+ MUXRDY_CFG(MUX_AXI, RCC_ASSCKSELR, 0, 3, 31),
+ MUXRDY_CFG(MUX_MCU, RCC_MSSCKSELR, 0, 2, 31),
+ MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2),
+ MUX_CFG(MUX_SDMMC12, RCC_SDMMC12CKSELR, 0, 3),
+ MUX_CFG(MUX_SPI2S23, RCC_SPI2S23CKSELR, 0, 3),
+ MUX_CFG(MUX_SPI45, RCC_SPI45CKSELR, 0, 3),
+ MUX_CFG(MUX_I2C12, RCC_I2C12CKSELR, 0, 3),
+ MUX_CFG(MUX_I2C35, RCC_I2C35CKSELR, 0, 3),
+ MUX_CFG(MUX_LPTIM23, RCC_LPTIM23CKSELR, 0, 3),
+ MUX_CFG(MUX_LPTIM45, RCC_LPTIM45CKSELR, 0, 3),
+ MUX_CFG(MUX_UART24, RCC_UART24CKSELR, 0, 3),
+ MUX_CFG(MUX_UART35, RCC_UART35CKSELR, 0, 3),
+ MUX_CFG(MUX_UART78, RCC_UART78CKSELR, 0, 3),
+ MUX_CFG(MUX_SAI1, RCC_SAI1CKSELR, 0, 3),
+ MUX_CFG(MUX_ETH, RCC_ETHCKSELR, 0, 2),
+ MUX_CFG(MUX_I2C46, RCC_I2C46CKSELR, 0, 3),
+ MUX_CFG(MUX_RNG2, RCC_RNG2CKSELR, 0, 2),
+ MUX_CFG(MUX_SDMMC3, RCC_SDMMC3CKSELR, 0, 3),
+ MUX_CFG(MUX_FMC, RCC_FMCCKSELR, 0, 2),
+ MUX_CFG(MUX_QSPI, RCC_QSPICKSELR, 0, 2),
+ MUX_CFG(MUX_USBPHY, RCC_USBCKSELR, 0, 2),
+ MUX_CFG(MUX_USBO, RCC_USBCKSELR, 4, 1),
+ MUX_CFG(MUX_SPDIF, RCC_SPDIFCKSELR, 0, 2),
+ MUX_CFG(MUX_SPI2S1, RCC_SPI2S1CKSELR, 0, 3),
+ MUX_CFG(MUX_CEC, RCC_CECCKSELR, 0, 2),
+ MUX_CFG(MUX_LPTIM1, RCC_LPTIM1CKSELR, 0, 3),
+ MUX_CFG(MUX_UART6, RCC_UART6CKSELR, 0, 3),
+ MUX_CFG(MUX_FDCAN, RCC_FDCANCKSELR, 0, 2),
+ MUX_CFG(MUX_SAI2, RCC_SAI2CKSELR, 0, 3),
+ MUX_CFG(MUX_SAI3, RCC_SAI3CKSELR, 0, 3),
+ MUX_CFG(MUX_SAI4, RCC_SAI4CKSELR, 0, 3),
+ MUX_CFG(MUX_ADC, RCC_ADCCKSELR, 0, 2),
+ MUX_CFG(MUX_DSI, RCC_DSICKSELR, 0, 1),
+ MUX_CFG(MUX_RNG1, RCC_RNG1CKSELR, 0, 2),
+ MUX_CFG(MUX_STGEN, RCC_STGENCKSELR, 0, 2),
+ MUX_CFG(MUX_UART1, RCC_UART1CKSELR, 0, 3),
+ MUX_CFG(MUX_SPI6, RCC_SPI6CKSELR, 0, 3),
+ MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 3),
+ MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 3),
+};
+
+#define MASK_WIDTH_SHIFT(_width, _shift) \
+ GENMASK(((_width) + (_shift) - 1U), (_shift))
+
+int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id)
+{
+ const struct mux_cfg *mux;
+ uint32_t mask;
+
+ if (mux_id >= priv->nb_parents) {
+ panic();
+ }
+
+ mux = &priv->parents[mux_id];
+
+ mask = MASK_WIDTH_SHIFT(mux->width, mux->shift);
+
+ return (mmio_read_32(priv->base + mux->offset) & mask) >> mux->shift;
+}
+
+static int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel)
+{
+ const struct mux_cfg *mux = &priv->parents[pid];
+ uintptr_t address = priv->base + mux->offset;
+ uint32_t mask;
+ uint64_t timeout;
+
+ mask = MASK_WIDTH_SHIFT(mux->width, mux->shift);
+
+ mmio_clrsetbits_32(address, mask, (sel << mux->shift) & mask);
+
+ if (mux->bitrdy == MUX_NO_BIT_RDY) {
+ return 0;
+ }
+
+ timeout = timeout_init_us(CLKSRC_TIMEOUT);
+
+ mask = BIT(mux->bitrdy);
+
+ while ((mmio_read_32(address) & mask) == 0U) {
+ if (timeout_elapsed(timeout)) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t val)
+{
+ uint32_t data = val & CMD_DATA_MASK;
+ int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT;
+ int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
+
+ return clk_mux_set_parent(priv, mux, sel);
+}
+
+int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value)
+{
+ const struct div_cfg *divider;
+ uintptr_t address;
+ uint64_t timeout;
+ uint32_t mask;
+
+ if (div_id >= priv->nb_div) {
+ panic();
+ }
+
+ divider = &priv->div[div_id];
+ address = priv->base + divider->offset;
+
+ mask = MASK_WIDTH_SHIFT(divider->width, divider->shift);
+ mmio_clrsetbits_32(address, mask, (value << divider->shift) & mask);
+
+ if (divider->bitrdy == DIV_NO_BIT_RDY) {
+ return 0;
+ }
+
+ timeout = timeout_init_us(CLKSRC_TIMEOUT);
+ mask = BIT(divider->bitrdy);
+
+ while ((mmio_read_32(address) & mask) == 0U) {
+ if (timeout_elapsed(timeout)) {
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
const char *stm32mp_osc_node_label[NB_OSC] = {
[_LSI] = "clk-lsi",
[_LSE] = "clk-lse",
@@ -206,23 +464,6 @@
CLKDIV_NB
};
-enum stm32mp1_pllcfg {
- PLLCFG_M,
- PLLCFG_N,
- PLLCFG_P,
- PLLCFG_Q,
- PLLCFG_R,
- PLLCFG_O,
- PLLCFG_NB
-};
-
-enum stm32mp1_pllcsg {
- PLLCSG_MOD_PER,
- PLLCSG_INC_STEP,
- PLLCSG_SSCG_MODE,
- PLLCSG_NB
-};
-
enum stm32mp1_plltype {
PLL_800,
PLL_1600,
@@ -537,7 +778,18 @@
};
/* Define characteristic of PLL according type */
-#define DIVN_MIN 24
+#define POST_DIVM_MIN 8000000U
+#define POST_DIVM_MAX 16000000U
+#define DIVM_MIN 0U
+#define DIVM_MAX 63U
+#define DIVN_MIN 24U
+#define DIVN_MAX 99U
+#define DIVP_MIN 0U
+#define DIVP_MAX 127U
+#define FRAC_MAX 8192U
+#define VCO_MIN 800000000U
+#define VCO_MAX 1600000000U
+
static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
[PLL_800] = {
.refclk_min = 4,
@@ -1327,6 +1579,11 @@
uint32_t value;
uintptr_t rcc_base = stm32mp_rcc_base();
+ /* Do not reconfigure LSE if it is already ON */
+ if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) {
+ return;
+ }
+
if (digbyp) {
mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP);
}
@@ -1360,7 +1617,7 @@
static void stm32mp1_lse_wait(void)
{
if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) {
- VERBOSE("%s: failed\n", __func__);
+ EARLY_ERROR("%s: failed\n", __func__);
}
}
@@ -1369,7 +1626,7 @@
stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION);
if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) {
- VERBOSE("%s: failed\n", __func__);
+ EARLY_ERROR("%s: failed\n", __func__);
}
}
@@ -1387,7 +1644,7 @@
stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON);
if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) {
- VERBOSE("%s: failed\n", __func__);
+ EARLY_ERROR("%s: failed\n", __func__);
}
if (css) {
@@ -1406,7 +1663,7 @@
{
stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION);
if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) {
- VERBOSE("%s: failed\n", __func__);
+ EARLY_ERROR("%s: failed\n", __func__);
}
}
@@ -1414,7 +1671,7 @@
{
stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION);
if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) {
- VERBOSE("%s: failed\n", __func__);
+ EARLY_ERROR("%s: failed\n", __func__);
}
}
@@ -1454,7 +1711,7 @@
}
if (hsidiv == 4U) {
- ERROR("Invalid clk-hsi frequency\n");
+ EARLY_ERROR("Invalid clk-hsi frequency\n");
return -1;
}
@@ -1467,7 +1724,7 @@
static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id,
unsigned int clksrc,
- uint32_t *pllcfg, int plloff)
+ uint32_t *pllcfg, uint32_t fracv)
{
const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
uintptr_t rcc_base = stm32mp_rcc_base();
@@ -1476,8 +1733,7 @@
uintptr_t clksrc_address = rcc_base + (clksrc >> 4);
unsigned long refclk;
uint32_t ifrge = 0U;
- uint32_t src, value, fracv = 0;
- void *fdt;
+ uint32_t src, value;
/* Check PLL output */
if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) {
@@ -1516,10 +1772,6 @@
}
/* Fractional configuration */
- if (fdt_get_address(&fdt) == 1) {
- fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0);
- }
-
value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
value |= RCC_PLLNFRACR_FRACLE;
if (mmio_read_32(rcc_base + pll->pllxfracr) != value) {
@@ -1561,8 +1813,8 @@
/* Wait PLL lock */
while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) {
if (timeout_elapsed(timeout)) {
- ERROR("PLL%u start failed @ 0x%lx: 0x%x\n",
- pll_id, pllxcr, mmio_read_32(pllxcr));
+ EARLY_ERROR("PLL%u start failed @ 0x%lx: 0x%x\n",
+ pll_id, pllxcr, mmio_read_32(pllxcr));
return -ETIMEDOUT;
}
}
@@ -1590,8 +1842,8 @@
/* Wait PLL stopped */
while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) {
if (timeout_elapsed(timeout)) {
- ERROR("PLL%u stop failed @ 0x%lx: 0x%x\n",
- pll_id, pllxcr, mmio_read_32(pllxcr));
+ EARLY_ERROR("PLL%u stop failed @ 0x%lx: 0x%x\n",
+ pll_id, pllxcr, mmio_read_32(pllxcr));
return -ETIMEDOUT;
}
}
@@ -1683,190 +1935,270 @@
RCC_PLLNCR_SSCG_CTRL);
}
-static int stm32mp1_set_clksrc(unsigned int clksrc)
+static int clk_compute_pll1_settings(unsigned long input_freq,
+ uint32_t freq_khz,
+ uint32_t *pllcfg, uint32_t *fracv)
{
- uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
- uint64_t timeout;
+ unsigned long long best_diff = ULLONG_MAX;
+ unsigned int divm;
- mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK,
- clksrc & RCC_SELR_SRC_MASK);
+ /* Following parameters have always the same value */
+ pllcfg[PLLCFG_Q] = 0U;
+ pllcfg[PLLCFG_R] = 0U;
+ pllcfg[PLLCFG_O] = PQR(1, 0, 0);
- timeout = timeout_init_us(CLKSRC_TIMEOUT);
- while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) {
- if (timeout_elapsed(timeout)) {
- ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc,
- clksrc_address, mmio_read_32(clksrc_address));
- return -ETIMEDOUT;
+ for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) {
+ unsigned long post_divm = input_freq / divm;
+ unsigned int divp;
+
+ if ((post_divm < POST_DIVM_MIN) || (post_divm > POST_DIVM_MAX)) {
+ continue;
}
+
+ for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
+ unsigned long long output_freq = freq_khz * 1000ULL;
+ unsigned long long freq;
+ unsigned long long divn;
+ unsigned long long frac;
+ unsigned int i;
+
+ freq = output_freq * divm * (divp + 1U);
+
+ divn = (freq / input_freq) - 1U;
+ if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) {
+ continue;
+ }
+
+ frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX);
+
+ /* 2 loops to refine the fractional part */
+ for (i = 2U; i != 0U; i--) {
+ unsigned long long diff;
+ unsigned long long vco;
+
+ if (frac > FRAC_MAX) {
+ break;
+ }
+
+ vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX);
+
+ if ((vco < (VCO_MIN / 2U)) || (vco > (VCO_MAX / 2U))) {
+ frac++;
+ continue;
+ }
+
+ freq = vco / (divp + 1U);
+ if (output_freq < freq) {
+ diff = freq - output_freq;
+ } else {
+ diff = output_freq - freq;
+ }
+
+ if (diff < best_diff) {
+ pllcfg[PLLCFG_M] = divm - 1U;
+ pllcfg[PLLCFG_N] = (uint32_t)divn;
+ pllcfg[PLLCFG_P] = divp;
+ *fracv = (uint32_t)frac;
+
+ if (diff == 0U) {
+ return 0;
+ }
+
+ best_diff = diff;
+ }
+
+ frac++;
+ }
+ }
+ }
+
+ if (best_diff == ULLONG_MAX) {
+ return -EINVAL;
}
return 0;
}
-static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address)
+static int clk_get_pll1_settings(uint32_t clksrc, uint32_t freq_khz,
+ uint32_t *pllcfg, uint32_t *fracv)
{
- uint64_t timeout;
+ unsigned long input_freq = 0UL;
- mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK,
- clkdiv & RCC_DIVR_DIV_MASK);
+ assert(pllcfg != NULL);
+ assert(fracv != NULL);
- timeout = timeout_init_us(CLKDIV_TIMEOUT);
- while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) {
- if (timeout_elapsed(timeout)) {
- ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n",
- clkdiv, address, mmio_read_32(address));
- return -ETIMEDOUT;
- }
+ switch (clksrc) {
+ case CLK_PLL12_HSI:
+ input_freq = stm32mp_clk_get_rate(CK_HSI);
+ break;
+ case CLK_PLL12_HSE:
+ input_freq = stm32mp_clk_get_rate(CK_HSE);
+ break;
+ default:
+ break;
}
- return 0;
+ if (input_freq == 0UL) {
+ panic();
+ }
+
+ return clk_compute_pll1_settings(input_freq, freq_khz, pllcfg, fracv);
}
-static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv)
+static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv)
{
- uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
+ struct stm32_clk_platdata *pdata = priv->pdata;
+ uint32_t i;
- /*
- * Binding clksrc :
- * bit15-4 offset
- * bit3: disable
- * bit2-0: MCOSEL[2:0]
- */
- if ((clksrc & 0x8U) != 0U) {
- mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON);
- } else {
- mmio_clrsetbits_32(clksrc_address,
- RCC_MCOCFG_MCOSRC_MASK,
- clksrc & RCC_MCOCFG_MCOSRC_MASK);
- mmio_clrsetbits_32(clksrc_address,
- RCC_MCOCFG_MCODIV_MASK,
- clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
- mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON);
+ for (i = 0U; i < pdata->nclkdiv; i++) {
+ uint32_t div_id, div_n;
+ uint32_t val;
+ int ret;
+
+ val = pdata->clkdiv[i] & CMD_DATA_MASK;
+ div_id = (val & DIV_ID_MASK) >> DIV_ID_SHIFT;
+ div_n = (val & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT;
+
+ ret = clk_stm32_set_div(priv, div_id, div_n);
+ if (ret != 0) {
+ return ret;
+ }
}
+
+ return 0;
}
-static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
+static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data)
{
- uintptr_t address = stm32mp_rcc_base() + RCC_BDCR;
+ uint32_t sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT;
+ uint32_t enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT;
+ unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT;
+ struct stm32_clk_platdata *pdata = priv->pdata;
- if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) ||
- (clksrc != (uint32_t)CLK_RTC_DISABLED)) {
- mmio_clrsetbits_32(address,
- RCC_BDCR_RTCSRC_MASK,
- (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT);
+ if (binding_id == RTC) {
+ uintptr_t address = stm32mp_rcc_base() + RCC_BDCR;
- mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
- }
+ if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || (enable != 0U)) {
+ mmio_clrsetbits_32(address, RCC_BDCR_RTCSRC_MASK,
+ (sel & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT);
- if (lse_css) {
- mmio_setbits_32(address, RCC_BDCR_LSECSSON);
+ mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
+ /* Configure LSE CSS */
+ if (pdata->lse_css) {
+ mmio_setbits_32(priv->base + RCC_BDCR, RCC_BDCR_LSECSSON);
+ }
+ }
}
+
+ return 0;
}
-static void stm32mp1_pkcs_config(uint32_t pkcs)
+static int stm32_clk_configure_by_addr_val(struct stm32_clk_priv *priv,
+ uint32_t data)
{
- uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU);
- uint32_t value = pkcs & 0xFU;
- uint32_t mask = 0xFU;
+ uint32_t addr = data >> CLK_ADDR_SHIFT;
+ uint32_t val = data & CLK_ADDR_VAL_MASK;
- if ((pkcs & BIT(31)) != 0U) {
- mask <<= 4;
- value <<= 4;
- }
+ mmio_setbits_32(priv->base + addr, val);
- mmio_clrsetbits_32(address, mask, value);
+ return 0;
}
-static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg,
- uint32_t *fracv, uint32_t *csg,
- bool *csg_set)
+static int stm32_clk_source_configure(struct stm32_clk_priv *priv)
{
- void *fdt;
- int ret;
+ struct stm32_clk_platdata *pdata = priv->pdata;
+ bool ckper_disabled = false;
+ uint32_t i;
- if (fdt_get_address(&fdt) == 0) {
- return -FDT_ERR_NOTFOUND;
- }
+ for (i = 0U; i < pdata->nclksrc; i++) {
+ uint32_t val = pdata->clksrc[i];
+ uint32_t cmd, cmd_data;
+ int ret;
- ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB,
- pllcfg);
- if (ret < 0) {
- return -FDT_ERR_NOTFOUND;
+ if (val & CMD_ADDR_BIT) {
+ ret = stm32_clk_configure_by_addr_val(priv, val & ~CMD_ADDR_BIT);
+ if (ret != 0) {
+ return ret;
+ }
+
+ continue;
+ }
+
+ if (val == (uint32_t)CLK_CKPER_DISABLED) {
+ ckper_disabled = true;
+ continue;
+ }
+
+ cmd = (val & CMD_MASK) >> CMD_SHIFT;
+ cmd_data = val & ~CMD_MASK;
+
+ switch (cmd) {
+ case CMD_MUX:
+ ret = stm32_clk_configure_mux(priv, cmd_data);
+ break;
+
+ case CMD_CLK:
+ ret = stm32_clk_configure_clk(priv, cmd_data);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret != 0) {
+ return ret;
+ }
}
- *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0);
+ /*
+ * CKPER is source for some peripheral clocks
+ * (FMC-NAND / QPSI-NOR) and switching source is allowed
+ * only if previous clock is still ON
+ * => deactivate CKPER only after switching clock
+ */
+ if (!ckper_disabled) {
+ return 0;
+ }
- ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB,
- csg);
+ return stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED);
+}
- *csg_set = (ret == 0);
+static int stm32mp1_pll_configure_src(struct stm32_clk_priv *priv, int pll_idx)
+{
+ struct stm32_clk_platdata *pdata = priv->pdata;
+ struct stm32_pll_dt_cfg *pll_conf = &pdata->pll[pll_idx];
- if (ret == -FDT_ERR_NOTFOUND) {
- ret = 0;
+ if (!pll_conf->status) {
+ return 0;
}
- return ret;
+ return stm32_clk_configure_mux(priv, pll_conf->src);
}
int stm32mp1_clk_init(void)
{
- uintptr_t rcc_base = stm32mp_rcc_base();
- uint32_t pllfracv[_PLL_NB];
- uint32_t pllcsg[_PLL_NB][PLLCSG_NB];
- unsigned int clksrc[CLKSRC_NB];
- unsigned int clkdiv[CLKDIV_NB];
- unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
- int plloff[_PLL_NB];
- int ret, len;
+ struct stm32_clk_priv *priv = clk_stm32_get_priv();
+ struct stm32_clk_platdata *pdata = priv->pdata;
+ struct stm32_pll_dt_cfg *pll_conf = pdata->pll;
+ int ret;
enum stm32mp1_pll_id i;
- bool pllcsg_set[_PLL_NB];
- bool pllcfg_valid[_PLL_NB];
- bool lse_css = false;
bool pll3_preserve = false;
bool pll4_preserve = false;
bool pll4_bootrom = false;
- const fdt32_t *pkcs_cell;
- void *fdt;
int stgen_p = stm32mp1_clk_get_parent(STGEN_K);
int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K);
-
- if (fdt_get_address(&fdt) == 0) {
- return -FDT_ERR_NOTFOUND;
- }
-
- ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB,
- clksrc);
- if (ret < 0) {
- return -FDT_ERR_NOTFOUND;
- }
-
- ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB,
- clkdiv);
- if (ret < 0) {
- return -FDT_ERR_NOTFOUND;
- }
-
- for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
- char name[12];
-
- snprintf(name, sizeof(name), "st,pll@%u", i);
- plloff[i] = fdt_rcc_subnode_offset(name);
-
- pllcfg_valid[i] = fdt_check_node(plloff[i]);
- if (!pllcfg_valid[i]) {
- continue;
- }
+ uint32_t usbreg_bootrom = 0U;
- ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i],
- &pllfracv[i], pllcsg[i],
- &pllcsg_set[i]);
+ if (!pll_conf[_PLL1].status) {
+ ret = clk_get_pll1_settings(pll_conf[_PLL2].src, PLL1_NOMINAL_FREQ_IN_KHZ,
+ pll_conf[_PLL1].cfg, &pll_conf[_PLL1].frac);
if (ret != 0) {
return ret;
}
- }
- stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
- stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
+ pll_conf[_PLL1].status = true;
+ pll_conf[_PLL1].src = pll_conf[_PLL2].src;
+ }
/*
* Switch ON oscillator found in device-tree.
@@ -1882,7 +2214,7 @@
bypass = fdt_clk_read_bool(name, "st,bypass");
digbyp = fdt_clk_read_bool(name, "st,digbypass");
- lse_css = fdt_clk_read_bool(name, "st,css");
+ pdata->lse_css = fdt_clk_read_bool(name, "st,css");
lsedrv = fdt_clk_read_uint32_default(name, "st,drive",
LSEDRV_MEDIUM_HIGH);
stm32mp1_lse_enable(bypass, digbyp, lsedrv);
@@ -1903,36 +2235,28 @@
stm32mp1_csi_set(true);
/* Come back to HSI */
- ret = stm32mp1_set_clksrc(CLK_MPU_HSI);
+ ret = stm32_clk_configure_mux(priv, CLK_MPU_HSI);
if (ret != 0) {
return ret;
}
- ret = stm32mp1_set_clksrc(CLK_AXI_HSI);
+ ret = stm32_clk_configure_mux(priv, CLK_AXI_HSI);
if (ret != 0) {
return ret;
}
- ret = stm32mp1_set_clksrc(CLK_MCU_HSI);
+ ret = stm32_clk_configure_mux(priv, CLK_MCU_HSI);
if (ret != 0) {
return ret;
}
-
- if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) &
+ if ((mmio_read_32(priv->base + RCC_MP_RSTSCLRR) &
RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) {
- if (pllcfg_valid[_PLL3]) {
- pll3_preserve =
- stm32mp1_check_pll_conf(_PLL3,
- clksrc[CLKSRC_PLL3],
- pllcfg[_PLL3],
- plloff[_PLL3]);
- }
-
- if (pllcfg_valid[_PLL4]) {
- pll4_preserve =
- stm32mp1_check_pll_conf(_PLL4,
- clksrc[CLKSRC_PLL4],
- pllcfg[_PLL4],
- plloff[_PLL4]);
- }
+ pll3_preserve = stm32mp1_check_pll_conf(_PLL3,
+ pll_conf[_PLL3].src,
+ pll_conf[_PLL3].cfg,
+ pll_conf[_PLL3].frac);
+ pll4_preserve = stm32mp1_check_pll_conf(_PLL4,
+ pll_conf[_PLL4].src,
+ pll_conf[_PLL4].cfg,
+ pll_conf[_PLL4].frac);
}
/* Don't initialize PLL4, when used by BOOTROM */
if ((stm32mp_get_boot_itf_selected() ==
@@ -1964,58 +2288,27 @@
stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K));
}
- /* Select DIV */
- /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
- mmio_write_32(rcc_base + RCC_MPCKDIVR,
- clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK);
- ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR);
- if (ret != 0) {
- return ret;
- }
- ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR);
- if (ret != 0) {
- return ret;
- }
- ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR);
- if (ret != 0) {
- return ret;
- }
- ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR);
- if (ret != 0) {
- return ret;
- }
- ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR);
- if (ret != 0) {
- return ret;
- }
- ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR);
- if (ret != 0) {
- return ret;
- }
- ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR);
+ /* Configure dividers */
+ ret = stm32_clk_dividers_configure(priv);
if (ret != 0) {
return ret;
}
- /* No ready bit for RTC */
- mmio_write_32(rcc_base + RCC_RTCDIVR,
- clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK);
-
/* Configure PLLs source */
- ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]);
+ ret = stm32mp1_pll_configure_src(priv, _PLL1);
if (ret != 0) {
return ret;
}
if (!pll3_preserve) {
- ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]);
+ ret = stm32mp1_pll_configure_src(priv, _PLL3);
if (ret != 0) {
return ret;
}
}
if (!pll4_preserve) {
- ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]);
+ ret = stm32mp1_pll_configure_src(priv, _PLL4);
if (ret != 0) {
return ret;
}
@@ -2028,34 +2321,34 @@
continue;
}
- if (!pllcfg_valid[i]) {
+ if (!pll_conf[i].status) {
continue;
}
if ((i == _PLL4) && pll4_bootrom) {
/* Set output divider if not done by the Bootrom */
- stm32mp1_pll_config_output(i, pllcfg[i]);
+ stm32mp1_pll_config_output(i, pll_conf[i].cfg);
continue;
}
- ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]);
+ ret = stm32mp1_pll_config(i, pll_conf[i].cfg, pll_conf[i].frac);
if (ret != 0) {
return ret;
}
- if (pllcsg_set[i]) {
- stm32mp1_pll_csg(i, pllcsg[i]);
+ if (pll_conf[i].csg_enabled) {
+ stm32mp1_pll_csg(i, pll_conf[i].csg);
}
stm32mp1_pll_start(i);
}
/* Wait and start PLLs output when ready */
for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
- if (!pllcfg_valid[i]) {
+ if (!pll_conf[i].status) {
continue;
}
- ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]);
+ ret = stm32mp1_pll_output(i, pll_conf[i].cfg[PLLCFG_O]);
if (ret != 0) {
return ret;
}
@@ -2065,69 +2358,32 @@
stm32mp1_lse_wait();
}
- /* Configure with expected clock source */
- ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]);
- if (ret != 0) {
- return ret;
+ if (pll4_bootrom) {
+ usbreg_bootrom = mmio_read_32(priv->base + RCC_USBCKSELR);
}
- ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]);
- if (ret != 0) {
- return ret;
- }
- ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]);
+
+ /* Configure with expected clock source */
+ ret = stm32_clk_source_configure(priv);
if (ret != 0) {
- return ret;
+ panic();
}
- stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css);
- /* Configure PKCK */
- pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len);
- if (pkcs_cell != NULL) {
- bool ckper_disabled = false;
- uint32_t j;
- uint32_t usbreg_bootrom = 0U;
-
- if (pll4_bootrom) {
- usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR);
- }
+ if (pll4_bootrom) {
+ uint32_t usbreg_value, usbreg_mask;
+ const struct stm32mp1_clk_sel *sel;
- for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) {
- uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]);
+ sel = clk_sel_ref(_USBPHY_SEL);
+ usbreg_mask = (uint32_t)sel->msk << sel->src;
+ sel = clk_sel_ref(_USBO_SEL);
+ usbreg_mask |= (uint32_t)sel->msk << sel->src;
- if (pkcs == (uint32_t)CLK_CKPER_DISABLED) {
- ckper_disabled = true;
- continue;
- }
- stm32mp1_pkcs_config(pkcs);
- }
-
- /*
- * CKPER is source for some peripheral clocks
- * (FMC-NAND / QPSI-NOR) and switching source is allowed
- * only if previous clock is still ON
- * => deactivated CKPER only after switching clock
- */
- if (ckper_disabled) {
- stm32mp1_pkcs_config(CLK_CKPER_DISABLED);
- }
-
- if (pll4_bootrom) {
- uint32_t usbreg_value, usbreg_mask;
- const struct stm32mp1_clk_sel *sel;
-
- sel = clk_sel_ref(_USBPHY_SEL);
- usbreg_mask = (uint32_t)sel->msk << sel->src;
- sel = clk_sel_ref(_USBO_SEL);
- usbreg_mask |= (uint32_t)sel->msk << sel->src;
-
- usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) &
- usbreg_mask;
- usbreg_bootrom &= usbreg_mask;
- if (usbreg_bootrom != usbreg_value) {
- VERBOSE("forbidden new USB clk path\n");
- VERBOSE("vs bootrom on USB boot\n");
- return -FDT_ERR_BADVALUE;
- }
+ usbreg_value = mmio_read_32(priv->base + RCC_USBCKSELR) &
+ usbreg_mask;
+ usbreg_bootrom &= usbreg_mask;
+ if (usbreg_bootrom != usbreg_value) {
+ EARLY_ERROR("forbidden new USB clk path\n");
+ EARLY_ERROR("vs bootrom on USB boot\n");
+ return -FDT_ERR_BADVALUE;
}
}
@@ -2139,7 +2395,7 @@
stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K));
/* Software Self-Refresh mode (SSR) during DDR initilialization */
- mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR,
+ mmio_clrsetbits_32(priv->base + RCC_DDRITFCR,
RCC_DDRITFCR_DDRCKMOD_MASK,
RCC_DDRITFCR_DDRCKMOD_SSR <<
RCC_DDRITFCR_DDRCKMOD_SHIFT);
@@ -2366,8 +2622,199 @@
.get_parent = stm32mp1_clk_get_parent,
};
+struct stm32_pll_dt_cfg mp15_pll[_PLL_NB];
+uint32_t mp15_clksrc[MUX_NB];
+uint32_t mp15_clkdiv[DIV_NB];
+
+struct stm32_clk_platdata stm32mp15_clock_pdata = {
+ .pll = mp15_pll,
+ .npll = _PLL_NB,
+ .clksrc = mp15_clksrc,
+ .nclksrc = MUX_NB,
+ .clkdiv = mp15_clkdiv,
+ .nclkdiv = DIV_NB,
+};
+
+static struct stm32_clk_priv stm32mp15_clock_data = {
+ .base = RCC_BASE,
+ .parents = parent_mp15,
+ .nb_parents = ARRAY_SIZE(parent_mp15),
+ .div = dividers_mp15,
+ .nb_div = ARRAY_SIZE(dividers_mp15),
+ .pdata = &stm32mp15_clock_pdata,
+};
+
+static int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name,
+ uint32_t *tab, uint32_t *nb)
+{
+ const fdt32_t *cell;
+ int len = 0;
+ uint32_t i;
+
+ cell = fdt_getprop(fdt, node, name, &len);
+ if (cell == NULL) {
+ *nb = 0U;
+ return 0;
+ }
+
+ for (i = 0U; i < ((uint32_t)len / sizeof(uint32_t)); i++) {
+ tab[i] = fdt32_to_cpu(cell[i]);
+ }
+
+ *nb = (uint32_t)len / sizeof(uint32_t);
+
+ return 0;
+}
+
+#define RCC_PLL_NAME_SIZE 12
+
+static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
+{
+ int err;
+
+ err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, &pll->cfg[PLLCFG_M]);
+ if (err != 0) {
+ return err;
+ }
+
+ err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLLCSG_NB, pll->csg);
+ if (err == 0) {
+ pll->csg_enabled = true;
+ } else if (err == -FDT_ERR_NOTFOUND) {
+ pll->csg_enabled = false;
+ } else {
+ return err;
+ }
+
+ pll->status = true;
+
+ pll->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0);
+
+ pll->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX);
+
+ return 0;
+}
+
+static int clk_stm32_load_output_config(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
+{
+ int err;
+
+ err = fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", (int)PLL_DIV_PQR_NB,
+ &pll->cfg[PLLCFG_P]);
+ if (err != 0) {
+ return err;
+ }
+
+ pll->cfg[PLLCFG_O] = PQR(1, 1, 1);
+
+ return 0;
+}
+
+static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
+{
+ const fdt32_t *cuint;
+ int subnode_pll;
+ int subnode_vco;
+ int err;
+
+ cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);
+ if (cuint == NULL) {
+ /* Case of no pll is defined */
+ return 0;
+ }
+
+ subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
+ if (subnode_pll < 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ cuint = fdt_getprop(fdt, subnode_pll, "st,pll_vco", NULL);
+ if (cuint == NULL) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ subnode_vco = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
+ if (subnode_vco < 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ err = clk_stm32_load_vco_config(fdt, subnode_vco, pll);
+ if (err != 0) {
+ return err;
+ }
+
+ err = clk_stm32_load_output_config(fdt, subnode_pll, pll);
+ if (err != 0) {
+ return err;
+ }
+
+ return 0;
+}
+
+static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata)
+{
+ size_t i = 0U;
+
+ for (i = _PLL1; i < pdata->npll; i++) {
+ struct stm32_pll_dt_cfg *pll = pdata->pll + i;
+ char name[RCC_PLL_NAME_SIZE];
+ int subnode;
+ int err;
+
+ snprintf(name, sizeof(name), "st,pll@%u", i);
+
+ subnode = fdt_subnode_offset(fdt, node, name);
+ if (!fdt_check_node(subnode)) {
+ continue;
+ }
+
+ err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);
+ if (err != 0) {
+ panic();
+ }
+ }
+
+ return 0;
+}
+
+static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata)
+{
+ void *fdt = NULL;
+ int node;
+ uint32_t err;
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -ENOENT;
+ }
+
+ node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
+ if (node < 0) {
+ panic();
+ }
+
+ err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata);
+ if (err != 0) {
+ return err;
+ }
+
+ err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clkdiv", pdata->clkdiv, &pdata->nclkdiv);
+ if (err != 0) {
+ return err;
+ }
+
+ err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clksrc", pdata->clksrc, &pdata->nclksrc);
+ if (err != 0) {
+ return err;
+ }
+
+ return 0;
+}
+
int stm32mp1_clk_probe(void)
{
+ uintptr_t base = RCC_BASE;
+ int ret;
+
#if defined(IMAGE_BL32)
if (!fdt_get_rcc_secure_state()) {
mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U);
@@ -2376,6 +2823,16 @@
stm32mp1_osc_init();
+ ret = stm32_clk_parse_fdt(&stm32mp15_clock_pdata);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_stm32_init(&stm32mp15_clock_data, base);
+ if (ret != 0) {
+ return ret;
+ }
+
sync_earlyboot_clocks_state();
clk_register(&stm32mp_clk_ops);
diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c
index 379547f..69922fd 100644
--- a/drivers/st/clk/stm32mp_clkfunc.c
+++ b/drivers/st/clk/stm32mp_clkfunc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -335,6 +335,19 @@
}
/*******************************************************************************
+ * This function returns the STGEN counter value.
+ ******************************************************************************/
+static unsigned long long stm32mp_stgen_get_counter(void)
+{
+#ifdef __aarch64__
+ return mmio_read_64(STGEN_BASE + CNTCV_OFF);
+#else
+ return (((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) |
+ mmio_read_32(STGEN_BASE + CNTCVL_OFF));
+#endif
+}
+
+/*******************************************************************************
* This function configures and restores the STGEN counter depending on the
* connected clock.
******************************************************************************/
@@ -350,9 +363,11 @@
}
mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
- counter = stm32mp_stgen_get_counter() * rate / cntfid0;
- stgen_set_counter(counter);
+ if (cntfid0 != 0U) {
+ counter = stm32mp_stgen_get_counter() * rate / cntfid0;
+ stgen_set_counter(counter);
+ }
mmio_write_32(STGEN_BASE + CNTFID_OFF, rate);
mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
@@ -363,32 +378,13 @@
}
/*******************************************************************************
- * This function returns the STGEN counter value.
+ * This function restores CPU generic timer rate from the STGEN clock rate.
******************************************************************************/
-unsigned long long stm32mp_stgen_get_counter(void)
+void stm32mp_stgen_restore_rate(void)
{
-#ifdef __aarch64__
- return mmio_read_64(STGEN_BASE + CNTCV_OFF);
-#else
- return (((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) |
- mmio_read_32(STGEN_BASE + CNTCVL_OFF));
-#endif
-}
+ unsigned long rate;
-/*******************************************************************************
- * This function restores the STGEN counter value.
- * It takes a first input value as a counter backup value to be restored and a
- * offset in ms to be added.
- ******************************************************************************/
-void stm32mp_stgen_restore_counter(unsigned long long value,
- unsigned long long offset_in_ms)
-{
- unsigned long long cnt;
+ rate = mmio_read_32(STGEN_BASE + CNTFID_OFF);
- cnt = value + ((offset_in_ms *
- mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U);
-
- mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
- stgen_set_counter(cnt);
- mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
+ write_cntfrq_el0((u_register_t)rate);
}
diff --git a/fdts/dualroot_cot_descriptors.dtsi b/fdts/dualroot_cot_descriptors.dtsi
new file mode 100644
index 0000000..459a1dd
--- /dev/null
+++ b/fdts/dualroot_cot_descriptors.dtsi
@@ -0,0 +1,314 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <tools_share/dualroot_oid.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <common/nv_cntr_ids.h>
+
+cot {
+ manifests {
+ compatible = "arm, cert-descs";
+
+ trusted_boot_fw_cert: trusted_boot_fw_cert {
+ root-certificate;
+ image-id =<TRUSTED_BOOT_FW_CERT_ID>;
+ antirollback-counter = <&trusted_nv_counter>;
+
+ tb_fw_hash: tb_fw_hash {
+ oid = TRUSTED_BOOT_FW_HASH_OID;
+ };
+ tb_fw_config_hash: tb_fw_config_hash {
+ oid = TRUSTED_BOOT_FW_CONFIG_HASH_OID;
+ };
+ hw_config_hash: hw_config_hash {
+ oid = HW_CONFIG_HASH_OID;
+ };
+ fw_config_hash: fw_config_hash {
+ oid = FW_CONFIG_HASH_OID;
+ };
+ };
+
+ trusted_key_cert: trusted_key_cert {
+ root-certificate;
+ image-id = <TRUSTED_KEY_CERT_ID>;
+ antirollback-counter = <&trusted_nv_counter>;
+
+ trusted_world_pk: trusted_world_pk {
+ oid = TRUSTED_WORLD_PK_OID;
+ };
+ };
+
+ scp_fw_key_cert: scp_fw_key_cert {
+ image-id = <SCP_FW_KEY_CERT_ID>;
+ parent = <&trusted_key_cert>;
+ signing-key = <&trusted_world_pk>;
+ antirollback-counter = <&trusted_nv_counter>;
+
+ scp_fw_content_pk: scp_fw_content_pk {
+ oid = SCP_FW_CONTENT_CERT_PK_OID;
+ };
+ };
+
+ scp_fw_content_cert: scp_fw_content_cert {
+ image-id = <SCP_FW_CONTENT_CERT_ID>;
+ parent = <&scp_fw_key_cert>;
+ signing-key = <&scp_fw_content_pk>;
+ antirollback-counter = <&trusted_nv_counter>;
+
+ scp_fw_hash: scp_fw_hash {
+ oid = SCP_FW_HASH_OID;
+ };
+ };
+
+ soc_fw_key_cert: soc_fw_key_cert {
+ image-id = <SOC_FW_KEY_CERT_ID>;
+ parent = <&trusted_key_cert>;
+ signing-key = <&trusted_world_pk>;
+ antirollback-counter = <&trusted_nv_counter>;
+ soc_fw_content_pk: soc_fw_content_pk {
+ oid = SOC_FW_CONTENT_CERT_PK_OID;
+ };
+ };
+
+ soc_fw_content_cert: soc_fw_content_cert {
+ image-id = <SOC_FW_CONTENT_CERT_ID>;
+ parent = <&soc_fw_key_cert>;
+ signing-key = <&soc_fw_content_pk>;
+ antirollback-counter = <&trusted_nv_counter>;
+
+ soc_fw_hash: soc_fw_hash {
+ oid = SOC_AP_FW_HASH_OID;
+ };
+ soc_fw_config_hash: soc_fw_config_hash {
+ oid = SOC_FW_CONFIG_HASH_OID;
+ };
+ };
+
+ trusted_os_fw_key_cert: trusted_os_fw_key_cert {
+ image-id = <TRUSTED_OS_FW_KEY_CERT_ID>;
+ parent = <&trusted_key_cert>;
+ signing-key = <&trusted_world_pk>;
+ antirollback-counter = <&trusted_nv_counter>;
+
+ tos_fw_content_pk: tos_fw_content_pk {
+ oid = TRUSTED_OS_FW_CONTENT_CERT_PK_OID;
+ };
+ };
+
+ trusted_os_fw_content_cert: trusted_os_fw_content_cert {
+ image-id = <TRUSTED_OS_FW_CONTENT_CERT_ID>;
+ parent = <&trusted_os_fw_key_cert>;
+ signing-key = <&tos_fw_content_pk>;
+ antirollback-counter = <&trusted_nv_counter>;
+
+ tos_fw_hash: tos_fw_hash {
+ oid = TRUSTED_OS_FW_HASH_OID;
+ };
+ tos_fw_extra1_hash: tos_fw_extra1_hash {
+ oid = TRUSTED_OS_FW_EXTRA1_HASH_OID;
+ };
+ tos_fw_extra2_hash: tos_fw_extra2_hash {
+ oid = TRUSTED_OS_FW_EXTRA2_HASH_OID;
+ };
+ tos_fw_config_hash: tos_fw_config_hash {
+ oid = TRUSTED_OS_FW_CONFIG_HASH_OID;
+ };
+ };
+
+ non_trusted_fw_content_cert: non_trusted_fw_content_cert {
+ root-certificate;
+ image-id = <NON_TRUSTED_FW_CONTENT_CERT_ID>;
+ signing-key = <&prot_pk>;
+ antirollback-counter = <&non_trusted_nv_counter>;
+
+ nt_world_bl_hash: nt_world_bl_hash {
+ oid = NON_TRUSTED_WORLD_BOOTLOADER_HASH_OID;
+ };
+ nt_fw_config_hash: nt_fw_config_hash {
+ oid = NON_TRUSTED_FW_CONFIG_HASH_OID;
+ };
+ };
+
+#if defined(SPD_spmd)
+ sip_sp_content_cert: sip_sp_content_cert {
+ image-id = <SIP_SP_CONTENT_CERT_ID>;
+ parent = <&trusted_key_cert>;
+ signing-key = <&trusted_world_pk>;
+ antirollback-counter = <&trusted_nv_counter>;
+
+ sp_pkg1_hash: sp_pkg1_hash {
+ oid = SP_PKG1_HASH_OID;
+ };
+ sp_pkg2_hash: sp_pkg2_hash {
+ oid = SP_PKG2_HASH_OID;
+ };
+ sp_pkg3_hash: sp_pkg3_hash {
+ oid = SP_PKG3_HASH_OID;
+ };
+ sp_pkg4_hash: sp_pkg4_hash {
+ oid = SP_PKG4_HASH_OID;
+ };
+ };
+
+ plat_sp_content_cert: plat_sp_content_cert {
+ root-certificate;
+ image-id = <PLAT_SP_CONTENT_CERT_ID>;
+ signing-key = <&prot_pk>;
+ antirollback-counter = <&non_trusted_nv_counter>;
+
+ sp_pkg5_hash: sp_pkg5_hash {
+ oid = SP_PKG5_HASH_OID;
+ };
+ sp_pkg6_hash: sp_pkg6_hash {
+ oid = SP_PKG6_HASH_OID;
+ };
+ sp_pkg7_hash: sp_pkg7_hash {
+ oid = SP_PKG7_HASH_OID;
+ };
+ sp_pkg8_hash: sp_pkg8_hash {
+ oid = SP_PKG8_HASH_OID;
+ };
+ };
+#endif
+ };
+
+ images {
+ compatible = "arm, img-descs";
+
+ hw_config {
+ image-id = <HW_CONFIG_ID>;
+ parent = <&trusted_boot_fw_cert>;
+ hash = <&hw_config_hash>;
+ };
+
+ scp_bl2_image {
+ image-id = <SCP_BL2_IMAGE_ID>;
+ parent = <&scp_fw_content_cert>;
+ hash = <&scp_fw_hash>;
+ };
+
+ bl31_image {
+ image-id = <BL31_IMAGE_ID>;
+ parent = <&soc_fw_content_cert>;
+ hash = <&soc_fw_hash>;
+ };
+
+ soc_fw_config {
+ image-id = <SOC_FW_CONFIG_ID>;
+ parent = <&soc_fw_content_cert>;
+ hash = <&soc_fw_config_hash>;
+ };
+
+ bl32_image {
+ image-id = <BL32_IMAGE_ID>;
+ parent = <&trusted_os_fw_content_cert>;
+ hash = <&tos_fw_hash>;
+ };
+
+ bl32_extra1_image {
+ image-id = <BL32_EXTRA1_IMAGE_ID>;
+ parent = <&trusted_os_fw_content_cert>;
+ hash = <&tos_fw_extra1_hash>;
+ };
+
+ bl32_extra2_image {
+ image-id = <BL32_EXTRA2_IMAGE_ID>;
+ parent = <&trusted_os_fw_content_cert>;
+ hash = <&tos_fw_extra2_hash>;
+ };
+
+ tos_fw_config {
+ image-id = <TOS_FW_CONFIG_ID>;
+ parent = <&trusted_os_fw_content_cert>;
+ hash = <&tos_fw_config_hash>;
+ };
+
+ bl33_image {
+ image-id = <BL33_IMAGE_ID>;
+ parent = <&non_trusted_fw_content_cert>;
+ hash = <&nt_world_bl_hash>;
+ };
+
+ nt_fw_config {
+ image-id = <NT_FW_CONFIG_ID>;
+ parent = <&non_trusted_fw_content_cert>;
+ hash = <&nt_fw_config_hash>;
+ };
+
+#if defined(SPD_spmd)
+ sp_pkg1 {
+ image-id = <SP_PKG1_ID>;
+ parent = <&sip_sp_content_cert>;
+ hash = <&sp_pkg1_hash>;
+ };
+
+ sp_pkg2 {
+ image-id = <SP_PKG2_ID>;
+ parent = <&sip_sp_content_cert>;
+ hash = <&sp_pkg2_hash>;
+ };
+
+ sp_pkg3 {
+ image-id = <SP_PKG3_ID>;
+ parent = <&sip_sp_content_cert>;
+ hash = <&sp_pkg3_hash>;
+ };
+
+ sp_pkg4 {
+ image-id = <SP_PKG4_ID>;
+ parent = <&sip_sp_content_cert>;
+ hash = <&sp_pkg4_hash>;
+ };
+
+ sp_pkg5 {
+ image-id = <SP_PKG5_ID>;
+ parent = <&plat_sp_content_cert>;
+ hash = <&sp_pkg5_hash>;
+ };
+
+ sp_pkg6 {
+ image-id = <SP_PKG6_ID>;
+ parent = <&plat_sp_content_cert>;
+ hash = <&sp_pkg6_hash>;
+ };
+
+ sp_pkg7 {
+ image-id = <SP_PKG7_ID>;
+ parent = <&plat_sp_content_cert>;
+ hash = <&sp_pkg7_hash>;
+ };
+
+ sp_pkg8 {
+ image-id = <SP_PKG8_ID>;
+ parent = <&plat_sp_content_cert>;
+ hash = <&sp_pkg8_hash>;
+ };
+#endif
+ };
+};
+
+non_volatile_counters: non_volatile_counters {
+ compatible = "arm, non-volatile-counter";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ trusted_nv_counter: trusted_nv_counter {
+ id = <TRUSTED_NV_CTR_ID>;
+ oid = TRUSTED_FW_NVCOUNTER_OID;
+ };
+
+ non_trusted_nv_counter: non_trusted_nv_counter {
+ id = <NON_TRUSTED_NV_CTR_ID>;
+ oid = NON_TRUSTED_FW_NVCOUNTER_OID;
+ };
+};
+
+rot_keys {
+ prot_pk: prot_pk {
+ oid = PROT_PK_OID;
+ };
+};
diff --git a/fdts/stm32mp135f-dk.dts b/fdts/stm32mp135f-dk.dts
index 7a7d461..08fbbb9 100644
--- a/fdts/stm32mp135f-dk.dts
+++ b/fdts/stm32mp135f-dk.dts
@@ -190,7 +190,6 @@
CLK_AXI_PLL2P
CLK_MLAHBS_PLL3
CLK_CKPER_HSE
- CLK_RTC_LSE
CLK_SDMMC1_PLL4P
CLK_SDMMC2_PLL4P
CLK_STGEN_HSE
@@ -212,16 +211,9 @@
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_APB6, 1)
- DIV(DIV_RTC, 0)
>;
st,pll_vco {
- pll1_vco_1300Mhz: pll1-vco-1300Mhz {
- src = < CLK_PLL12_HSE >;
- divmn = < 2 80 >;
- frac = < 0x800 >;
- };
-
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
@@ -240,19 +232,6 @@
};
};
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1:st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
-
- st,pll = < &pll1_cfg1 >;
-
- pll1_cfg1: pll1_cfg1 {
- st,pll_vco = < &pll1_vco_1300Mhz >;
- st,pll_div_pqr = < 0 1 1 >;
- };
- };
-
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
pll2:st,pll@1 {
compatible = "st,stm32mp1-pll";
diff --git a/fdts/stm32mp151a-prtt1a.dts b/fdts/stm32mp151a-prtt1a.dts
index 3634620..9742dcb 100644
--- a/fdts/stm32mp151a-prtt1a.dts
+++ b/fdts/stm32mp151a-prtt1a.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023, Protonic Holland - All Rights Reserved
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
* Author: David Jander <david@protonic.nl>
*/
/dts-v1/;
@@ -123,7 +124,7 @@
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
- CLK_RNG1_LSI
+ CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts
index f0da350..7135970 100644
--- a/fdts/stm32mp157a-avenger96.dts
+++ b/fdts/stm32mp157a-avenger96.dts
@@ -175,29 +175,9 @@
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
- CLK_PLL12_HSE
- CLK_PLL3_HSE
- CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
- >;
-
- st,clkdiv = <
- 1 /*MPU*/
- 0 /*AXI*/
- 0 /*MCU*/
- 1 /*APB1*/
- 1 /*APB2*/
- 1 /*APB3*/
- 1 /*APB4*/
- 2 /*APB5*/
- 23 /*RTC*/
- 0 /*MCO1*/
- 0 /*MCO2*/
- >;
-
- st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
@@ -228,42 +208,83 @@
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
- CLK_RNG1_LSI
+ CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = <2 80 0 0 0 PQR(1,0,0)>;
- frac = <0x800>;
+ st,clkdiv = <
+ DIV(DIV_MPU, 1)
+ DIV(DIV_AXI, 0)
+ DIV(DIV_MCU, 0)
+ DIV(DIV_APB1, 1)
+ DIV(DIV_APB2, 1)
+ DIV(DIV_APB3, 1)
+ DIV(DIV_APB4, 1)
+ DIV(DIV_APB5, 2)
+ DIV(DIV_RTC, 23)
+ DIV(DIV_MCO1, 0)
+ DIV(DIV_MCO2, 0)
+ >;
+
+ st,pll_vco {
+ pll2_vco_1066Mhz: pll2-vco-1066Mhz {
+ src = <CLK_PLL12_HSE>;
+ divmn = <2 65>;
+ frac = <0x1400>;
+ };
+
+ pll3_vco_417Mhz: pll3-vco-417Mhz {
+ src = <CLK_PLL3_HSE>;
+ divmn = <1 33>;
+ frac = <0x1a04>;
+ };
+
+ pll4_vco_480Mhz: pll4-vco-480Mhz {
+ src = <CLK_PLL4_HSE>;
+ divmn = <1 39>;
+ };
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
- cfg = <2 65 1 0 0 PQR(1,1,1)>;
- frac = <0x1400>;
+
+ st,pll = <&pll2_cfg1>;
+
+ pll2_cfg1: pll2_cfg1 {
+ st,pll_vco = <&pll2_vco_1066Mhz>;
+ st,pll_div_pqr = <1 0 0>;
+ };
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
- cfg = <1 33 1 16 36 PQR(1,1,1)>;
- frac = <0x1a04>;
+
+ st,pll = <&pll3_cfg1>;
+
+ pll3_cfg1: pll3_cfg1 {
+ st,pll_vco = <&pll3_vco_417Mhz>;
+ st,pll_div_pqr = <1 16 36>;
+ };
};
/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = <1 39 3 11 4 PQR(1,1,1)>;
+
+ st,pll = <&pll4_cfg1>;
+
+ pll4_cfg1: pll4_cfg1 {
+ st,pll_vco = <&pll4_vco_480Mhz>;
+ st,pll_div_pqr = <3 11 4>;
+ };
};
};
diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index d7bcc84..d85221b 100644
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -194,29 +194,8 @@
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
- CLK_PLL12_HSE
- CLK_PLL3_HSE
- CLK_PLL4_HSE
- CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
- >;
-
- st,clkdiv = <
- 1 /*MPU*/
- 0 /*AXI*/
- 0 /*MCU*/
- 1 /*APB1*/
- 1 /*APB2*/
- 1 /*APB3*/
- 1 /*APB4*/
- 2 /*APB5*/
- 23 /*RTC*/
- 0 /*MCO1*/
- 0 /*MCO2*/
- >;
-
- st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
@@ -247,42 +226,82 @@
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
- CLK_RNG1_LSI
+ CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = <2 80 0 0 0 PQR(1,0,0)>;
- frac = <0x800>;
+ st,clkdiv = <
+ DIV(DIV_MPU, 1)
+ DIV(DIV_AXI, 0)
+ DIV(DIV_MCU, 0)
+ DIV(DIV_APB1, 1)
+ DIV(DIV_APB2, 1)
+ DIV(DIV_APB3, 1)
+ DIV(DIV_APB4, 1)
+ DIV(DIV_APB5, 2)
+ DIV(DIV_MCO1, 0)
+ DIV(DIV_MCO2, 0)
+ >;
+
+ st,pll_vco {
+ pll2_vco_1066Mhz: pll2-vco-1066Mhz {
+ src = <CLK_PLL12_HSE>;
+ divmn = <2 65>;
+ frac = <0x1400>;
+ };
+
+ pll3_vco_417Mhz: pll3-vco-417Mhz {
+ src = <CLK_PLL3_HSE>;
+ divmn = <1 33>;
+ frac = <0x1a04>;
+ };
+
+ pll4_vco_594Mhz: pll4-vco-594Mhz {
+ src = <CLK_PLL4_HSE>;
+ divmn = <3 98>;
+ };
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
- cfg = <2 65 1 0 0 PQR(1,1,1)>;
- frac = <0x1400>;
+
+ st,pll = <&pll2_cfg1>;
+
+ pll2_cfg1: pll2_cfg1 {
+ st,pll_vco = <&pll2_vco_1066Mhz>;
+ st,pll_div_pqr = <1 0 0>;
+ };
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
- cfg = <1 33 1 16 36 PQR(1,1,1)>;
- frac = <0x1a04>;
+
+ st,pll = <&pll3_cfg1>;
+
+ pll3_cfg1: pll3_cfg1 {
+ st,pll_vco = <&pll3_vco_417Mhz>;
+ st,pll_div_pqr = <1 16 36>;
+ };
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = <3 98 5 7 7 PQR(1,1,1)>;
+
+ st,pll = <&pll4_cfg1>;
+
+ pll4_cfg1: pll4_cfg1 {
+ st,pll_vco = <&pll4_vco_594Mhz>;
+ st,pll_div_pqr = <5 7 7>;
+ };
};
};
diff --git a/fdts/stm32mp157c-odyssey-som.dtsi b/fdts/stm32mp157c-odyssey-som.dtsi
index a0be718..e5d41fc 100644
--- a/fdts/stm32mp157c-odyssey-som.dtsi
+++ b/fdts/stm32mp157c-odyssey-som.dtsi
@@ -207,29 +207,9 @@
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
- CLK_PLL12_HSE
- CLK_PLL3_HSE
- CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
- >;
-
- st,clkdiv = <
- 1 /*MPU*/
- 0 /*AXI*/
- 0 /*MCU*/
- 1 /*APB1*/
- 1 /*APB2*/
- 1 /*APB3*/
- 1 /*APB4*/
- 2 /*APB5*/
- 23 /*RTC*/
- 0 /*MCO1*/
- 0 /*MCO2*/
- >;
-
- st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
@@ -260,42 +240,83 @@
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
- CLK_RNG1_LSI
+ CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = <2 80 0 0 0 PQR(1,0,0)>;
- frac = <0x800>;
+ st,clkdiv = <
+ DIV(DIV_MPU, 1)
+ DIV(DIV_AXI, 0)
+ DIV(DIV_MCU, 0)
+ DIV(DIV_APB1, 1)
+ DIV(DIV_APB2, 1)
+ DIV(DIV_APB3, 1)
+ DIV(DIV_APB4, 1)
+ DIV(DIV_APB5, 2)
+ DIV(DIV_RTC, 23)
+ DIV(DIV_MCO1, 0)
+ DIV(DIV_MCO2, 0)
+ >;
+
+ st,pll_vco {
+ pll2_vco_1066Mhz: pll2-vco-1066Mhz {
+ src = <CLK_PLL12_HSE>;
+ divmn = <2 65>;
+ frac = <0x1400>;
+ };
+
+ pll3_vco_417Mhz: pll3-vco-417Mhz {
+ src = <CLK_PLL3_HSE>;
+ divmn = <1 33>;
+ frac = <0x1a04>;
+ };
+
+ pll4_vco_594Mhz: pll4-vco-594Mhz {
+ src = <CLK_PLL4_HSE>;
+ divmn = <3 98>;
+ };
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
- cfg = <2 65 1 0 0 PQR(1,1,1)>;
- frac = <0x1400>;
+
+ st,pll = <&pll2_cfg1>;
+
+ pll2_cfg1: pll2_cfg1 {
+ st,pll_vco = <&pll2_vco_1066Mhz>;
+ st,pll_div_pqr = <1 0 0>;
+ };
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
- cfg = <1 33 1 16 36 PQR(1,1,1)>;
- frac = <0x1a04>;
+
+ st,pll = <&pll3_cfg1>;
+
+ pll3_cfg1: pll3_cfg1 {
+ st,pll_vco = <&pll3_vco_417Mhz>;
+ st,pll_div_pqr = <1 16 36>;
+ };
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = <3 98 5 7 7 PQR(1,1,1)>;
+
+ st,pll = <&pll4_cfg1>;
+
+ pll4_cfg1: pll4_cfg1 {
+ st,pll_vco = <&pll4_vco_594Mhz>;
+ st,pll_div_pqr = <5 7 7>;
+ };
};
};
diff --git a/fdts/stm32mp15xx-dhcom-som.dtsi b/fdts/stm32mp15xx-dhcom-som.dtsi
index 5138868..12846db 100644
--- a/fdts/stm32mp15xx-dhcom-som.dtsi
+++ b/fdts/stm32mp15xx-dhcom-som.dtsi
@@ -193,29 +193,9 @@
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
- CLK_PLL12_HSE
- CLK_PLL3_HSE
- CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_PLL4P
- >;
-
- st,clkdiv = <
- 1 /*MPU*/
- 0 /*AXI*/
- 0 /*MCU*/
- 1 /*APB1*/
- 1 /*APB2*/
- 1 /*APB3*/
- 1 /*APB4*/
- 2 /*APB5*/
- 23 /*RTC*/
- 0 /*MCO1*/
- 1 /*MCO2*/
- >;
-
- st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
@@ -246,42 +226,83 @@
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
- CLK_RNG1_LSI
+ CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = <2 80 0 0 0 PQR(1,0,0)>;
- frac = <0x800>;
+ st,clkdiv = <
+ DIV(DIV_MPU, 1)
+ DIV(DIV_AXI, 0)
+ DIV(DIV_MCU, 0)
+ DIV(DIV_APB1, 1)
+ DIV(DIV_APB2, 1)
+ DIV(DIV_APB3, 1)
+ DIV(DIV_APB4, 1)
+ DIV(DIV_APB5, 2)
+ DIV(DIV_RTC, 23)
+ DIV(DIV_MCO1, 0)
+ DIV(DIV_MCO2, 1)
+ >;
+
+ st,pll_vco {
+ pll2_vco_1066Mhz: pll2-vco-1066Mhz {
+ src = <CLK_PLL12_HSE>;
+ divmn = <2 65>;
+ frac = <0x1400>;
+ };
+
+ pll3_vco_417Mhz: pll3-vco-417Mhz {
+ src = <CLK_PLL3_HSE>;
+ divmn = <1 33>;
+ frac = <0x1a04>;
+ };
+
+ pll4_vco_600Mhz: pll4-vco-600hz {
+ src = <CLK_PLL4_HSE>;
+ divmn = <1 49>;
+ };
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
- cfg = <2 65 1 0 0 PQR(1,1,1)>;
- frac = <0x1400>;
+
+ st,pll = <&pll2_cfg1>;
+
+ pll2_cfg1: pll2_cfg1 {
+ st,pll_vco = <&pll2_vco_1066Mhz>;
+ st,pll_div_pqr = <1 0 0>;
+ };
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
- cfg = <1 33 1 16 36 PQR(1,1,1)>;
- frac = <0x1a04>;
+
+ st,pll = <&pll3_cfg1>;
+
+ pll3_cfg1: pll3_cfg1 {
+ st,pll_vco = <&pll3_vco_417Mhz>;
+ st,pll_div_pqr = <1 16 36>;
+ };
};
/* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = <1 49 5 11 11 PQR(1,1,1)>;
+
+ st,pll = <&pll4_cfg1>;
+
+ pll4_cfg1: pll4_cfg1 {
+ st,pll_vco = <&pll4_vco_600Mhz>;
+ st,pll_div_pqr = <5 11 11>;
+ };
};
};
diff --git a/fdts/stm32mp15xx-dhcor-som.dtsi b/fdts/stm32mp15xx-dhcor-som.dtsi
index 8d829a4..2ebfb2d 100644
--- a/fdts/stm32mp15xx-dhcor-som.dtsi
+++ b/fdts/stm32mp15xx-dhcor-som.dtsi
@@ -4,7 +4,7 @@
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
* Copyright (C) 2022 DH electronics GmbH
- * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
*/
#include "stm32mp15-pinctrl.dtsi"
@@ -188,29 +188,9 @@
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
- CLK_PLL12_HSE
- CLK_PLL3_HSE
- CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
- >;
-
- st,clkdiv = <
- 1 /*MPU*/
- 0 /*AXI*/
- 0 /*MCU*/
- 1 /*APB1*/
- 1 /*APB2*/
- 1 /*APB3*/
- 1 /*APB4*/
- 2 /*APB5*/
- 23 /*RTC*/
- 0 /*MCO1*/
- 0 /*MCO2*/
- >;
-
- st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
@@ -241,42 +221,84 @@
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
- CLK_RNG1_LSI
+ CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = <2 80 0 0 0 PQR(1,0,0)>;
- frac = <0x800>;
+ st,clkdiv = <
+ DIV(DIV_MPU, 1)
+ DIV(DIV_AXI, 0)
+ DIV(DIV_MCU, 0)
+ DIV(DIV_APB1, 1)
+ DIV(DIV_APB2, 1)
+ DIV(DIV_APB3, 1)
+ DIV(DIV_APB4, 1)
+ DIV(DIV_APB5, 2)
+ DIV(DIV_RTC, 23)
+ DIV(DIV_MCO1, 0)
+ DIV(DIV_MCO2, 0)
+ >;
+
+ st,pll_vco {
+ pll2_vco_1066Mhz: pll2-vco-1066Mhz {
+ src = <CLK_PLL12_HSE>;
+ divmn = <2 65>;
+ frac = <0x1400>;
+ };
+
+ pll3_vco_417Mhz: pll3-vco-417Mhz {
+ src = <CLK_PLL3_HSE>;
+ divmn = <1 33>;
+ frac = <0x1a04>;
+ };
+
+ pll4_vco_594Mhz: pll4-vco-594Mhz {
+ src = <CLK_PLL4_HSE>;
+ divmn = <3 98>;
+ };
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
- cfg = <2 65 1 0 0 PQR(1,1,1)>;
- frac = <0x1400>;
+
+ st,pll = <&pll2_cfg1>;
+
+ pll2_cfg1: pll2_cfg1 {
+ st,pll_vco = <&pll2_vco_1066Mhz>;
+ st,pll_div_pqr = <1 0 0>;
+ };
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
- cfg = <1 33 1 16 36 PQR(1,1,1)>;
- frac = <0x1a04>;
+
+ st,pll = <&pll3_cfg1>;
+
+ pll3_cfg1: pll3_cfg1 {
+ st,pll_vco = <&pll3_vco_417Mhz>;
+ st,pll_div_pqr = <1 16 36>;
+ };
};
- /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
+ /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */ /* @TOCHECK */
+ /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = <3 98 5 7 5 PQR(1,1,1)>;
+
+ st,pll = <&pll4_cfg1>;
+
+ pll4_cfg1: pll4_cfg1 {
+ st,pll_vco = <&pll4_vco_594Mhz>;
+ st,pll_div_pqr = <5 7 7>;
+ };
};
};
diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi
index d8b7c48..bac9e05 100644
--- a/fdts/stm32mp15xx-dkx.dtsi
+++ b/fdts/stm32mp15xx-dkx.dtsi
@@ -198,29 +198,8 @@
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
- CLK_PLL12_HSE
- CLK_PLL3_HSE
- CLK_PLL4_HSE
- CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
- >;
-
- st,clkdiv = <
- 1 /*MPU*/
- 0 /*AXI*/
- 0 /*MCU*/
- 1 /*APB1*/
- 1 /*APB2*/
- 1 /*APB3*/
- 1 /*APB4*/
- 2 /*APB5*/
- 23 /*RTC*/
- 0 /*MCO1*/
- 0 /*MCO2*/
- >;
-
- st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
@@ -251,42 +230,82 @@
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
- CLK_RNG1_LSI
+ CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
- frac = < 0x800 >;
+ st,clkdiv = <
+ DIV(DIV_MPU, 1)
+ DIV(DIV_AXI, 0)
+ DIV(DIV_MCU, 0)
+ DIV(DIV_APB1, 1)
+ DIV(DIV_APB2, 1)
+ DIV(DIV_APB3, 1)
+ DIV(DIV_APB4, 1)
+ DIV(DIV_APB5, 2)
+ DIV(DIV_MCO1, 0)
+ DIV(DIV_MCO2, 0)
+ >;
+
+ st,pll_vco {
+ pll2_vco_1066Mhz: pll2-vco-1066Mhz {
+ src = <CLK_PLL12_HSE>;
+ divmn = <2 65>;
+ frac = <0x1400>;
+ };
+
+ pll3_vco_417Mhz: pll3-vco-417Mhz {
+ src = <CLK_PLL3_HSE>;
+ divmn = <1 33>;
+ frac = <0x1a04>;
+ };
+
+ pll4_vco_594Mhz: pll4-vco-594Mhz {
+ src = <CLK_PLL4_HSE>;
+ divmn = <3 98>;
+ };
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
- cfg = <2 65 1 0 0 PQR(1,1,1)>;
- frac = <0x1400>;
+
+ st,pll = <&pll2_cfg1>;
+
+ pll2_cfg1: pll2_cfg1 {
+ st,pll_vco = <&pll2_vco_1066Mhz>;
+ st,pll_div_pqr = <1 0 0>;
+ };
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
- cfg = <1 33 1 16 36 PQR(1,1,1)>;
- frac = <0x1a04>;
+
+ st,pll = <&pll3_cfg1>;
+
+ pll3_cfg1: pll3_cfg1 {
+ st,pll_vco = <&pll3_vco_417Mhz>;
+ st,pll_div_pqr = <1 16 36>;
+ };
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = <3 98 5 7 7 PQR(1,1,1)>;
+
+ st,pll = <&pll4_cfg1>;
+
+ pll4_cfg1: pll4_cfg1 {
+ st,pll_vco = <&pll4_vco_594Mhz>;
+ st,pll_div_pqr = <5 7 7>;
+ };
};
};
diff --git a/fdts/stm32mp15xx-osd32.dtsi b/fdts/stm32mp15xx-osd32.dtsi
index ef4c3c0..6e27b41 100644
--- a/fdts/stm32mp15xx-osd32.dtsi
+++ b/fdts/stm32mp15xx-osd32.dtsi
@@ -185,29 +185,9 @@
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
- CLK_PLL12_HSE
- CLK_PLL3_HSE
- CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
- >;
-
- st,clkdiv = <
- 1 /*MPU*/
- 0 /*AXI*/
- 0 /*MCU*/
- 1 /*APB1*/
- 1 /*APB2*/
- 1 /*APB3*/
- 1 /*APB4*/
- 2 /*APB5*/
- 23 /*RTC*/
- 0 /*MCO1*/
- 0 /*MCO2*/
- >;
-
- st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
@@ -238,41 +218,82 @@
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
- CLK_RNG1_LSI
+ CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
- frac = < 0x800 >;
+ st,clkdiv = <
+ DIV(DIV_MPU, 1)
+ DIV(DIV_AXI, 0)
+ DIV(DIV_MCU, 0)
+ DIV(DIV_APB1, 1)
+ DIV(DIV_APB2, 1)
+ DIV(DIV_APB3, 1)
+ DIV(DIV_APB4, 1)
+ DIV(DIV_APB5, 2)
+ DIV(DIV_RTC, 23)
+ DIV(DIV_MCO1, 0)
+ DIV(DIV_MCO2, 0)
+ >;
+
+ st,pll_vco {
+ pll2_vco_1066Mhz: pll2-vco-1066Mhz {
+ src = <CLK_PLL12_HSE>;
+ divmn = <2 65>;
+ frac = <0x1400>;
+ };
+
+ pll3_vco_417Mhz: pll3-vco-417Mhz {
+ src = <CLK_PLL3_HSE>;
+ divmn = <1 33>;
+ frac = <0x1a04>;
+ };
+
+ pll4_vco_594Mhz: pll4-vco-594Mhz {
+ src = <CLK_PLL4_HSE>;
+ divmn = <3 98>;
+ };
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
- cfg = <2 65 1 0 0 PQR(1,1,1)>;
- frac = <0x1400>;
+
+ st,pll = <&pll2_cfg1>;
+
+ pll2_cfg1: pll2_cfg1 {
+ st,pll_vco = <&pll2_vco_1066Mhz>;
+ st,pll_div_pqr = <1 0 0>;
+ };
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
- cfg = <1 33 1 16 36 PQR(1,1,1)>;
- frac = <0x1a04>;
+
+ st,pll = <&pll3_cfg1>;
+
+ pll3_cfg1: pll3_cfg1 {
+ st,pll_vco = <&pll3_vco_417Mhz>;
+ st,pll_div_pqr = <1 16 36>;
+ };
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = <3 98 5 7 7 PQR(1,1,1)>;
+
+ st,pll = <&pll4_cfg1>;
+
+ pll4_cfg1: pll4_cfg1 {
+ st,pll_vco = <&pll4_vco_594Mhz>;
+ st,pll_div_pqr = <5 7 7>;
+ };
};
};
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index fe6a695..f900eaf 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -72,6 +72,26 @@
<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
+ cs-pmu@0 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
+ };
+
+ cs-pmu@1 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
+ };
+
+ cs-pmu@2 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
+ };
+
+ cs-pmu@3 {
+ compatible = "arm,coresight-pmu";
+ reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
+ };
+
sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";
diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h
index 61286b2..8fd5ed1 100644
--- a/include/drivers/st/stm32mp_clkfunc.h
+++ b/include/drivers/st/stm32mp_clkfunc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,8 +29,6 @@
unsigned long fdt_get_uart_clock_freq(uintptr_t instance);
void stm32mp_stgen_config(unsigned long rate);
-void stm32mp_stgen_restore_counter(unsigned long long value,
- unsigned long long offset_in_ms);
-unsigned long long stm32mp_stgen_get_counter(void);
+void stm32mp_stgen_restore_rate(void);
#endif /* STM32MP_CLKFUNC_H */
diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h
index 1d5bb78..031e432 100644
--- a/include/dt-bindings/clock/stm32mp13-clks.h
+++ b/include/dt-bindings/clock/stm32mp13-clks.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */
/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Copyright (C) STMicroelectronics 2022-2024 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
@@ -193,7 +193,13 @@
#define SAI1 160
#define SAI2 161
-#define STM32MP1_LAST_CLK 162
+#define SPI1 162
+#define SPI2 163
+#define SPI3 164
+#define SPI4 165
+#define SPI5 166
+
+#define STM32MP1_LAST_CLK 167
/* SCMI clock identifiers */
#define CK_SCMI0_HSE 0
diff --git a/include/dt-bindings/clock/stm32mp15-clksrc.h b/include/dt-bindings/clock/stm32mp15-clksrc.h
index 3a3792d..e601b48 100644
--- a/include/dt-bindings/clock/stm32mp15-clksrc.h
+++ b/include/dt-bindings/clock/stm32mp15-clksrc.h
@@ -1,273 +1,413 @@
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
- * Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2017-2024, STMicroelectronics - All Rights Reserved
*/
#ifndef _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_
#define _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_
+#include <lib/utils_def.h>
+
+#define CMD_DIV 0
+#define CMD_MUX 1
+#define CMD_CLK 2
+
+#define CMD_ADDR_BIT BIT(31)
+
+#define CMD_SHIFT 26
+#define CMD_MASK GENMASK_32(31, 26)
+#define CMD_DATA_MASK GENMASK_32(25, 0)
+
+#define DIV_ID_SHIFT 8
+#define DIV_ID_MASK GENMASK_32(15, 8)
+
+#define DIV_DIVN_SHIFT 0
+#define DIV_DIVN_MASK GENMASK_32(7, 0)
+
+#define MUX_ID_SHIFT 4
+#define MUX_ID_MASK GENMASK_32(11, 4)
+
+#define MUX_SEL_SHIFT 0
+#define MUX_SEL_MASK GENMASK_32(3, 0)
+
+#define CLK_ID_MASK GENMASK_32(19, 11)
+#define CLK_ID_SHIFT 11
+#define CLK_ON_MASK 0x00000400
+#define CLK_ON_SHIFT 10
+#define CLK_DIV_MASK GENMASK_32(9, 4)
+#define CLK_DIV_SHIFT 4
+#define CLK_SEL_MASK GENMASK_32(3, 0)
+#define CLK_SEL_SHIFT 0
+
+#define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\
+ ((div_id) << DIV_ID_SHIFT) |\
+ (div))
+
+#define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\
+ ((mux_id) << MUX_ID_SHIFT) |\
+ (sel))
+
+/* CLK output is enable */
+#define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\
+ ((clk_id) << CLK_ID_SHIFT) |\
+ (sel) | CLK_ON_MASK)
+
+#define CLK_DISABLED(clk_id) ((CMD_CLK << CMD_SHIFT) |\
+ ((clk_id) << CLK_ID_SHIFT))
+
+#define CLK_ADDR_SHIFT 16
+#define CLK_ADDR_MASK GENMASK_32(30, 16)
+#define CLK_ADDR_VAL_MASK GENMASK_32(15, 0)
+
+#define DIV_PLL1DIVP 0
+#define DIV_PLL2DIVP 1
+#define DIV_PLL2DIVQ 2
+#define DIV_PLL2DIVR 3
+#define DIV_PLL3DIVP 4
+#define DIV_PLL3DIVQ 5
+#define DIV_PLL3DIVR 6
+#define DIV_PLL4DIVP 7
+#define DIV_PLL4DIVQ 8
+#define DIV_PLL4DIVR 9
+#define DIV_MPU 10
+#define DIV_AXI 11
+#define DIV_MCU 12
+#define DIV_APB1 13
+#define DIV_APB2 14
+#define DIV_APB3 15
+#define DIV_APB4 16
+#define DIV_APB5 17
+#define DIV_RTC 19
+#define DIV_MCO1 20
+#define DIV_MCO2 21
+#define DIV_HSI 22
+#define DIV_TRACE 23
+#define DIV_ETHPTP 24
+#define DIV_NB 25
+
+#define MUX_MPU 0
+#define MUX_AXI 1
+#define MUX_MCU 2
+#define MUX_PLL12 3
+#define MUX_PLL3 4
+#define MUX_PLL4 5
+#define MUX_CKPER 6
+#define MUX_RTC 7
+#define MUX_SDMMC12 8
+#define MUX_SDMMC3 9
+#define MUX_FMC 10
+#define MUX_QSPI 11
+#define MUX_RNG1 12
+#define MUX_RNG2 13
+#define MUX_USBPHY 14
+#define MUX_USBO 15
+#define MUX_STGEN 16
+#define MUX_SPDIF 17
+#define MUX_SPI2S1 18
+#define MUX_SPI2S23 19
+#define MUX_SPI45 20
+#define MUX_SPI6 21
+#define MUX_CEC 22
+#define MUX_I2C12 23
+#define MUX_I2C35 24
+#define MUX_I2C46 25
+#define MUX_LPTIM1 26
+#define MUX_LPTIM23 27
+#define MUX_LPTIM45 28
+#define MUX_UART1 29
+#define MUX_UART24 30
+#define MUX_UART35 31
+#define MUX_UART6 32
+#define MUX_UART78 33
+#define MUX_SAI1 34
+#define MUX_SAI2 35
+#define MUX_SAI3 36
+#define MUX_SAI4 37
+#define MUX_DSI 38
+#define MUX_FDCAN 39
+#define MUX_ADC 40
+#define MUX_ETH 41
+#define MUX_MCO1 42
+#define MUX_MCO2 43
+#define MUX_NB 44
+
/* PLL output is enable when x=1, with x=p,q or r */
#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
+/* st,clksrc: clock sources */
+#define CLK_MPU_HSI CLKSRC(MUX_MPU, 0)
+#define CLK_MPU_HSE CLKSRC(MUX_MPU, 1)
+#define CLK_MPU_PLL1P CLKSRC(MUX_MPU, 2)
+#define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3)
+
-/* st,clksrc: mandatory clock source */
-#define CLK_MPU_HSI 0x00000200
-#define CLK_MPU_HSE 0x00000201
-#define CLK_MPU_PLL1P 0x00000202
-#define CLK_MPU_PLL1P_DIV 0x00000203
+#define CLK_AXI_HSI CLKSRC(MUX_AXI, 0)
+#define CLK_AXI_HSE CLKSRC(MUX_AXI, 1)
+#define CLK_AXI_PLL2P CLKSRC(MUX_AXI, 2)
-#define CLK_AXI_HSI 0x00000240
-#define CLK_AXI_HSE 0x00000241
-#define CLK_AXI_PLL2P 0x00000242
+#define CLK_MCU_HSI CLKSRC(MUX_MCU, 0)
+#define CLK_MCU_HSE CLKSRC(MUX_MCU, 1)
+#define CLK_MCU_CSI CLKSRC(MUX_MCU, 2)
+#define CLK_MCU_PLL3P CLKSRC(MUX_MCU, 3)
-#define CLK_MCU_HSI 0x00000480
-#define CLK_MCU_HSE 0x00000481
-#define CLK_MCU_CSI 0x00000482
-#define CLK_MCU_PLL3P 0x00000483
+#define CLK_PLL12_HSI CLKSRC(MUX_PLL12, 0)
+#define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1)
-#define CLK_PLL12_HSI 0x00000280
-#define CLK_PLL12_HSE 0x00000281
+#define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0)
+#define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1)
+#define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2)
-#define CLK_PLL3_HSI 0x00008200
-#define CLK_PLL3_HSE 0x00008201
-#define CLK_PLL3_CSI 0x00008202
+#define CLK_PLL4_HSI CLKSRC(MUX_PLL4, 0)
+#define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1)
+#define CLK_PLL4_CSI CLKSRC(MUX_PLL4, 2)
+#define CLK_PLL4_I2SCKIN CLKSRC(MUX_PLL4, 3)
-#define CLK_PLL4_HSI 0x00008240
-#define CLK_PLL4_HSE 0x00008241
-#define CLK_PLL4_CSI 0x00008242
-#define CLK_PLL4_I2SCKIN 0x00008243
+#define CLK_RTC_DISABLED CLK_DISABLED(RTC)
+#define CLK_RTC_LSE CLK_SRC(RTC, 1)
+#define CLK_RTC_LSI CLK_SRC(RTC, 2)
+#define CLK_RTC_HSE CLK_SRC(RTC, 3)
-#define CLK_RTC_DISABLED 0x00001400
-#define CLK_RTC_LSE 0x00001401
-#define CLK_RTC_LSI 0x00001402
-#define CLK_RTC_HSE 0x00001403
+/* Register addresses of MCO1 & MCO2 */
+#define MCO1 0x800
+#define MCO2 0x804
-#define CLK_MCO1_HSI 0x00008000
-#define CLK_MCO1_HSE 0x00008001
-#define CLK_MCO1_CSI 0x00008002
-#define CLK_MCO1_LSI 0x00008003
-#define CLK_MCO1_LSE 0x00008004
-#define CLK_MCO1_DISABLED 0x0000800F
+#define MCO_OFF 0
+#define MCO_ON 1
+#define MCO_STATUS_SHIFT 12
-#define CLK_MCO2_MPU 0x00008040
-#define CLK_MCO2_AXI 0x00008041
-#define CLK_MCO2_MCU 0x00008042
-#define CLK_MCO2_PLL4P 0x00008043
-#define CLK_MCO2_HSE 0x00008044
-#define CLK_MCO2_HSI 0x00008045
-#define CLK_MCO2_DISABLED 0x0000804F
+#define MCO_ON_CFG(addr, sel) (CMD_ADDR_BIT |\
+ ((addr) << CLK_ADDR_SHIFT) |\
+ (MCO_ON << MCO_STATUS_SHIFT) |\
+ (sel))
-/* st,pkcs: peripheral kernel clock source */
+#define MCO_OFF_CFG(addr) (CMD_ADDR_BIT |\
+ ((addr) << CLK_ADDR_SHIFT) |\
+ (MCO_OFF << MCO_STATUS_SHIFT))
-#define CLK_I2C12_PCLK1 0x00008C00
-#define CLK_I2C12_PLL4R 0x00008C01
-#define CLK_I2C12_HSI 0x00008C02
-#define CLK_I2C12_CSI 0x00008C03
-#define CLK_I2C12_DISABLED 0x00008C07
+#define CLK_MCO1_HSI MCO_ON_CFG(MCO1, 0)
+#define CLK_MCO1_HSE MCO_ON_CFG(MCO1, 1)
+#define CLK_MCO1_CSI MCO_ON_CFG(MCO1, 2)
+#define CLK_MCO1_LSI MCO_ON_CFG(MCO1, 3)
+#define CLK_MCO1_LSE MCO_ON_CFG(MCO1, 4)
+#define CLK_MCO1_DISABLED MCO_OFF_CFG(MCO1)
-#define CLK_I2C35_PCLK1 0x00008C40
-#define CLK_I2C35_PLL4R 0x00008C41
-#define CLK_I2C35_HSI 0x00008C42
-#define CLK_I2C35_CSI 0x00008C43
-#define CLK_I2C35_DISABLED 0x00008C47
+#define CLK_MCO2_MPU MCO_ON_CFG(MCO2, 0)
+#define CLK_MCO2_AXI MCO_ON_CFG(MCO2, 1)
+#define CLK_MCO2_MCU MCO_ON_CFG(MCO2, 2)
+#define CLK_MCO2_PLL4 MCO_ON_CFG(MCO2, 3)
+#define CLK_MCO2_HSE MCO_ON_CFG(MCO2, 4)
+#define CLK_MCO2_HSI MCO_ON_CFG(MCO2, 5)
+#define CLK_MCO2_DISABLED MCO_OFF_CFG(MCO2)
-#define CLK_I2C46_PCLK5 0x00000C00
-#define CLK_I2C46_PLL3Q 0x00000C01
-#define CLK_I2C46_HSI 0x00000C02
-#define CLK_I2C46_CSI 0x00000C03
-#define CLK_I2C46_DISABLED 0x00000C07
+#define CLK_I2C12_PCLK1 CLKSRC(MUX_I2C12, 0)
+#define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1)
+#define CLK_I2C12_HSI CLKSRC(MUX_I2C12, 2)
+#define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3)
+#define CLK_I2C12_DISABLED CLKSRC(MUX_I2C12, 7)
-#define CLK_SAI1_PLL4Q 0x00008C80
-#define CLK_SAI1_PLL3Q 0x00008C81
-#define CLK_SAI1_I2SCKIN 0x00008C82
-#define CLK_SAI1_CKPER 0x00008C83
-#define CLK_SAI1_PLL3R 0x00008C84
-#define CLK_SAI1_DISABLED 0x00008C87
+#define CLK_I2C35_PCLK1 CLKSRC(MUX_I2C35, 0)
+#define CLK_I2C35_PLL4R CLKSRC(MUX_I2C35, 1)
+#define CLK_I2C35_HSI CLKSRC(MUX_I2C35, 2)
+#define CLK_I2C35_CSI CLKSRC(MUX_I2C35, 3)
+#define CLK_I2C35_DISABLED CLKSRC(MUX_I2C35, 7)
-#define CLK_SAI2_PLL4Q 0x00008CC0
-#define CLK_SAI2_PLL3Q 0x00008CC1
-#define CLK_SAI2_I2SCKIN 0x00008CC2
-#define CLK_SAI2_CKPER 0x00008CC3
-#define CLK_SAI2_SPDIF 0x00008CC4
-#define CLK_SAI2_PLL3R 0x00008CC5
-#define CLK_SAI2_DISABLED 0x00008CC7
+#define CLK_I2C46_PCLK5 CLKSRC(MUX_I2C46, 0)
+#define CLK_I2C46_PLL3Q CLKSRC(MUX_I2C46, 1)
+#define CLK_I2C46_HSI CLKSRC(MUX_I2C46, 2)
+#define CLK_I2C46_CSI CLKSRC(MUX_I2C46, 3)
+#define CLK_I2C46_DISABLED CLKSRC(MUX_I2C46, 7)
-#define CLK_SAI3_PLL4Q 0x00008D00
-#define CLK_SAI3_PLL3Q 0x00008D01
-#define CLK_SAI3_I2SCKIN 0x00008D02
-#define CLK_SAI3_CKPER 0x00008D03
-#define CLK_SAI3_PLL3R 0x00008D04
-#define CLK_SAI3_DISABLED 0x00008D07
+#define CLK_SAI1_PLL4Q CLKSRC(MUX_SAI1, 0)
+#define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1)
+#define CLK_SAI1_I2SCKIN CLKSRC(MUX_SAI1, 2)
+#define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3)
+#define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4)
+#define CLK_SAI1_DISABLED CLKSRC(MUX_SAI1, 7)
-#define CLK_SAI4_PLL4Q 0x00008D40
-#define CLK_SAI4_PLL3Q 0x00008D41
-#define CLK_SAI4_I2SCKIN 0x00008D42
-#define CLK_SAI4_CKPER 0x00008D43
-#define CLK_SAI4_PLL3R 0x00008D44
-#define CLK_SAI4_DISABLED 0x00008D47
+#define CLK_SAI2_PLL4Q CLKSRC(MUX_SAI2, 0)
+#define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1)
+#define CLK_SAI2_I2SCKIN CLKSRC(MUX_SAI2, 2)
+#define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3)
+#define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4)
+#define CLK_SAI2_PLL3R CLKSRC(MUX_SAI2, 5)
+#define CLK_SAI2_DISABLED CLKSRC(MUX_SAI2, 7)
-#define CLK_SPI2S1_PLL4P 0x00008D80
-#define CLK_SPI2S1_PLL3Q 0x00008D81
-#define CLK_SPI2S1_I2SCKIN 0x00008D82
-#define CLK_SPI2S1_CKPER 0x00008D83
-#define CLK_SPI2S1_PLL3R 0x00008D84
-#define CLK_SPI2S1_DISABLED 0x00008D87
+#define CLK_SAI3_PLL4Q CLKSRC(MUX_SAI3, 0)
+#define CLK_SAI3_PLL3Q CLKSRC(MUX_SAI3, 1)
+#define CLK_SAI3_I2SCKIN CLKSRC(MUX_SAI3, 2)
+#define CLK_SAI3_CKPER CLKSRC(MUX_SAI3, 3)
+#define CLK_SAI3_PLL3R CLKSRC(MUX_SAI3, 4)
+#define CLK_SAI3_DISABLED CLKSRC(MUX_SAI3, 7)
-#define CLK_SPI2S23_PLL4P 0x00008DC0
-#define CLK_SPI2S23_PLL3Q 0x00008DC1
-#define CLK_SPI2S23_I2SCKIN 0x00008DC2
-#define CLK_SPI2S23_CKPER 0x00008DC3
-#define CLK_SPI2S23_PLL3R 0x00008DC4
-#define CLK_SPI2S23_DISABLED 0x00008DC7
+#define CLK_SAI4_PLL4Q CLKSRC(MUX_SAI4, 0)
+#define CLK_SAI4_PLL3Q CLKSRC(MUX_SAI4, 1)
+#define CLK_SAI4_I2SCKIN CLKSRC(MUX_SAI4, 2)
+#define CLK_SAI4_CKPER CLKSRC(MUX_SAI4, 3)
+#define CLK_SAI4_PLL3R CLKSRC(MUX_SAI4, 4)
+#define CLK_SAI4_DISABLED CLKSRC(MUX_SAI4, 7)
-#define CLK_SPI45_PCLK2 0x00008E00
-#define CLK_SPI45_PLL4Q 0x00008E01
-#define CLK_SPI45_HSI 0x00008E02
-#define CLK_SPI45_CSI 0x00008E03
-#define CLK_SPI45_HSE 0x00008E04
-#define CLK_SPI45_DISABLED 0x00008E07
+#define CLK_SPI2S1_PLL4P CLKSRC(MUX_SPI2S1, 0)
+#define CLK_SPI2S1_PLL3Q CLKSRC(MUX_SPI2S1, 1)
+#define CLK_SPI2S1_I2SCKIN CLKSRC(MUX_SPI2S1, 2)
+#define CLK_SPI2S1_CKPER CLKSRC(MUX_SPI2S1, 3)
+#define CLK_SPI2S1_PLL3R CLKSRC(MUX_SPI2S1, 4)
+#define CLK_SPI2S1_DISABLED CLKSRC(MUX_SPI2S1, 7)
-#define CLK_SPI6_PCLK5 0x00000C40
-#define CLK_SPI6_PLL4Q 0x00000C41
-#define CLK_SPI6_HSI 0x00000C42
-#define CLK_SPI6_CSI 0x00000C43
-#define CLK_SPI6_HSE 0x00000C44
-#define CLK_SPI6_PLL3Q 0x00000C45
-#define CLK_SPI6_DISABLED 0x00000C47
+#define CLK_SPI2S23_PLL4P CLKSRC(MUX_SPI2S23, 0)
+#define CLK_SPI2S23_PLL3Q CLKSRC(MUX_SPI2S23, 1)
+#define CLK_SPI2S23_I2SCKIN CLKSRC(MUX_SPI2S23, 2)
+#define CLK_SPI2S23_CKPER CLKSRC(MUX_SPI2S23, 3)
+#define CLK_SPI2S23_PLL3R CLKSRC(MUX_SPI2S23, 4)
+#define CLK_SPI2S23_DISABLED CLKSRC(MUX_SPI2S23, 7)
-#define CLK_UART6_PCLK2 0x00008E40
-#define CLK_UART6_PLL4Q 0x00008E41
-#define CLK_UART6_HSI 0x00008E42
-#define CLK_UART6_CSI 0x00008E43
-#define CLK_UART6_HSE 0x00008E44
-#define CLK_UART6_DISABLED 0x00008E47
+#define CLK_SPI45_PCLK2 CLKSRC(MUX_SPI45, 0)
+#define CLK_SPI45_PLL4Q CLKSRC(MUX_SPI45, 1)
+#define CLK_SPI45_HSI CLKSRC(MUX_SPI45, 2)
+#define CLK_SPI45_CSI CLKSRC(MUX_SPI45, 3)
+#define CLK_SPI45_HSE CLKSRC(MUX_SPI45, 4)
+#define CLK_SPI45_DISABLED CLKSRC(MUX_SPI45, 7)
-#define CLK_UART24_PCLK1 0x00008E80
-#define CLK_UART24_PLL4Q 0x00008E81
-#define CLK_UART24_HSI 0x00008E82
-#define CLK_UART24_CSI 0x00008E83
-#define CLK_UART24_HSE 0x00008E84
-#define CLK_UART24_DISABLED 0x00008E87
+#define CLK_SPI6_PCLK5 CLKSRC(MUX_SPI6, 0)
+#define CLK_SPI6_PLL4Q CLKSRC(MUX_SPI6, 1)
+#define CLK_SPI6_HSI CLKSRC(MUX_SPI6, 2)
+#define CLK_SPI6_CSI CLKSRC(MUX_SPI6, 3)
+#define CLK_SPI6_HSE CLKSRC(MUX_SPI6, 4)
+#define CLK_SPI6_PLL3Q CLKSRC(MUX_SPI6, 5)
+#define CLK_SPI6_DISABLED CLKSRC(MUX_SPI6, 7)
-#define CLK_UART35_PCLK1 0x00008EC0
-#define CLK_UART35_PLL4Q 0x00008EC1
-#define CLK_UART35_HSI 0x00008EC2
-#define CLK_UART35_CSI 0x00008EC3
-#define CLK_UART35_HSE 0x00008EC4
-#define CLK_UART35_DISABLED 0x00008EC7
+#define CLK_UART6_PCLK2 CLKSRC(MUX_UART6, 0)
+#define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1)
+#define CLK_UART6_HSI CLKSRC(MUX_UART6, 2)
+#define CLK_UART6_CSI CLKSRC(MUX_UART6, 3)
+#define CLK_UART6_HSE CLKSRC(MUX_UART6, 4)
+#define CLK_UART6_DISABLED CLKSRC(MUX_UART6, 7)
-#define CLK_UART78_PCLK1 0x00008F00
-#define CLK_UART78_PLL4Q 0x00008F01
-#define CLK_UART78_HSI 0x00008F02
-#define CLK_UART78_CSI 0x00008F03
-#define CLK_UART78_HSE 0x00008F04
-#define CLK_UART78_DISABLED 0x00008F07
+#define CLK_UART24_PCLK1 CLKSRC(MUX_UART24, 0)
+#define CLK_UART24_PLL4Q CLKSRC(MUX_UART24, 1)
+#define CLK_UART24_HSI CLKSRC(MUX_UART24, 2)
+#define CLK_UART24_CSI CLKSRC(MUX_UART24, 3)
+#define CLK_UART24_HSE CLKSRC(MUX_UART24, 4)
+#define CLK_UART24_DISABLED CLKSRC(MUX_UART24, 7)
-#define CLK_UART1_PCLK5 0x00000C80
-#define CLK_UART1_PLL3Q 0x00000C81
-#define CLK_UART1_HSI 0x00000C82
-#define CLK_UART1_CSI 0x00000C83
-#define CLK_UART1_PLL4Q 0x00000C84
-#define CLK_UART1_HSE 0x00000C85
-#define CLK_UART1_DISABLED 0x00000C87
+#define CLK_UART35_PCLK1 CLKSRC(MUX_UART35, 0)
+#define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1)
+#define CLK_UART35_HSI CLKSRC(MUX_UART35, 2)
+#define CLK_UART35_CSI CLKSRC(MUX_UART35, 3)
+#define CLK_UART35_HSE CLKSRC(MUX_UART35, 4)
+#define CLK_UART35_DISABLED CLKSRC(MUX_UART35, 7)
-#define CLK_SDMMC12_HCLK6 0x00008F40
-#define CLK_SDMMC12_PLL3R 0x00008F41
-#define CLK_SDMMC12_PLL4P 0x00008F42
-#define CLK_SDMMC12_HSI 0x00008F43
-#define CLK_SDMMC12_DISABLED 0x00008F47
+#define CLK_UART78_PCLK1 CLKSRC(MUX_UART78, 0)
+#define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1)
+#define CLK_UART78_HSI CLKSRC(MUX_UART78, 2)
+#define CLK_UART78_CSI CLKSRC(MUX_UART78, 3)
+#define CLK_UART78_HSE CLKSRC(MUX_UART78, 4)
+#define CLK_UART78_DISABLED CLKSRC(MUX_UART78, 7)
-#define CLK_SDMMC3_HCLK2 0x00008F80
-#define CLK_SDMMC3_PLL3R 0x00008F81
-#define CLK_SDMMC3_PLL4P 0x00008F82
-#define CLK_SDMMC3_HSI 0x00008F83
-#define CLK_SDMMC3_DISABLED 0x00008F87
+#define CLK_UART1_PCLK5 CLKSRC(MUX_UART1, 0)
+#define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1)
+#define CLK_UART1_HSI CLKSRC(MUX_UART1, 2)
+#define CLK_UART1_CSI CLKSRC(MUX_UART1, 3)
+#define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4)
+#define CLK_UART1_HSE CLKSRC(MUX_UART1, 5)
+#define CLK_UART1_DISABLED CLKSRC(MUX_UART1, 7)
-#define CLK_ETH_PLL4P 0x00008FC0
-#define CLK_ETH_PLL3Q 0x00008FC1
-#define CLK_ETH_DISABLED 0x00008FC3
+#define CLK_SDMMC12_HCLK6 CLKSRC(MUX_SDMMC12, 0)
+#define CLK_SDMMC12_PLL3R CLKSRC(MUX_SDMMC12, 1)
+#define CLK_SDMMC12_PLL4P CLKSRC(MUX_SDMMC12, 2)
+#define CLK_SDMMC12_HSI CLKSRC(MUX_SDMMC12, 3)
+#define CLK_SDMMC12_DISABLED CLKSRC(MUX_SDMMC12, 7)
-#define CLK_QSPI_ACLK 0x00009000
-#define CLK_QSPI_PLL3R 0x00009001
-#define CLK_QSPI_PLL4P 0x00009002
-#define CLK_QSPI_CKPER 0x00009003
+#define CLK_SDMMC3_HCLK2 CLKSRC(MUX_SDMMC3, 0)
+#define CLK_SDMMC3_PLL3R CLKSRC(MUX_SDMMC3, 1)
+#define CLK_SDMMC3_PLL4P CLKSRC(MUX_SDMMC3, 2)
+#define CLK_SDMMC3_HSI CLKSRC(MUX_SDMMC3, 3)
+#define CLK_SDMMC3_DISABLED CLKSRC(MUX_SDMMC3, 7)
-#define CLK_FMC_ACLK 0x00009040
-#define CLK_FMC_PLL3R 0x00009041
-#define CLK_FMC_PLL4P 0x00009042
-#define CLK_FMC_CKPER 0x00009043
+#define CLK_ETH_PLL4P CLKSRC(MUX_ETH, 0)
+#define CLK_ETH_PLL3Q CLKSRC(MUX_ETH, 1)
+#define CLK_ETH_DISABLED CLKSRC(MUX_ETH, 3)
-#define CLK_FDCAN_HSE 0x000090C0
-#define CLK_FDCAN_PLL3Q 0x000090C1
-#define CLK_FDCAN_PLL4Q 0x000090C2
-#define CLK_FDCAN_PLL4R 0x000090C3
+#define CLK_QSPI_ACLK CLKSRC(MUX_QSPI, 0)
+#define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1)
+#define CLK_QSPI_PLL4P CLKSRC(MUX_QSPI, 2)
+#define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3)
-#define CLK_SPDIF_PLL4P 0x00009140
-#define CLK_SPDIF_PLL3Q 0x00009141
-#define CLK_SPDIF_HSI 0x00009142
-#define CLK_SPDIF_DISABLED 0x00009143
+#define CLK_FMC_ACLK CLKSRC(MUX_FMC, 0)
+#define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1)
+#define CLK_FMC_PLL4P CLKSRC(MUX_FMC, 2)
+#define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3)
-#define CLK_CEC_LSE 0x00009180
-#define CLK_CEC_LSI 0x00009181
-#define CLK_CEC_CSI_DIV122 0x00009182
-#define CLK_CEC_DISABLED 0x00009183
+#define CLK_FDCAN_HSE CLKSRC(MUX_FDCAN, 0)
+#define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1)
+#define CLK_FDCAN_PLL4Q CLKSRC(MUX_FDCAN, 2)
+#define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3)
-#define CLK_USBPHY_HSE 0x000091C0
-#define CLK_USBPHY_PLL4R 0x000091C1
-#define CLK_USBPHY_HSE_DIV2 0x000091C2
-#define CLK_USBPHY_DISABLED 0x000091C3
+#define CLK_SPDIF_PLL4P CLKSRC(MUX_SPDIF, 0)
+#define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1)
+#define CLK_SPDIF_HSI CLKSRC(MUX_SPDIF, 2)
+#define CLK_SPDIF_DISABLED CLKSRC(MUX_SPDIF, 3)
-#define CLK_USBO_PLL4R 0x800091C0
-#define CLK_USBO_USBPHY 0x800091C1
+#define CLK_CEC_LSE CLKSRC(MUX_CEC, 0)
+#define CLK_CEC_LSI CLKSRC(MUX_CEC, 1)
+#define CLK_CEC_CSI_DIV122 CLKSRC(MUX_CEC, 2)
+#define CLK_CEC_DISABLED CLKSRC(MUX_CEC, 3)
-#define CLK_RNG1_CSI 0x00000CC0
-#define CLK_RNG1_PLL4R 0x00000CC1
-#define CLK_RNG1_LSE 0x00000CC2
-#define CLK_RNG1_LSI 0x00000CC3
+#define CLK_USBPHY_HSE CLKSRC(MUX_USBPHY, 0)
+#define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1)
+#define CLK_USBPHY_HSE_DIV2 CLKSRC(MUX_USBPHY, 2)
+#define CLK_USBPHY_DISABLED CLKSRC(MUX_USBPHY, 3)
-#define CLK_RNG2_CSI 0x00009200
-#define CLK_RNG2_PLL4R 0x00009201
-#define CLK_RNG2_LSE 0x00009202
-#define CLK_RNG2_LSI 0x00009203
+#define CLK_USBO_PLL4R CLKSRC(MUX_USBO, 0)
+#define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1)
-#define CLK_CKPER_HSI 0x00000D00
-#define CLK_CKPER_CSI 0x00000D01
-#define CLK_CKPER_HSE 0x00000D02
-#define CLK_CKPER_DISABLED 0x00000D03
+#define CLK_RNG1_CSI CLKSRC(MUX_RNG1, 0)
+#define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1)
+#define CLK_RNG1_LSE CLKSRC(MUX_RNG1, 2)
+#define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3)
-#define CLK_STGEN_HSI 0x00000D40
-#define CLK_STGEN_HSE 0x00000D41
-#define CLK_STGEN_DISABLED 0x00000D43
+#define CLK_RNG2_CSI CLKSRC(MUX_RNG2, 0)
+#define CLK_RNG2_PLL4R CLKSRC(MUX_RNG2, 1)
+#define CLK_RNG2_LSE CLKSRC(MUX_RNG2, 2)
+#define CLK_RNG2_LSI CLKSRC(MUX_RNG2, 3)
-#define CLK_DSI_DSIPLL 0x00009240
-#define CLK_DSI_PLL4P 0x00009241
+#define CLK_CKPER_HSI CLKSRC(MUX_CKPER, 0)
+#define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1)
+#define CLK_CKPER_HSE CLKSRC(MUX_CKPER, 2)
+#define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3)
-#define CLK_ADC_PLL4R 0x00009280
-#define CLK_ADC_CKPER 0x00009281
-#define CLK_ADC_PLL3Q 0x00009282
-#define CLK_ADC_DISABLED 0x00009283
+#define CLK_STGEN_HSI CLKSRC(MUX_STGEN, 0)
+#define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1)
+#define CLK_STGEN_DISABLED CLKSRC(MUX_STGEN, 3)
-#define CLK_LPTIM45_PCLK3 0x000092C0
-#define CLK_LPTIM45_PLL4P 0x000092C1
-#define CLK_LPTIM45_PLL3Q 0x000092C2
-#define CLK_LPTIM45_LSE 0x000092C3
-#define CLK_LPTIM45_LSI 0x000092C4
-#define CLK_LPTIM45_CKPER 0x000092C5
-#define CLK_LPTIM45_DISABLED 0x000092C7
+#define CLK_DSI_DSIPLL CLKSRC(MUX_DSI, 0)
+#define CLK_DSI_PLL4P CLKSRC(MUX_DSI, 1)
-#define CLK_LPTIM23_PCLK3 0x00009300
-#define CLK_LPTIM23_PLL4Q 0x00009301
-#define CLK_LPTIM23_CKPER 0x00009302
-#define CLK_LPTIM23_LSE 0x00009303
-#define CLK_LPTIM23_LSI 0x00009304
-#define CLK_LPTIM23_DISABLED 0x00009307
+#define CLK_ADC_PLL4R CLKSRC(MUX_ADC, 0)
+#define CLK_ADC_CKPER CLKSRC(MUX_ADC, 1)
+#define CLK_ADC_PLL3Q CLKSRC(MUX_ADC, 2)
+#define CLK_ADC_DISABLED CLKSRC(MUX_ADC, 3)
+
+#define CLK_LPTIM45_PCLK3 CLKSRC(MUX_LPTIM45, 0)
+#define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1)
+#define CLK_LPTIM45_PLL3Q CLKSRC(MUX_LPTIM45, 2)
+#define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3)
+#define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4)
+#define CLK_LPTIM45_CKPER CLKSRC(MUX_LPTIM45, 5)
+#define CLK_LPTIM45_DISABLED CLKSRC(MUX_LPTIM45, 7)
+
+#define CLK_LPTIM23_PCLK3 CLKSRC(MUX_LPTIM23, 0)
+#define CLK_LPTIM23_PLL4Q CLKSRC(MUX_LPTIM23, 1)
+#define CLK_LPTIM23_CKPER CLKSRC(MUX_LPTIM23, 2)
+#define CLK_LPTIM23_LSE CLKSRC(MUX_LPTIM23, 3)
+#define CLK_LPTIM23_LSI CLKSRC(MUX_LPTIM23, 4)
+#define CLK_LPTIM23_DISABLED CLKSRC(MUX_LPTIM23, 7)
-#define CLK_LPTIM1_PCLK1 0x00009340
-#define CLK_LPTIM1_PLL4P 0x00009341
-#define CLK_LPTIM1_PLL3Q 0x00009342
-#define CLK_LPTIM1_LSE 0x00009343
-#define CLK_LPTIM1_LSI 0x00009344
-#define CLK_LPTIM1_CKPER 0x00009345
-#define CLK_LPTIM1_DISABLED 0x00009347
+#define CLK_LPTIM1_PCLK1 CLKSRC(MUX_LPTIM1, 0)
+#define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1)
+#define CLK_LPTIM1_PLL3Q CLKSRC(MUX_LPTIM1, 2)
+#define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3)
+#define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4)
+#define CLK_LPTIM1_CKPER CLKSRC(MUX_LPTIM1, 5)
+#define CLK_LPTIM1_DISABLED CLKSRC(MUX_LPTIM1, 7)
/* define for st,pll /csg */
#define SSCG_MODE_CENTER_SPREAD 0
diff --git a/include/lib/psa/cca_attestation.h b/include/lib/psa/cca_attestation.h
new file mode 100644
index 0000000..4062dde
--- /dev/null
+++ b/include/lib/psa/cca_attestation.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CCA_ATTESTATION_H
+#define CCA_ATTESTATION_H
+
+#include <stdint.h>
+#include <psa/crypto_types.h>
+
+psa_status_t
+cca_attestation_get_realm_key(uintptr_t buf, size_t *len, unsigned int type);
+
+psa_status_t
+cca_attestation_get_plat_token(uintptr_t buf, size_t *len,
+ uintptr_t hash, size_t hash_size);
+
+#endif /* CCA_ATTESTATION_H */
diff --git a/lib/psa/cca_attestation.c b/lib/psa/cca_attestation.c
new file mode 100644
index 0000000..9e9e0c1
--- /dev/null
+++ b/lib/psa/cca_attestation.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <psa/crypto_sizes.h>
+#include <psa/crypto_types.h>
+#include <psa/crypto_values.h>
+
+#include <cca_attestation.h>
+#include <delegated_attestation.h>
+#include <services/rmmd_svc.h>
+
+psa_status_t
+cca_attestation_get_realm_key(uintptr_t buf, size_t *len, unsigned int type)
+{
+ size_t dak_len;
+ psa_status_t ret = PSA_SUCCESS;
+
+ /*
+ * Current RMM implementations only support the public key size for
+ * ECC-P384, i.e. ATTEST_KEY_CURVE_ECC_SECP384R1 attestation key.
+ *
+ * This ECC key has following properties:
+ * ecc_curve: 0x12 (PSA_ECC_FAMILY_SECP_R1)
+ * key_bits: 384
+ * hash_alg: 0x02000009 (PSA_ALG_SHA_256)
+ */
+ assert(type == ATTEST_KEY_CURVE_ECC_SECP384R1);
+
+ ret = rse_delegated_attest_get_delegated_key(PSA_ECC_FAMILY_SECP_R1,
+ 384, (uint8_t *)buf, *len,
+ &dak_len, PSA_ALG_SHA_256);
+ if (ret != PSA_SUCCESS) {
+ return ret;
+ }
+
+ if (dak_len != PSA_BITS_TO_BYTES(384)) {
+ return PSA_ERROR_INVALID_ARGUMENT;
+ }
+
+ *len = dak_len;
+
+ return ret;
+}
+
+psa_status_t
+cca_attestation_get_plat_token(uintptr_t buf, size_t *len,
+ uintptr_t hash, size_t hash_size)
+{
+ size_t token_len = 0;
+ psa_status_t ret = PSA_SUCCESS;
+
+ ret = rse_delegated_attest_get_token((const uint8_t *)hash, hash_size,
+ (uint8_t *)buf, *len, &token_len);
+ if (ret != PSA_SUCCESS) {
+ return ret;
+ }
+
+ *len = token_len;
+
+ return ret;
+}
diff --git a/plat/arm/board/common/board_arm_trusted_boot.c b/plat/arm/board/common/board_arm_trusted_boot.c
index 655a4d2..4a2572f 100644
--- a/plat/arm/board/common/board_arm_trusted_boot.c
+++ b/plat/arm/board/common/board_arm_trusted_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -219,6 +219,15 @@
} else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
nv_ctr_addr = (uint32_t *)FCONF_GET_PROPERTY(cot, nv_cntr_addr,
NON_TRUSTED_NV_CTR_ID);
+#if defined(ARM_COT_cca)
+ } else if (strcmp(oid, CCA_FW_NVCOUNTER_OID) == 0) {
+ /*
+ * Use Trusted NV counter for platforms that don't support
+ * the CCA NV Counter.
+ */
+ nv_ctr_addr = (uint32_t *)FCONF_GET_PROPERTY(cot, nv_cntr_addr,
+ TRUSTED_NV_CTR_ID);
+#endif
} else {
return 1;
}
diff --git a/plat/arm/board/fvp/fdts/fvp_cot_desc.dtsi b/plat/arm/board/fvp/fdts/fvp_cot_desc.dtsi
new file mode 100644
index 0000000..9c8328b
--- /dev/null
+++ b/plat/arm/board/fvp/fdts/fvp_cot_desc.dtsi
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#if COT_DESC_IN_DTB
+ #if defined(ARM_COT_cca)
+ #include "cca_cot_descriptors.dtsi"
+ #elif defined(ARM_COT_dualroot)
+ #include "dualroot_cot_descriptors.dtsi"
+ #elif defined(ARM_COT_tbbr)
+ #include "tbbr_cot_descriptors.dtsi"
+ #endif
+#endif
diff --git a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
index 9eb2177..b1d3bc1 100644
--- a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
@@ -103,13 +103,7 @@
#endif /* ARM_BL2_SP_LIST_DTS */
};
-#if COT_DESC_IN_DTB
- #if defined(ARM_COT_cca)
- #include "cca_cot_descriptors.dtsi"
- #elif defined(ARM_COT_tbbr)
- #include "tbbr_cot_descriptors.dtsi"
- #endif
-#endif
+#include "fvp_cot_desc.dtsi"
#if MEASURED_BOOT
#include "event_log.dtsi"
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h
new file mode 100644
index 0000000..bd2e682
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the CSS specific definitions for the third generation of
+ * platforms.
+ */
+
+#ifndef NRD_CSS_DEF3_H
+#define NRD_CSS_DEF3_H
+
+/*******************************************************************************
+ * CSS memory map related defines
+ ******************************************************************************/
+
+/* Shared RAM */
+#define NRD_CSS_SHARED_SRAM_BASE UL(0x00000000)
+
+/* General Peripherals */
+#define NRD_CSS_PERIPH_BASE UL(0x20000000)
+#define NRD_CSS_PERIPH_SIZE UL(0x20000000)
+
+/* System NCI */
+#define NRD_CSS_SYSTEM_NCI_BASE UL(0x20000000)
+#define NRD_CSS_SYSTEM_NCI_SIZE UL(0x04000000)
+
+/* Debug NIC */
+#define NRD_CSS_DEBUG_NIC_BASE UL(0x28000000)
+#define NRD_CSS_DEBUG_NIC_SIZE UL(0x01000000)
+
+/* NS UART */
+#define NRD_CSS_NS_UART_BASE UL(0x2A400000)
+#define NRD_CSS_NS_UART_SIZE UL(0x00010000)
+
+/* Secure UART */
+#define NRD_CSS_SECURE_UART_BASE UL(0x2A410000)
+#define NRD_CSS_SECURE_UART_SIZE UL(0x00010000)
+
+/* Realm UART */
+#define NRD_CSS_REALM_UART_BASE UL(0x2A420000)
+#define NRD_CSS_REALM_UART_SIZE UL(0x00010000)
+
+/* Generic Refclk */
+#define NRD_CSS_GENERIC_REFCLK_BASE UL(0x2A430000)
+#define NRD_CSS_GENERIC_REFCLK_SIZE UL(0x00010000)
+
+/* NS Watchdog */
+#define NRD_CSS_AP_NS_WDOG_BASE UL(0x2A440000)
+#define NRD_CSS_AP_NS_WDOG_SIZE UL(0x00020000)
+
+/* Root Watchdog */
+#define NRD_CSS_AP_ROOT_WDOG_BASE UL(0x2A460000)
+#define NRD_CSS_AP_ROOT_WDOG_SIZE UL(0x00020000)
+
+/* Secure Watchdog */
+#define NRD_CSS_AP_SECURE_WDOG_BASE UL(0x2A480000)
+#define NRD_CSS_AP_SECURE_WDOG_SIZE UL(0x00020000)
+
+/* SID */
+#define NRD_CSS_SID_BASE UL(0x2A4A0000)
+#define NRD_CSS_SID_SIZE UL(0x00010000)
+
+/* SRAM Secure Error Record Block - AP */
+#define NRD_CSS_SECURE_SRAM_ERB_AP_BASE UL(0x2A4B0000)
+#define NRD_CSS_SECURE_SRAM_ERB_AP_SIZE UL(0x00010000)
+
+/* SRAM NS Error Record Block - AP */
+#define NRD_CSS_NS_SRAM_ERB_AP_BASE UL(0x2A4C0000)
+#define NRD_CSS_NS_SRAM_ERB_AP_SIZE UL(0x00010000)
+
+/* SRAM Root Error Record Block - AP */
+#define NRD_CSS_ROOT_SRAM_ERB_AP_BASE UL(0x2A4D0000)
+#define NRD_CSS_ROOT_SRAM_ERB_AP_SIZE UL(0x00010000)
+
+/* SRAM Realm Error Record Block - AP */
+#define NRD_CSS_REALM_SRAM_ERB_AP_BASE UL(0x2A4E0000)
+#define NRD_CSS_REALM_SRAM_ERB_AP_SIZE UL(0x00010000)
+
+/* SRAM Secure Error Record Block - SCP */
+#define NRD_CSS_SECURE_SRAM_ERB_SCP_BASE UL(0x2A4F0000)
+#define NRD_CSS_SECURE_SRAM_ERB_SCP_SIZE UL(0x00010000)
+
+/* SRAM NS Error Record Block - SCP */
+#define NRD_CSS_NS_SRAM_ERB_SCP_BASE UL(0x2A500000)
+#define NRD_CSS_NS_SRAM_ERB_SCP_SIZE UL(0x00010000)
+
+/* SRAM Root Error Record Block - SCP */
+#define NRD_CSS_ROOT_SRAM_ERB_SCP_BASE UL(0x2A510000)
+#define NRD_CSS_ROOT_SRAM_ERB_SCP_SIZE UL(0x00010000)
+
+/* SRAM Realm Error Record Block - SCP */
+#define NRD_CSS_REALM_SRAM_ERB_SCP_BASE UL(0x2A520000)
+#define NRD_CSS_REALM_SRAM_ERB_SCP_SIZE UL(0x00010000)
+
+/* SRAM Secure Error Record Block - MCP */
+#define NRD_CSS_SECURE_SRAM_ERB_MCP_BASE UL(0x2A530000)
+#define NRD_CSS_SECURE_SRAM_ERB_MCP_SIZE UL(0x00010000)
+
+/* SRAM NS Error Record Block - MCP */
+#define NRD_CSS_NS_SRAM_ERB_MCP_BASE UL(0x2A540000)
+#define NRD_CSS_NS_SRAM_ERB_MCP_SIZE UL(0x00010000)
+
+/* SRAM Root Error Record Block - MCP */
+#define NRD_CSS_ROOT_SRAM_ERB_MCP_BASE UL(0x2A550000)
+#define NRD_CSS_ROOT_SRAM_ERB_MCP_SIZE UL(0x00010000)
+
+/* SRAM Realm Error Record Block - MCP */
+#define NRD_CSS_REALM_SRAM_ERB_MCP_BASE UL(0x2A560000)
+#define NRD_CSS_REALM_SRAM_ERB_MCP_SIZE UL(0x00010000)
+
+/* SRAM Secure Error Record Block - RSE */
+#define NRD_CSS_SECURE_SRAM_ERB_RSE_BASE UL(0x2A570000)
+#define NRD_CSS_SECURE_SRAM_ERB_RSE_SIZE UL(0x00010000)
+
+/* SRAM NS Error Record Block - RSE */
+#define NRD_CSS_NS_SRAM_ERB_RSE_BASE UL(0x2A580000)
+#define NRD_CSS_NS_SRAM_ERB_RSE_SIZE UL(0x00010000)
+
+/* SRAM Root Error Record Block - RSE */
+#define NRD_CSS_ROOT_SRAM_ERB_RSE_BASE UL(0x2A590000)
+#define NRD_CSS_ROOT_SRAM_ERB_RSE_SIZE UL(0x00010000)
+
+/* SRAM Realm Error Record Block - RSE */
+#define NRD_CSS_REALM_SRAM_ERB_RSE_BASE UL(0x2A5A0000)
+#define NRD_CSS_REALM_SRAM_ERB_RSE_SIZE UL(0x00010000)
+
+/* RSE SRAM Secure Error Record Block - RSM */
+#define NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_BASE UL(0x2A5B0000)
+#define NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* RSE SRAM Secure Error Record Block - RSM */
+#define NRD_CSS_RSE_NS_SRAM_ERB_RSM_BASE UL(0x2A5C0000)
+#define NRD_CSS_RSE_NS_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* SCP SRAM Secure Error Record Block - RSM */
+#define NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_BASE UL(0x2A5D0000)
+#define NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* SCP SRAM NS Error Record Block - RSM */
+#define NRD_CSS_SCP_NS_SRAM_ERB_RSM_BASE UL(0x2A5E0000)
+#define NRD_CSS_SCP_NS_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* MCP SRAM Secure Error Record Block - RSM */
+#define NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_BASE UL(0x2A5F0000)
+#define NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* MCP SRAM NS Error Record Block - RSM */
+#define NRD_CSS_MCP_NS_SRAM_ERB_RSM_BASE UL(0x2A600000)
+#define NRD_CSS_MCP_NS_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* CNTCTL Refclk Readframe */
+#define NRD_CSS_CNTCTL_REFCLK_READFRAME_BASE UL(0x2A800000)
+#define NRD_CSS_CNTCTL_REFCLK_READFRAME_SIZE UL(0x00020000)
+
+/* CNTCTL base */
+#define NRD_CSS_SYS_TIMCTL_BASE UL(0x2A810000)
+
+/* Secure Timer */
+#define NRD_CSS_SECURE_TIMER_CTL_BASE UL(0x2A820000)
+#define NRD_CSS_SECURE_TIMER_CTL_SIZE UL(0x00010000)
+
+/* NS Timer */
+#define NRD_CSS_NS_TIMER_CTL_BASE UL(0x2A830000)
+#define NRD_CSS_NS_TIMER_CTL_SIZE UL(0x00010000)
+
+/* AP - SCP NS MHU */
+#define NRD_CSS_AP_SCP_NS_MHU_BASE UL(0x2A900000)
+#define NRD_CSS_AP_SCP_NS_MHU_SIZE UL(0x00020000)
+
+/* AP - SCP Secure MHU */
+#define NRD_CSS_AP_SCP_SECURE_MHU_BASE UL(0x2A920000)
+#define NRD_CSS_AP_SCP_SECURE_MHU_SIZE UL(0x00020000)
+
+/* AP - SCP Root MHU */
+#define NRD_CSS_AP_SCP_ROOT_MHU_BASE UL(0x2A940000)
+#define NRD_CSS_AP_SCP_ROOT_MHU_SIZE UL(0x00020000)
+
+/* AP - MCP NS MHU */
+#define NRD_CSS_AP_MCP_NS_MHU_BASE UL(0x2AA00000)
+#define NRD_CSS_AP_MCP_NS_MHU_SIZE UL(0x00020000)
+
+/* AP - MCP Secure MHU */
+#define NRD_CSS_AP_MCP_SECURE_MHU_BASE UL(0x2AA20000)
+#define NRD_CSS_AP_MCP_SECURE_MHU_SIZE UL(0x00020000)
+
+/* AP - MCP Root MHU */
+#define NRD_CSS_AP_MCP_ROOT_MHU_BASE UL(0x2AA40000)
+#define NRD_CSS_AP_MCP_ROOT_MHU_SIZE UL(0x00020000)
+
+/* AP - RSE NS MHU */
+#define NRD_CSS_AP_RSE_NS_MHU_BASE UL(0x2AB00000)
+#define NRD_CSS_AP_RSE_NS_MHU_SIZE UL(0x00020000)
+
+/* AP - RSE Secure MHU */
+#define NRD_CSS_AP_RSE_SECURE_MHU_BASE UL(0x2AB20000)
+#define NRD_CSS_AP_RSE_SECURE_MHU_SIZE UL(0x00020000)
+
+/* AP - RSE Root MHU */
+#define NRD_CSS_AP_RSE_ROOT_MHU_BASE UL(0x2AB40000)
+#define NRD_CSS_AP_RSE_ROOT_MHU_SIZE UL(0x00020000)
+
+/* AP - RSE Realm MHU */
+#define NRD_CSS_AP_RSE_REALM_MHU_BASE UL(0x2AB60000)
+#define NRD_CSS_AP_RSE_REALM_MHU_SIZE UL(0x00020000)
+
+/* SCP - MCP - RSE Cross chip MHU */
+#define NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_BASE UL(0x2AC00000)
+#define NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_SIZE UL(0x00120000)
+
+/* Synchronization Master Tupdate */
+#define NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_BASE UL(0x2B100000)
+#define NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_SIZE UL(0x00030000)
+
+/* AP - RSE NS MHU */
+#define NRD_CSS_STM_SYSTEM_ITS_BASE UL(0x2CF00000)
+#define NRD_CSS_STM_SYSTEM_ITS_SIZE UL(0x02100000)
+
+/* SCP - MCP - RSE Shared SRAM */
+#define NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_BASE UL(0x2F000000)
+#define NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_SIZE UL(0x00400000)
+
+/* GIC base */
+#define NRD_CSS_GIC_BASE UL(0x30000000)
+#define NRD_CSS_GIC_SIZE UL(0x08000000)
+
+/* CMN */
+#define NRD_CSS_CMN_BASE ULL(0x100000000)
+#define NRD_CSS_CMN_SIZE UL(0x40000000)
+
+/* LCP Peripherals */
+#define NRD_CSS_LCP_PERIPHERAL_BASE ULL(0x200000000)
+#define NRD_CSS_LCP_PERIPHERAL_SIZE UL(0x40000000)
+
+/* DDR IO */
+#define NRD_CSS_DDR_IO_BASE ULL(0x240000000)
+#define NRD_CSS_DDR_IO_SIZE UL(0x40000000)
+
+/* SMMU & NCI IO */
+#define NRD_CSS_SMMU_NCI_IO_BASE ULL(0x280000000)
+#define NRD_CSS_SMMU_NCI_IO_SIZE UL(0x60000000)
+
+/* GPC SMMU */
+#define NRD_CSS_GPC_SMMUV3_BASE UL(0x300000000)
+#define NRD_CSS_GPC_SMMUV3_SIZE UL(0x8000000)
+
+/* DRAM1 */
+#define NRD_CSS_DRAM1_BASE UL(0x80000000)
+
+/* DRAM2 */
+#define NRD_CSS_DRAM2_BASE ULL(0x8080000000)
+
+/*******************************************************************************
+ * MHUv3 related definitions
+ ******************************************************************************/
+
+#define MHU_V3_MBX_FRAME_OFFSET UL(0x10000)
+
+/* MHUv3 Postbox and Mailbox register frame base */
+#define AP_RSE_ROOT_MHU_V3_PBX NRD_CSS_AP_RSE_ROOT_MHU_BASE
+#define AP_RSE_ROOT_MHU_V3_MBX NRD_CSS_AP_RSE_ROOT_MHU_BASE + \
+ MHU_V3_MBX_FRAME_OFFSET
+
+#define AP_RSE_SECURE_MHU_V3_PBX NRD_CSS_AP_RSE_SECURE_MHU_BASE
+#define AP_RSE_SECURE_MHU_V3_MBX NRD_CSS_AP_RSE_SECURE_MHU_BASE + \
+ MHU_V3_MBX_FRAME_OFFSET
+
+#endif /* NRD_CSS_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
new file mode 100644
index 0000000..1b92ec2
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the CSS-firmware specific definitions for the third
+ * generation of platforms.
+ */
+
+#ifndef NRD_CSS_FW_DEF3_H
+#define NRD_CSS_FW_DEF3_H
+
+#include <nrd_css_def3.h>
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+#define NRD_CSS_BL1_RW_SIZE UL(64 * 1024) /* 64KB */
+
+#define NRD_CSS_BL1_RO_BASE NRD_CSS_SHARED_SRAM_BASE
+#define NRD_CSS_BL1_RO_SIZE UL(0x00019000)
+
+# define NRD_CSS_BL2_SIZE UL(0x30000)
+
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
+ * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
+ * and BL1-RW. NRD_BL31_SIZE - is tuned with respect to the actual BL31
+ * PROGBITS size which is around 64-68KB at the time this change is being made.
+ * A buffer of ~35KB is added to account for future expansion of the image,
+ * making it a total of 100KB.
+ */
+#define NRD_CSS_BL31_SIZE UL(116 * 1024) /* 116 KB */
+
+#define NRD_CSS_DRAM1_CARVEOUT_SIZE UL(0x0C000000) /* 117MB */
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define NRD_CSS_UART_CLK_IN_HZ UL(7372800)
+
+/*******************************************************************************
+ * Watchdog config
+ ******************************************************************************/
+
+#define NRD_CSS_AP_SECURE_WDOG_TIMEOUT UL(100)
+
+/*******************************************************************************
+ * RMM Console Config
+ ******************************************************************************/
+
+#define NRD_CSS_RMM_CONSOLE_BASE NRD_CSS_REALM_UART_BASE
+#define NRD_CSS_RMM_CONSOLE_BAUD ARM_CONSOLE_BAUDRATE
+#define NRD_CSS_RMM_CONSOLE_CLK_IN_HZ UL(14745600)
+#define NRD_CSS_RMM_CONSOLE_NAME "pl011"
+#define NRD_CSS_RMM_CONSOLE_COUNT UL(1)
+
+/*******************************************************************************
+ * MMU mapping
+ ******************************************************************************/
+
+#define NRD_CSS_PERIPH_MMAP(n) \
+ MAP_REGION_FLAT( \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
+ NRD_CSS_PERIPH_BASE, \
+ NRD_CSS_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+
+#define NRD_CSS_SHARED_RAM_MMAP(n) \
+ MAP_REGION_FLAT( \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
+ ARM_SHARED_RAM_BASE, \
+ ARM_SHARED_RAM_SIZE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#define NRD_CSS_GPC_SMMU_SMMUV3_MMAP \
+ MAP_REGION_FLAT( \
+ NRD_CSS_GPC_SMMUV3_BASE, \
+ NRD_CSS_GPC_SMMUV3_SIZE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+
+#define NRD_CSS_BL1_RW_MMAP \
+ MAP_REGION_FLAT( \
+ BL1_RW_BASE, \
+ BL1_RW_LIMIT - BL1_RW_BASE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#define NRD_CSS_NS_DRAM1_MMAP \
+ MAP_REGION_FLAT( \
+ ARM_NS_DRAM1_BASE, \
+ ARM_NS_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#define NRD_CSS_GPT_L1_DRAM_MMAP \
+ MAP_REGION_FLAT( \
+ ARM_L1_GPT_BASE, \
+ ARM_L1_GPT_SIZE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#define NRD_CSS_EL3_RMM_SHARED_MEM_MMAP \
+ MAP_REGION_FLAT( \
+ ARM_EL3_RMM_SHARED_BASE, \
+ ARM_EL3_RMM_SHARED_SIZE, \
+ MT_MEMORY | MT_RW | MT_REALM)
+
+#define NRD_CSS_RMM_REGION_MMAP \
+ MAP_REGION_FLAT( \
+ ARM_REALM_BASE, \
+ ARM_REALM_SIZE, \
+ MT_MEMORY | MT_RW | MT_REALM)
+
+#endif /* NRD_CSS_FW_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h
new file mode 100644
index 0000000..f9a62ae
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h
@@ -0,0 +1,584 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NRD_PAS_DEF3_H
+#define NRD_PAS_DEF3_H
+
+#ifndef __ASSEMBLER__
+#include <stddef.h>
+#include <lib/gpt_rme/gpt_rme.h>
+#endif
+
+#include <nrd_css_def3.h>
+
+/*****************************************************************************
+ * PAS regions used to initialize the Granule Protection Table (GPT)
+ ****************************************************************************/
+
+/*
+ * =====================================================================
+ * Base Addr |Size |L? GPT |PAS |Content |
+ * =====================================================================
+ * 0x00000000 |256MB |L0 GPT |ANY |SHARED RAM |
+ * 0x0FFFFFFF | | | |AP EXPANSION |
+ * ---------------------------------------------------------------------
+ * 0x20000000 |64MB |L1 GPT |ROOT |SYSTEM NCI |
+ * 0x23FFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x28000000 |16MB |L1 GPT |SECURE |DEBUG NIC |
+ * 0x28FFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A400000 |64KB |L1 GPT |NS |NS UART |
+ * 0x2A40FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A410000 |64KB |L1 GPT |SECURE |SECURE UART |
+ * 0x2A41FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A420000 |64KB |L1 GPT |REALM |REALM UART |
+ * 0x2A42FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A430000 |64KB |L1 GPT |SECURE |GENERIC REFCLK |
+ * 0x2A43FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A440000 |128KB |L1 GPT |NS |AP NS WDOG |
+ * 0x2A45FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A460000 |128KB |L1 GPT |ROOT |AP ROOT WDOG |
+ * 0x2A47FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A480000 |128KB |L1 GPT |SECURE |AP SECURE WDOG |
+ * 0x2A49FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A4A0000 |64KB |L1 GPT |NS |SID |
+ * 0x2A4AFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A4B0000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR |
+ * 0x2A4BFFFF | | | |RECORD BLOCK - AP |
+ * ---------------------------------------------------------------------
+ * 0x2A4C0000 |64KB |L1 GPT |NS |NS SRAM ERROR |
+ * 0x2A4CFFFF | | | |RECORD BLOCK - AP |
+ * ---------------------------------------------------------------------
+ * 0x2A4D0000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR |
+ * 0x2A4DFFFF | | | |RECORD BLOCK - AP |
+ * ---------------------------------------------------------------------
+ * 0x2A4E0000 |64KB |L1 GPT |REALM |REALM SRAM ERROR |
+ * 0x2A4EFFFF | | | |RECORD BLOCK - AP |
+ * ---------------------------------------------------------------------
+ * 0x2A4F0000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR |
+ * 0x2A4FFFFF | | | |RECORD BLOCK - SCP |
+ * ---------------------------------------------------------------------
+ * 0x2A500000 |64KB |L1 GPT |NS |NS SRAM ERROR |
+ * 0x2A50FFFF | | | |RECORD BLOCK - SCP |
+ * ---------------------------------------------------------------------
+ * 0x2A510000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR |
+ * 0x2A51FFFF | | | |RECORD BLOCK - SCP |
+ * ---------------------------------------------------------------------
+ * 0x2A520000 |64KB |L1 GPT |REALM |REALM SRAM ERROR |
+ * 0x2A52FFFF | | | |RECORD BLOCK - SCP |
+ * ---------------------------------------------------------------------
+ * 0x2A530000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR |
+ * 0x2A53FFFF | | | |RECORD BLOCK - MCP |
+ * ---------------------------------------------------------------------
+ * 0x2A540000 |64KB |L1 GPT |NS |NS SRAM ERROR |
+ * 0x2A54FFFF | | | |RECORD BLOCK - MCP |
+ * ---------------------------------------------------------------------
+ * 0x2A550000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR |
+ * 0x2A55FFFF | | | |RECORD BLOCK - MCP |
+ * ---------------------------------------------------------------------
+ * 0x2A560000 |64KB |L1 GPT |REALM |REALM SRAM ERROR |
+ * 0x2A56FFFF | | | |RECORD BLOCK - MCP |
+ * ---------------------------------------------------------------------
+ * 0x2A570000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR |
+ * 0x2A57FFFF | | | |RECORD BLOCK - RSE |
+ * ---------------------------------------------------------------------
+ * 0x2A580000 |64KB |L1 GPT |NS |NS SRAM ERROR |
+ * 0x2A58FFFF | | | |RECORD BLOCK - RSE |
+ * ---------------------------------------------------------------------
+ * 0x2A590000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR |
+ * 0x2A59FFFF | | | |RECORD BLOCK - RSE |
+ * ---------------------------------------------------------------------
+ * 0x2A5A0000 |64KB |L1 GPT |REALM |REALM SRAM ERROR |
+ * 0x2A5AFFFF | | | |RECORD BLOCK - RSE |
+ * ---------------------------------------------------------------------
+ * 0x2A5B0000 |64KB |L1 GPT |SECURE |RSE SECURE SRAM ERROR |
+ * 0x2A5BFFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A5C0000 |64KB |L1 GPT |NS |RSE NS SRAM ERROR |
+ * 0x2A5CFFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A5D0000 |64KB |L1 GPT |SECURE |SCP SECURE SRAM ERROR |
+ * 0x2A5DFFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A5E0000 |64KB |L1 GPT |NS |SCP NS SRAM ERROR |
+ * 0x2A5EFFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A5F0000 |64KB |L1 GPT |SECURE |MCP SECURE SRAM ERROR |
+ * 0x2A5FFFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A600000 |64KB |L1 GPT |NS |MCP NS SRAM ERROR |
+ * 0x2A60FFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A800000 |128KB |L1 GPT |NS |CNTCTL REFCLK |
+ * 0x2A81FFFF | | | |READ FRAME |
+ * ---------------------------------------------------------------------
+ * 0x2A820000 |64KB |L1 GPT |SECURE |SECURE TIMER CTL |
+ * 0x2A82FFFF | | | |BASE FRAME |
+ * ---------------------------------------------------------------------
+ * 0x2A830000 |64KB |L1 GPT |NS |NS TIMER CTL |
+ * 0x2A83FFFF | | | |BASE FRAME |
+ * ---------------------------------------------------------------------
+ * 0x2A900000 |128KB |L1 GPT |NS |AP-SCP NS |
+ * 0x2A91FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2A920000 |128KB |L1 GPT |SECURE |AP-SCP SECURE |
+ * 0x2A93FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2A940000 |128KB |L1 GPT |ROOT |AP-SCP ROOT |
+ * 0x2A95FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AA00000 |128KB |L1 GPT |NS |AP-MCP NS |
+ * 0x2AA1FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AA20000 |128KB |L1 GPT |SECURE |AP-MCP SECURE |
+ * 0x2AA3FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AA40000 |128KB |L1 GPT |ROOT |AP-MCP ROOT |
+ * 0x2AA5FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AB00000 |128KB |L1 GPT |NS |AP-MCP NS |
+ * 0x2AB1FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AB20000 |128KB |L1 GPT |SECURE |AP-RSE SECURE |
+ * 0x2AB3FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AB40000 |128KB |L1 GPT |ROOT |AP-RSE ROOT |
+ * 0x2AB5FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AB60000 |128KB |L1 GPT |REALM |AP-RSE REALM |
+ * 0x2AB7FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AC00000 |1152KB |L1 GPT |ROOT |SCP MCP RSE |
+ * 0x2ACEFFFF | | | |CROSS CHIP MHU |
+ * ---------------------------------------------------------------------
+ * 0x2B100000 |192KB |L1 GPT |SECURE |SYNCNT |
+ * 0x2B12FFFF | | | |MSTUPDTVAL_ADDR |
+ * ---------------------------------------------------------------------
+ * 0x2CF00000 |~33MB |L1 GPT |NS |STM SYSTEM ITS |
+ * 0x2EFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2F000000 |4MB |L1 GPT |ANY |SHARED SRAM |
+ * 0x2F3FFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x30000000 |128MB |L1 GPT |ANY |GIC CLAYTON |
+ * 0x37FFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x80000000 |2GB - |L1 GPT |NS |NS DRAM |
+ * 0xFFFE2BFF |117MB | | | |
+ * ---------------------------------------------------------------------
+ * 0x80000000 |26MB |L1 GPT |REALM |RMM |
+ * 0x37FFFFFF | | | |TF-A SHARED |
+ * ---------------------------------------------------------------------
+ * 0x80000000 |2MB |L1 GPT |ROOT |L1GPT |
+ * 0x37FFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x100080000000 |2GB |L1 GPT |NS |DRAM 1 CHIP 3 |
+ * 0x1000FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x200080000000 |2GB |L1 GPT |NS |DRAM 1 CHIP 2 |
+ * 0x2000FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x300080000000 |2GB |L1 GPT |NS |DRAM 1 CHIP 1 |
+ * 0x3000FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x100000000 |1GB |L1 GPT |ANY |CMN |
+ * 0x13FFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x200000000 |1GB |L1 GPT |ANY |LCP PERIPHERALS |
+ * 0x23FFFFFFF | | | |DDR |
+ * ---------------------------------------------------------------------
+ * 0x240000000 |1GB |L1 GPT |ANY |DDR IO |
+ * 0x27FFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x280000000 |1.5GB |L1 GPT |ANY |SMMU & NCI IO |
+ * 0x2DFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x300000000 |128MB |L1 GPT |ROOT |GPC SMMU |
+ * 0x308000000 | | | | |
+ * ---------------------------------------------------------------------
+ * 0x8080000000 |6GB |L1 GPT |ANY |DRAM 2 CHIP 0 |
+ * 0x81FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x108080000000 |6GB |L1 GPT |NS |DRAM 2 CHIP 1 |
+ * 0x1081FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x208080000000 |6GB |L1 GPT |NS |DRAM 2 CHIP 2 |
+ * 0x2081FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x308080000000 |6GB |L1 GPT |NS |DRAM 2 CHIP 3 |
+ * 0x3081FFFFFFFF | | | | |
+ * =====================================================================
+ */
+
+/*******************************************************************************
+ * Multichip config
+ ******************************************************************************/
+
+#define NRD_MC_BASE(base, n) (NRD_REMOTE_CHIP_MEM_OFFSET(n) + base)
+
+/*******************************************************************************
+ * PAS mappings
+ ******************************************************************************/
+
+#define NRD_PAS_SHARED_SRAM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SHARED_SRAM_BASE, \
+ NRD_CSS_SHARED_SRAM_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_SYSTEM_NCI \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SYSTEM_NCI_BASE, \
+ NRD_CSS_SYSTEM_NCI_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_DEBUG_NIC \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_DEBUG_NIC_BASE, \
+ NRD_CSS_DEBUG_NIC_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_NS_UART \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_NS_UART_BASE, \
+ NRD_CSS_NS_UART_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_REALM_UART \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_REALM_UART_BASE, \
+ NRD_CSS_REALM_UART_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_AP_NS_WDOG \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_NS_WDOG_BASE, \
+ NRD_CSS_AP_NS_WDOG_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_AP_ROOT_WDOG \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_ROOT_WDOG_BASE, \
+ NRD_CSS_AP_ROOT_WDOG_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_AP_SECURE_WDOG \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_SECURE_WDOG_BASE, \
+ NRD_CSS_AP_SECURE_WDOG_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_SECURE_SRAM_ERB_AP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SECURE_SRAM_ERB_AP_BASE, \
+ NRD_CSS_SECURE_SRAM_ERB_AP_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_NS_SRAM_ERB_AP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_NS_SRAM_ERB_AP_BASE, \
+ NRD_CSS_NS_SRAM_ERB_AP_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_ROOT_SRAM_ERB_AP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_ROOT_SRAM_ERB_AP_BASE, \
+ NRD_CSS_ROOT_SRAM_ERB_AP_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_REALM_SRAM_ERB_AP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_REALM_SRAM_ERB_AP_BASE, \
+ NRD_CSS_REALM_SRAM_ERB_AP_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_SECURE_SRAM_ERB_SCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SECURE_SRAM_ERB_SCP_BASE, \
+ NRD_CSS_SECURE_SRAM_ERB_SCP_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_NS_SRAM_ERB_SCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_NS_SRAM_ERB_SCP_BASE, \
+ NRD_CSS_NS_SRAM_ERB_SCP_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_ROOT_SRAM_ERB_SCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_ROOT_SRAM_ERB_SCP_BASE, \
+ NRD_CSS_ROOT_SRAM_ERB_SCP_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_REALM_SRAM_ERB_SCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_REALM_SRAM_ERB_SCP_BASE, \
+ NRD_CSS_REALM_SRAM_ERB_SCP_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_SECURE_SRAM_ERB_MCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SECURE_SRAM_ERB_MCP_BASE, \
+ NRD_CSS_SECURE_SRAM_ERB_MCP_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_NS_SRAM_ERB_MCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_NS_SRAM_ERB_MCP_BASE, \
+ NRD_CSS_NS_SRAM_ERB_MCP_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_ROOT_SRAM_ERB_MCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_ROOT_SRAM_ERB_MCP_BASE, \
+ NRD_CSS_ROOT_SRAM_ERB_MCP_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_REALM_SRAM_ERB_MCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_REALM_SRAM_ERB_MCP_BASE, \
+ NRD_CSS_REALM_SRAM_ERB_MCP_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_SECURE_SRAM_ERB_RSE \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SECURE_SRAM_ERB_RSE_BASE, \
+ NRD_CSS_SECURE_SRAM_ERB_RSE_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_NS_SRAM_ERB_RSE \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_NS_SRAM_ERB_RSE_BASE, \
+ NRD_CSS_NS_SRAM_ERB_RSE_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_ROOT_SRAM_ERB_RSE \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_ROOT_SRAM_ERB_RSE_BASE, \
+ NRD_CSS_ROOT_SRAM_ERB_RSE_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_REALM_SRAM_ERB_RSE \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_REALM_SRAM_ERB_RSE_BASE, \
+ NRD_CSS_REALM_SRAM_ERB_RSE_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_RSE_SECURE_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_RSE_NS_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_RSE_NS_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_RSE_NS_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_SCP_SECURE_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_SCP_NS_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SCP_NS_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_SCP_NS_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_MCP_SECURE_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_MCP_NS_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_MCP_NS_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_MCP_NS_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_AP_SCP_ROOT_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_SCP_ROOT_MHU_BASE, \
+ NRD_CSS_AP_SCP_ROOT_MHU_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_AP_MCP_NS_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_MCP_NS_MHU_BASE, \
+ NRD_CSS_AP_MCP_NS_MHU_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_AP_MCP_SECURE_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_MCP_SECURE_MHU_BASE, \
+ NRD_CSS_AP_MCP_SECURE_MHU_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_AP_MCP_ROOT_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_MCP_ROOT_MHU_BASE, \
+ NRD_CSS_AP_MCP_ROOT_MHU_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_AP_RSE_NS_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_RSE_NS_MHU_BASE, \
+ NRD_CSS_AP_RSE_NS_MHU_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_AP_RSE_SECURE_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_RSE_SECURE_MHU_BASE, \
+ NRD_CSS_AP_RSE_SECURE_MHU_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_AP_RSE_ROOT_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_RSE_ROOT_MHU_BASE, \
+ NRD_CSS_AP_RSE_ROOT_MHU_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_AP_RSE_REALM_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_RSE_REALM_MHU_BASE, \
+ NRD_CSS_AP_RSE_REALM_MHU_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_SCP_MCP_RSE_CROSS_CHIP_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_BASE, \
+ NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_SYNCNT_MSTUPDTVAL_ADDR \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_BASE, \
+ NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_STM_SYSTEM_ITS \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_STM_SYSTEM_ITS_BASE, \
+ NRD_CSS_STM_SYSTEM_ITS_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_SCP_MCP_RSE_SHARED_SRAM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_BASE, \
+ NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_GIC \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_GIC_BASE, \
+ NRD_CSS_GIC_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_NS_DRAM \
+ GPT_MAP_REGION_GRANULE( \
+ ARM_NS_DRAM1_BASE, \
+ ARM_NS_DRAM1_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM1_CHIP1 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM1_BASE, 1), \
+ ARM_DRAM1_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM1_CHIP2 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM1_BASE, 2), \
+ ARM_DRAM1_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM1_CHIP3 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM1_BASE, 3), \
+ ARM_DRAM1_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_RMM \
+ GPT_MAP_REGION_GRANULE( \
+ ARM_REALM_BASE, \
+ ARM_REALM_SIZE + \
+ ARM_EL3_RMM_SHARED_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_L1GPT \
+ GPT_MAP_REGION_GRANULE( \
+ ARM_L1_GPT_BASE, \
+ ARM_L1_GPT_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_CMN \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_CMN_BASE, \
+ NRD_CSS_CMN_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_LCP_PERIPHERAL \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_LCP_PERIPHERAL_BASE, \
+ NRD_CSS_LCP_PERIPHERAL_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_DDR_IO \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_DDR_IO_BASE, \
+ NRD_CSS_DDR_IO_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_SMMU_NCI_IO \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SMMU_NCI_IO_BASE, \
+ NRD_CSS_SMMU_NCI_IO_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_GPC_SMMUV3 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_GPC_SMMUV3_BASE, \
+ NRD_CSS_GPC_SMMUV3_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_DRAM2_CHIP0 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 0), \
+ ARM_DRAM2_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM2_CHIP1 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 1), \
+ ARM_DRAM2_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM2_CHIP2 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 2), \
+ ARM_DRAM2_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM2_CHIP3 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 3), \
+ ARM_DRAM2_SIZE, \
+ GPT_GPI_NS)
+
+#endif /* NRD_PAS_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
new file mode 100644
index 0000000..0dce512
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
@@ -0,0 +1,756 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the platform port definitions for the
+ * third generation of platforms.
+ */
+
+#ifndef NRD_PLAT_ARM_DEF3_H
+#define NRD_PLAT_ARM_DEF3_H
+
+#include <common/tbbr/tbbr_img_def.h>
+
+#ifndef __ASSEMBLER__
+#include <lib/mmio.h>
+#endif /* __ASSEMBLER__ */
+
+#include <plat/arm/common/arm_spm_def.h>
+#include <plat/common/common_def.h>
+#include <nrd_css_fw_def3.h>
+#include <nrd_ros_fw_def3.h>
+
+/*******************************************************************************
+ * Core count
+ ******************************************************************************/
+
+#define PLATFORM_CORE_COUNT (NRD_CHIP_COUNT * \
+ PLAT_ARM_CLUSTER_COUNT * \
+ NRD_MAX_CPUS_PER_CLUSTER * \
+ NRD_MAX_PE_PER_CPU)
+
+/*******************************************************************************
+ * PA/VA config
+ ******************************************************************************/
+
+#ifdef __aarch64__
+#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
+ NRD_CHIP_COUNT)
+#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
+ NRD_CHIP_COUNT)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#endif
+
+/*******************************************************************************
+ * XLAT definitions
+ ******************************************************************************/
+
+/*
+ * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
+ * plat_arm_mmap array defined for each BL stage. In addition to that, on
+ * multi-chip platforms, address regions on each of the remote chips are
+ * also mapped. In BL31, for instance, three address regions on the remote
+ * chips are accessed - secure ram, css device and soc device regions.
+ */
+#if defined(IMAGE_BL31)
+# define PLAT_ARM_MMAP_ENTRIES (9 + ((NRD_CHIP_COUNT - 1) * 3))
+# define MAX_XLAT_TABLES (9 + ((NRD_CHIP_COUNT - 1) * 3))
+#elif defined(IMAGE_BL32)
+# define PLAT_ARM_MMAP_ENTRIES U(8)
+# define MAX_XLAT_TABLES U(5)
+#elif defined(IMAGE_BL2)
+# define PLAT_ARM_MMAP_ENTRIES (16 + (NRD_CHIP_COUNT - 1))
+# define MAX_XLAT_TABLES (11 + ((NRD_CHIP_COUNT - 1) * 2))
+#else
+# define PLAT_ARM_MMAP_ENTRIES U(7)
+# define MAX_XLAT_TABLES U(7)
+#endif
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
+
+#define PLAT_ARM_MAX_BL1_RW_SIZE NRD_CSS_BL1_RW_SIZE
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth. Additional 8KiB space is added per chip in
+ * order to accommodate the additional level of translation required for "TZC"
+ * peripheral access which lies in >4TB address space.
+ *
+ */
+#define PLAT_ARM_MAX_BL2_SIZE (NRD_CSS_BL2_SIZE + \
+ ((NRD_CHIP_COUNT - 1) * 0x2000))
+
+#define PLAT_ARM_MAX_BL31_SIZE (NRD_CSS_BL31_SIZE + \
+ PLAT_ARM_MAX_BL2_SIZE + \
+ PLAT_ARM_MAX_BL1_RW_SIZE)
+
+/*******************************************************************************
+ * BL31 plat param
+ ******************************************************************************/
+
+/* Special value used to verify platform parameters from BL2 to BL31 */
+#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
+
+/*******************************************************************************
+ * Stack sizes
+ ******************************************************************************/
+
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE UL(0x1000)
+# else
+# define PLATFORM_STACK_SIZE UL(0x440)
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE UL(0x1000)
+# else
+# define PLATFORM_STACK_SIZE UL(0x400)
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE UL(0x400)
+#elif defined(IMAGE_BL31)
+# if SPM_MM
+# define PLATFORM_STACK_SIZE UL(0x500)
+# else
+# define PLATFORM_STACK_SIZE UL(0x400)
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE UL(0x440)
+#endif
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define ARM_CONSOLE_BAUDRATE (115200)
+
+/* UART related constants */
+#define PLAT_ARM_BOOT_UART_BASE NRD_CSS_SECURE_UART_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_RUN_UART_BASE NRD_CSS_SECURE_UART_BASE
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_CRASH_UART_BASE NRD_CSS_SECURE_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
+
+/*******************************************************************************
+ * System counter and timer config
+ ******************************************************************************/
+
+#define ARM_SYS_CNTCTL_BASE NRD_CSS_GENERIC_REFCLK_BASE
+#define ARM_SYS_CNTREAD_BASE NRD_CSS_CNTCTL_REFCLK_READFRAME_BASE
+#define ARM_SYS_TIMCTL_BASE NRD_CSS_SYS_TIMCTL_BASE
+#define ARM_SYS_CNT_BASE_S NRD_CSS_SECURE_TIMER_CTL_BASE
+#define ARM_SYS_CNT_BASE_NS NRD_CSS_NS_TIMER_CTL_BASE
+
+/*******************************************************************************
+ * SRAM and DRAM config for FW
+ ******************************************************************************/
+
+#define PLAT_ARM_TRUSTED_ROM_BASE NRD_CSS_SECURE_ROM_BASE
+#define PLAT_ARM_TRUSTED_ROM_SIZE NRD_CSS_SECURE_ROM_SIZE
+
+#define PLAT_ARM_DRAM2_BASE NRD_CSS_DRAM2_BASE
+#define PLAT_ARM_DRAM2_SIZE NRD_CSS_DRAM2_SIZE
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE NRD_CSS_SECURE_SRAM_SIZE
+
+#define PLAT_ARM_NSTIMER_FRAME_ID (0)
+
+#define PLAT_ARM_NSRAM_BASE NRD_CSS_NS_SRAM_BASE
+#define PLAT_ARM_NSRAM_SIZE NRD_CSS_NS_SRAM_SIZE
+
+/*******************************************************************************
+ * Power config
+ ******************************************************************************/
+
+/*
+ * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
+ * power levels have a 1:1 mapping with the MPIDR affinity levels.
+ */
+#define ARM_PWR_LVL0 MPIDR_AFFLVL0
+#define ARM_PWR_LVL1 MPIDR_AFFLVL1
+#define ARM_PWR_LVL2 MPIDR_AFFLVL2
+#define ARM_PWR_LVL3 MPIDR_AFFLVL3
+
+/* Local power state for power domains in Run state. */
+#define ARM_LOCAL_STATE_RUN U(0)
+/* Local power state for retention. Valid only for CPU power domains */
+#define ARM_LOCAL_STATE_RET U(1)
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains
+ */
+#define ARM_LOCAL_STATE_OFF U(2)
+/*
+ * This macro defines the deepest retention state possible. A higher state
+ * id will represent an invalid or a power down state.
+ */
+#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
+
+#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
+#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
+
+/*******************************************************************************
+ * MHU config
+ ******************************************************************************/
+
+#define PLAT_CSS_MHU_BASE NRD_CSS_AP_SCP_SECURE_MHU_BASE
+#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
+
+/*******************************************************************************
+ * Cache config
+ ******************************************************************************/
+
+#define ARM_CACHE_WRITEBACK_SHIFT U(6)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
+
+/*******************************************************************************
+ * SCMI config
+ ******************************************************************************/
+
+/* Number of SCMI channels on the platform */
+#define PLAT_ARM_SCMI_CHANNEL_COUNT NRD_CHIP_COUNT
+
+/*******************************************************************************
+ * GIC/EHF config
+ ******************************************************************************/
+
+/* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */
+#define PLAT_CORE_FAULT_IRQ U(17)
+
+/* ARM platforms use 3 upper bits of secure interrupt priority */
+#define PLAT_PRI_BITS U(3)
+
+#if ENABLE_FEAT_RAS && FFH_SUPPORT
+#define PLAT_RAS_PRI U(0x10)
+#endif
+
+#if ENABLE_FEAT_RAS && FFH_SUPPORT
+#define PLAT_SP_PRI PLAT_RAS_PRI
+#else
+#define PLAT_SP_PRI U(0x10)
+#endif
+
+#define ARM_IRQ_SEC_PHY_TIMER U(29)
+
+#define ARM_IRQ_SEC_SGI_0 U(8)
+#define ARM_IRQ_SEC_SGI_1 U(9)
+#define ARM_IRQ_SEC_SGI_2 U(10)
+#define ARM_IRQ_SEC_SGI_3 U(11)
+#define ARM_IRQ_SEC_SGI_4 U(12)
+#define ARM_IRQ_SEC_SGI_5 U(13)
+#define ARM_IRQ_SEC_SGI_6 U(14)
+#define ARM_IRQ_SEC_SGI_7 U(15)
+
+#define ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define ARM_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE)
+
+#define ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE)
+
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+
+#define PLAT_ARM_GICD_BASE NRD_CSS_GIC_BASE
+#if (NRD_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x00100000)
+#else
+#define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x001C0000)
+#endif
+
+/*******************************************************************************
+ * SDEI config
+ ******************************************************************************/
+
+#define PLAT_SDEI_CRITICAL_PRI U(0x60)
+#define PLAT_SDEI_NORMAL_PRI U(0x70)
+
+/* SGI used for SDEI signalling */
+#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
+
+#if SDEI_IN_FCONF
+/* ARM SDEI dynamic private event max count */
+#define ARM_SDEI_DP_EVENT_MAX_CNT U(3)
+
+/* ARM SDEI dynamic shared event max count */
+#define ARM_SDEI_DS_EVENT_MAX_CNT U(3)
+#else
+/* ARM SDEI dynamic private event numbers */
+#define ARM_SDEI_DP_EVENT_0 UL(1000)
+#define ARM_SDEI_DP_EVENT_1 UL(1001)
+#define ARM_SDEI_DP_EVENT_2 UL(1002)
+
+/* ARM SDEI dynamic shared event numbers */
+#define ARM_SDEI_DS_EVENT_0 UL(2000)
+#define ARM_SDEI_DS_EVENT_1 UL(2001)
+#define ARM_SDEI_DS_EVENT_2 UL(2002)
+
+#define ARM_SDEI_PRIVATE_EVENTS \
+ SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, \
+ SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, \
+ SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
+
+#define ARM_SDEI_SHARED_EVENTS \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, \
+ SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, \
+ SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, \
+ SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
+#endif /* SDEI_IN_FCONF */
+
+/*******************************************************************************
+ * SDS config
+ ******************************************************************************/
+
+/* SDS ID for unusable CPU MPID list structure */
+#define SDS_ISOLATED_CPU_LIST_ID U(128)
+
+/* Index of SDS region used in the communication with SCP */
+#define SDS_SCP_AP_REGION_ID U(0)
+
+/*******************************************************************************
+ * SMMUv3 Config
+ ******************************************************************************/
+
+/* SMMUv3 root offset register */
+#define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0xA0000)
+
+/*******************************************************************************
+ * Platform type identification macro
+ ******************************************************************************/
+
+/* Platform ID related accessors */
+#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F)
+#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00)
+#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00)
+#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08)
+#define BOARD_CSS_PLAT_TYPE_RTL U(0x00)
+#define BOARD_CSS_PLAT_TYPE_FPGA U(0x01)
+#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02)
+#define BOARD_CSS_PLAT_TYPE_FVP U(0x03)
+
+#ifndef __ASSEMBLER__
+#define BOARD_CSS_GET_PLAT_TYPE(addr) \
+ ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
+ >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
+#endif /* __ASSEMBLER__ */
+
+/* Platform ID address */
+#define BOARD_CSS_PLAT_ID_REG_ADDR NRD_ROS_PLATFORM_PERIPH_BASE + \
+ UL(0x00FE00E0)
+
+/*******************************************************************************
+ * Flash config
+ ******************************************************************************/
+
+#define MAX_IO_DEVICES U(3)
+#define MAX_IO_HANDLES U(4)
+
+#define V2M_SYS_LED U(0x8)
+
+#define V2M_SYS_LED_SS_SHIFT U(0)
+#define V2M_SYS_LED_EL_SHIFT U(1)
+#define V2M_SYS_LED_EC_SHIFT U(3)
+
+#define V2M_SYS_LED_SS_MASK U(0x01)
+#define V2M_SYS_LED_EL_MASK U(0x03)
+#define V2M_SYS_LED_EC_MASK U(0x1f)
+
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
+
+#define V2M_SYSREGS_BASE NRD_ROS_SYSTEM_PERIPH_BASE + \
+ UL(0x00010000)
+#define V2M_FLASH0_BASE NRD_ROS_SMC0_BASE
+#define V2M_FLASH0_SIZE NRD_ROS_SMC0_SIZE
+#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
+
+#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
+ V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+/*******************************************************************************
+ * ROS peripheral config
+ ******************************************************************************/
+
+/* Non-volatile counters */
+#define SOC_TRUSTED_NVCTR_BASE NRD_ROS_PLATFORM_PERIPH_BASE + \
+ UL(0x00E70000)
+#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000)
+#define TFW_NVCTR_SIZE U(4)
+#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004)
+#define NTFW_CTR_SIZE U(4)
+
+/*******************************************************************************
+ * SRAM layout
+ ******************************************************************************/
+
+/*
+ * Trusted SRAM
+ * 0x00100000 +--------------+
+ * | L0 GPT |
+ * 0x000E0000 +--------------+ loaded by BL2 +----------------+
+ * | BL1 (rw) | <<<<<<<<<<<<< | |
+ * |--------------| <<<<<<<<<<<<< | BL31 NOBITS |
+ * | BL2 | <<<<<<<<<<<<< | |
+ * |--------------| <<<<<<<<<<<<< |----------------|
+ * | | <<<<<<<<<<<<< | BL31 PROGBITS |
+ * | | +----------------+
+ * +--------------+
+ * | CONFIG |
+ * 0x0001A000 +--------------+
+ * | Shared |
+ * 0x00019000 +--------------+
+ * | BL1 (ro) |
+ * 0x00000000 +--------------+
+ */
+
+/*******************************************************************************
+ * BL1 RO specifics
+ ******************************************************************************/
+
+/*
+ * SRAM region to store BL1 code and RO. This has been carved out at the bottom
+ * of SRAM
+ */
+
+#define BL1_RO_BASE NRD_CSS_BL1_RO_BASE
+#define BL1_RO_LIMIT (NRD_CSS_BL1_RO_BASE \
+ + NRD_CSS_BL1_RO_SIZE)
+
+/*******************************************************************************
+ * L0 GPT specifics
+ ******************************************************************************/
+
+/*
+ * L0 GPT has to be aligned to its size. In order to avoid holes due to
+ * alignment, place L0 GPT at the top of SRAM.
+ */
+#define ARM_L0_GPT_SIZE UL(0x00020000) /* 128KB */
+#define ARM_L0_GPT_BASE NRD_CSS_SHARED_SRAM_SIZE - \
+ ARM_L0_GPT_SIZE
+
+#define ARM_L0_GPT_LIMIT (ARM_L0_GPT_BASE + ARM_L0_GPT_SIZE)
+
+/*******************************************************************************
+ * Arm shared RAM specifics
+ ******************************************************************************/
+
+#define ARM_SHARED_RAM_BASE (NRD_CSS_BL1_RO_BASE + \
+ NRD_CSS_BL1_RO_SIZE)
+#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
+
+/*******************************************************************************
+ * Arm BL RAM specifics
+ ******************************************************************************/
+
+/*Rest of SRAM till L0 GPT base */
+#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
+ ARM_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_SIZE (ARM_L0_GPT_BASE - \
+ ARM_BL_RAM_BASE)
+
+/*******************************************************************************
+ * FW_CONFIG specifics
+ ******************************************************************************/
+
+/*
+ * To enable FW_CONFIG to be loaded by BL1, define the corresponding base
+ * and limit. Leave enough space of BL2 meminfo.
+ */
+#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
+#define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \
+ + (PAGE_SIZE / 2U))
+
+/*
+ * Boot parameters passed from BL2 to BL31/BL32 are stored here
+ */
+#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT)
+#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
+ + (PAGE_SIZE / 2U))
+
+/*
+ * Define limit of firmware configuration memory:
+ * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
+ */
+#define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2)
+#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE)
+
+/*******************************************************************************
+ * BL1 RW specifics
+ ******************************************************************************/
+
+#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
+ ARM_BL_RAM_SIZE - \
+ PLAT_ARM_MAX_BL1_RW_SIZE)
+#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
+ ARM_BL_RAM_SIZE)
+
+/*******************************************************************************
+ * BL2 specific defines.
+ ******************************************************************************/
+
+/* Put BL2 just below BL1. */
+#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
+#define BL2_LIMIT BL1_RW_BASE
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+
+/* Keep BL31 below BL2 in the Trusted SRAM.*/
+#define BL31_BASE ((ARM_BL_RAM_BASE + \
+ ARM_BL_RAM_SIZE) - \
+ PLAT_ARM_MAX_BL31_SIZE)
+#define BL31_PROGBITS_LIMIT BL2_BASE
+#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+
+/*
+ * The max number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#define ARM_BL_REGIONS 7
+
+#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
+ ARM_BL_REGIONS)
+
+/*******************************************************************************
+ * DRAM layout
+ ******************************************************************************/
+
+/*
+ * The top 100MB of DRAM1 is configured as follows:
+ * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled
+ * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM
+ * - REALM DRAM: Reserved for Realm world if RME is enabled
+ *
+ * DRAM layout
+ * +------------------+
+ * | REALM (RMM) |
+ * | (32MB - 4KB) |
+ * +------------------+
+ * | |
+ * | TF-A <-> RMM |
+ * | SHARED (4KB) |
+ * +------------------+
+ * | L1 GPT |
+ * | |
+ * DRAM1 End +------------------+
+ */
+
+/* Number of DRAM banks */
+#if (NRD_PLATFORM_VARIANT == 2)
+#define ARM_DRAM_NUM_BANKS U(8)
+#else
+#define ARM_DRAM_NUM_BANKS U(2)
+#endif
+
+/*******************************************************************************
+ * DRAM bank1 specific defines.
+ ******************************************************************************/
+
+/* Bank-1 DRAM */
+#define ARM_DRAM1_BASE UL(0x80000000)
+#define ARM_DRAM1_SIZE UL(0x80000000)
+#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
+ ARM_DRAM1_SIZE - 1U)
+
+/*******************************************************************************
+ * DRAM bank2 specific defines.
+ ******************************************************************************/
+
+/* Bank-2 DRAM */
+#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
+#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
+#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
+ ARM_DRAM2_SIZE - 1U)
+
+/*******************************************************************************
+ * L1GPT specific defines.
+ ******************************************************************************/
+
+/* 2MB per L1 entry, PPS - 48 bits, PGS - 4KB, L0GPTSZ - 16GB */
+#define ARM_L1_GPT_SIZE (UL(40 * 1024 * 1024) + \
+ ((NRD_CHIP_COUNT - 1) * \
+ (4 * 1024 * 1024)))
+
+#define ARM_L1_GPT_BASE (ARM_DRAM1_BASE + \
+ ARM_DRAM1_SIZE - \
+ ARM_L1_GPT_SIZE)
+#define ARM_L1_GPT_END (ARM_L1_GPT_BASE + \
+ ARM_L1_GPT_SIZE - 1U)
+
+/*******************************************************************************
+ * "RMM TF-A shared region" specific defines.
+ ******************************************************************************/
+
+/* PLAT_ARM_EL3_RMM_SHARED_SIZE */
+#define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */
+
+#define ARM_EL3_RMM_SHARED_BASE (ARM_L1_GPT_BASE - \
+ ARM_EL3_RMM_SHARED_SIZE)
+
+#define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \
+ ARM_EL3_RMM_SHARED_SIZE - 1U)
+
+/*******************************************************************************
+ * RMM specific defines.
+ ******************************************************************************/
+
+/* ARM_REALM_SIZE */
+#define ARM_REALM_SIZE (UL(0x02600000) - \
+ ARM_EL3_RMM_SHARED_SIZE)
+#define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \
+ ARM_REALM_SIZE)
+
+#define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U)
+
+#define RMM_BASE (ARM_REALM_BASE)
+#define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE)
+#define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE)
+#define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE)
+
+/*******************************************************************************
+ * NRD_CSS_CARVEOUT_RESERVED region specific defines.
+ ******************************************************************************/
+
+#define NRD_CSS_CARVEOUT_RESERVED_BASE (ARM_DRAM1_BASE + \
+ ARM_DRAM1_SIZE - \
+ NRD_CSS_DRAM1_CARVEOUT_SIZE)
+#define NRD_CSS_CARVEOUT_RESERVED_SIZE (NRD_CSS_DRAM1_CARVEOUT_SIZE - \
+ (ARM_EL3_RMM_SHARED_SIZE + \
+ ARM_REALM_SIZE + \
+ ARM_L1_GPT_SIZE))
+
+#define NRD_CSS_CARVEOUT_RESERVED_END (NRD_CSS_CARVEOUT_RESERVED_BASE +\
+ NRD_CSS_CARVEOUT_RESERVED_SIZE - 1U)
+
+/*******************************************************************************
+ * NS RAM specific defines specific defines.
+ ******************************************************************************/
+
+#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
+#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
+ NRD_CSS_DRAM1_CARVEOUT_SIZE)
+
+#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
+ ARM_NS_DRAM1_SIZE - 1U)
+
+/*******************************************************************************
+ * MMU mapping
+ ******************************************************************************/
+
+#define V2M_MAP_FLASH0_RW \
+ MAP_REGION_FLAT( \
+ V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+
+#define V2M_MAP_FLASH0_RO \
+ MAP_REGION_FLAT( \
+ V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_RO_DATA | EL3_PAS)
+
+#define ARM_MAP_L0_GPT_REGION \
+ MAP_REGION_FLAT( \
+ ARM_L0_GPT_BASE, \
+ ARM_L0_GPT_SIZE, \
+ MT_MEMORY | MT_RW | MT_ROOT)
+
+#define ARM_MAP_BL_CONFIG_REGION \
+ MAP_REGION_FLAT( \
+ ARM_BL_RAM_BASE, \
+ (ARM_FW_CONFIGS_LIMIT - ARM_BL_RAM_BASE), \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#if SEPARATE_CODE_AND_RODATA
+#define ARM_MAP_BL_RO \
+ MAP_REGION_FLAT( \
+ BL_CODE_BASE, \
+ (BL_CODE_END - BL_CODE_BASE), \
+ MT_CODE | EL3_PAS), \
+ MAP_REGION_FLAT( \
+ BL_RO_DATA_BASE, \
+ (BL_RO_DATA_END - BL_RO_DATA_BASE), \
+ MT_RO_DATA | EL3_PAS)
+#else
+#define ARM_MAP_BL_RO \
+ MAP_REGION_FLAT( \
+ BL_CODE_BASE, \
+ (BL_CODE_END - BL_CODE_BASE), \
+ MT_CODE | EL3_PAS)
+#endif
+
+#if USE_COHERENT_MEM
+#define ARM_MAP_BL_COHERENT_RAM \
+ MAP_REGION_FLAT( \
+ BL_COHERENT_RAM_BASE, \
+ BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+#endif
+
+#define ARM_MAP_DRAM2 \
+ MAP_REGION_FLAT( \
+ ARM_DRAM2_BASE, \
+ ARM_DRAM2_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#endif /* NRD_PLAT_ARM_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_def3.h
new file mode 100644
index 0000000..c987621
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_def3.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the RoS specific definitions for the third generation of
+ * platforms.
+ */
+
+#ifndef NRD_ROS_DEF3_H
+#define NRD_ROS_DEF3_H
+
+/*******************************************************************************
+ * RoS memory map related defines
+ ******************************************************************************/
+
+/* System peripherals */
+#define NRD_ROS_SYSTEM_PERIPH_BASE UL(0x0C000000)
+#define NRD_ROS_SYSTEM_PERIPH_SIZE UL(0x02000000)
+
+/* Platform peripherals */
+#define NRD_ROS_PLATFORM_PERIPH_BASE UL(0x0E000000)
+#define NRD_ROS_PLATFORM_PERIPH_SIZE UL(0x02000000)
+
+/* SMC0 */
+#define NRD_ROS_SMC0_BASE UL(0x08000000)
+#define NRD_ROS_SMC0_SIZE UL(0x04000000)
+
+#endif /* NRD_ROS_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_fw_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_fw_def3.h
new file mode 100644
index 0000000..c0fde85
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_fw_def3.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the RoS firmware specific definitions for the
+ * third generation of platforms. RoS (Rest Of System) is used to refer to the
+ * part of the reference design platform that excludes CSS.
+ */
+
+#ifndef NRD_ROS_FW_DEF3_H
+#define NRD_ROS_FW_DEF3_H
+
+#include <nrd_ros_def3.h>
+
+/*******************************************************************************
+ * MMU mapping
+ ******************************************************************************/
+
+#define NRD_ROS_PLATFORM_PERIPH_MMAP \
+ MAP_REGION_FLAT( \
+ NRD_ROS_PLATFORM_PERIPH_BASE, \
+ NRD_ROS_PLATFORM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define NRD_ROS_SYSTEM_PERIPH_MMAP \
+ MAP_REGION_FLAT( \
+ NRD_ROS_SYSTEM_PERIPH_BASE, \
+ NRD_ROS_SYSTEM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define NRD_ROS_V2M_MEM_PROTECT_MMAP \
+ MAP_REGION_FLAT( \
+ PLAT_ARM_MEM_PROT_ADDR, \
+ V2M_FLASH_BLOCK_SIZE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+
+#define NRD_ROS_FLASH0_RO_MMAP \
+ MAP_REGION_FLAT( \
+ V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RO | MT_SECURE)
+
+#endif /* NRD_ROS_FW_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
index 94f80c3..391c68c 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
@@ -28,6 +28,14 @@
#define RD_V2_SID_VER_PART_NUM 0x07F2
#define RD_V2_CONFIG_ID 0x1
+/* SID Version values for RD-Fremont */
+#define RD_FREMONT_SID_VER_PART_NUM 0x07EE
+#define RD_FREMONT_CONFIG_ID 0x0
+
+/* SID Version values for RD-Fremont variants */
+#define RD_FREMONT_CFG1_SID_VER_PART_NUM 0x07F9
+#define RD_FREMONT_CFG2_SID_VER_PART_NUM 0x07EE
+
/* Structure containing Neoverse RD platform variant information */
typedef struct nrd_platform_info {
unsigned int platform_id; /* Part Number of the platform */
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index a22c799..5a7dfb1 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -73,6 +73,52 @@
#endif
};
+static scmi_channel_plat_info_t plat3_rd_scmi_info[] = {
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
+ .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+ },
+ #if (NRD_CHIP_COUNT > 1)
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(1),
+ .db_reg_addr = PLAT_CSS_MHU_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(1) +
+ MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+ },
+ #endif
+ #if (NRD_CHIP_COUNT > 2)
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(2),
+ .db_reg_addr = PLAT_CSS_MHU_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(2) +
+ MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+ },
+ #endif
+ #if (NRD_CHIP_COUNT > 3)
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(3),
+ .db_reg_addr = PLAT_CSS_MHU_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(3) +
+ MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+ },
+ #endif
+};
+
scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
{
if (nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
@@ -85,6 +131,13 @@
panic();
}
return &plat_rd_scmi_info[channel_id];
+ } else if (nrd_plat_info.platform_id == RD_FREMONT_SID_VER_PART_NUM ||
+ nrd_plat_info.platform_id == RD_FREMONT_CFG1_SID_VER_PART_NUM ||
+ nrd_plat_info.platform_id == RD_FREMONT_CFG2_SID_VER_PART_NUM) {
+ if (channel_id >= ARRAY_SIZE(plat3_rd_scmi_info)) {
+ panic();
+ }
+ return &plat3_rd_scmi_info[channel_id];
} else if (nrd_plat_info.platform_id == SGI575_SSC_VER_PART_NUM) {
return &sgi575_scmi_plat_info;
} else {
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat3.c b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
new file mode 100644
index 0000000..7b98052
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <drivers/arm/css/sds.h>
+#include <drivers/arm/sbsa.h>
+#include <lib/utils_def.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+
+/*
+ * Table of regions for different BL stages to map using the MMU.
+ */
+#if IMAGE_BL1
+const mmap_region_t plat_arm_mmap[] = {
+ NRD_CSS_SHARED_RAM_MMAP(0),
+ NRD_ROS_FLASH0_RO_MMAP,
+ NRD_CSS_PERIPH_MMAP(0),
+ NRD_ROS_PLATFORM_PERIPH_MMAP,
+ NRD_ROS_SYSTEM_PERIPH_MMAP,
+ {0}
+};
+#endif /* IMAGE_BL3 */
+
+#if IMAGE_BL2
+const mmap_region_t plat_arm_mmap[] = {
+ NRD_CSS_SHARED_RAM_MMAP(0),
+ NRD_ROS_FLASH0_RO_MMAP,
+#ifdef PLAT_ARM_MEM_PROT_ADDR
+ NRD_ROS_V2M_MEM_PROTECT_MMAP,
+#endif
+ NRD_CSS_PERIPH_MMAP(0),
+ NRD_ROS_PLATFORM_PERIPH_MMAP,
+ NRD_ROS_SYSTEM_PERIPH_MMAP,
+ NRD_CSS_NS_DRAM1_MMAP,
+#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
+ NRD_CSS_BL1_RW_MMAP,
+#endif
+ NRD_CSS_GPT_L1_DRAM_MMAP,
+ NRD_CSS_RMM_REGION_MMAP,
+ {0}
+};
+#endif /* IMAGE_BL2 */
+
+#if IMAGE_BL31
+const mmap_region_t plat_arm_mmap[] = {
+ NRD_CSS_SHARED_RAM_MMAP(0),
+#ifdef PLAT_ARM_MEM_PROT_ADDR
+ NRD_ROS_V2M_MEM_PROTECT_MMAP,
+#endif
+ NRD_CSS_PERIPH_MMAP(0),
+ NRD_ROS_PLATFORM_PERIPH_MMAP,
+ NRD_ROS_SYSTEM_PERIPH_MMAP,
+ NRD_CSS_GPT_L1_DRAM_MMAP,
+ NRD_CSS_EL3_RMM_SHARED_MEM_MMAP,
+ NRD_CSS_GPC_SMMU_SMMUV3_MMAP,
+ {0}
+};
+#endif /* IMAGE_BL31 */
+
+ARM_CASSERT_MMAP
+
+#if TRUSTED_BOARD_BOOT
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+#endif
+
+void plat_arm_secure_wdt_start(void)
+{
+ sbsa_wdog_start(NRD_CSS_AP_SECURE_WDOG_BASE,
+ NRD_CSS_AP_SECURE_WDOG_TIMEOUT);
+}
+
+void plat_arm_secure_wdt_stop(void)
+{
+ sbsa_wdog_stop(NRD_CSS_AP_SECURE_WDOG_BASE);
+}
+
+static sds_region_desc_t nrd_sds_regions[] = {
+ { .base = PLAT_ARM_SDS_MEM_BASE },
+};
+
+sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
+{
+ *region_count = ARRAY_SIZE(nrd_sds_regions);
+
+ return nrd_sds_regions;
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_fw_config.dts
new file mode 100644
index 0000000..62ba0fa
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_fw_config.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/tbbr/tbbr_img_def.h>
+
+/dts-v1/;
+
+/ {
+ dtb-registry {
+ compatible = "fconf,dyn_cfg-dtb_registry";
+
+ tb_fw-config {
+ load-address = <0x0 0x01f300>;
+ max-size = <0x200>;
+ id = <TB_FW_CONFIG_ID>;
+ };
+
+ nt_fw-config {
+ load-address = <0x0 0xF3000000>;
+ max-size = <0x0100000>;
+ id = <NT_FW_CONFIG_ID>;
+ };
+ };
+};
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_nt_fw_config.dts
new file mode 100644
index 0000000..62cad39
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_nt_fw_config.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+/ {
+ /* compatible string */
+ compatible = "arm,rd-fremont";
+
+ /*
+ * Place holder for system-id node with default values. The
+ * value of platform-id and config-id will be set to the
+ * correct values during the BL2 stage of boot.
+ */
+ system-id {
+ platform-id = <0x0>;
+ config-id = <0x0>;
+ multi-chip-mode = <0x0>;
+ };
+};
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_tb_fw_config.dts
new file mode 100644
index 0000000..a4c7c72
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_tb_fw_config.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+ tb_fw-config {
+ compatible = "arm,tb_fw";
+
+ /* Disable authentication for development */
+ disable_auth = <0x0>;
+
+ /*
+ * The following two entries are placeholders for Mbed TLS
+ * heap information. The default values don't matter since
+ * they will be overwritten by BL1.
+ * In case of having shared Mbed TLS heap between BL1 and BL2,
+ * BL1 will populate these two properties with the respective
+ * info about the shared heap. This info will be available for
+ * BL2 in order to locate and re-use the heap.
+ */
+ mbedtls_heap_addr = <0x0 0x0>;
+ mbedtls_heap_size = <0x0>;
+ };
+};
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h
new file mode 100644
index 0000000..b55dbe8
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <plat/arm/css/common/css_def.h>
+#include <nrd_css_fw_def3.h>
+#include <nrd_pas_def3.h>
+#include <nrd_plat_arm_def3.h>
+#include <nrd_ros_fw_def3.h>
+
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
+ ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
+
+/* PE-Cluster count */
+#if (NRD_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_CLUSTER_COUNT U(8)
+#elif (NRD_PLATFORM_VARIANT == 2)
+#define PLAT_ARM_CLUSTER_COUNT U(4)
+#else
+#define PLAT_ARM_CLUSTER_COUNT U(16)
+#endif
+#define NRD_MAX_CPUS_PER_CLUSTER U(1)
+#define NRD_MAX_PE_PER_CPU U(1)
+
+/* Shared RAM*/
+#define NRD_CSS_SHARED_SRAM_SIZE UL(0x000100000)
+
+/* DRAM1 */
+#define NRD_CSS_DRAM1_SIZE ULL(0x80000000)
+
+/* DRAM2 */
+#define NRD_CSS_DRAM2_SIZE ULL(0x180000000)
+
+/* Address bits */
+#define NRD_ADDR_BITS_PER_CHIP U(36) /* 64GB */
+
+/*
+ * In the current implementation, the RoT Service request that requires the
+ * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The
+ * maximum required buffer size is calculated based on the platform-specific
+ * needs of this request.
+ */
+#define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE UL(0x1000)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_mhuv3.h b/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_mhuv3.h
new file mode 100644
index 0000000..400dcc5
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_mhuv3.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RDFREMONT_MHUV3_H
+#define RDFREMONT_MHUV3_H
+
+void mhu_v3_get_secure_device_base(uintptr_t *base, bool sender);
+
+#endif /* RDFREMONT_MHUV3_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_rse_comms.h b/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_rse_comms.h
new file mode 100644
index 0000000..ad1bc23
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_rse_comms.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RDFREMONT_RSE_COMMS_H
+#define RDFREMONT_RSE_COMMS_H
+
+int plat_rse_comms_init(void);
+
+#endif /* RDFREMONT_RSE_COMMS_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk b/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
new file mode 100644
index 0000000..bca6172
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
@@ -0,0 +1,139 @@
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+RD_FREMONT_VARIANTS := 0 1 2
+ifneq ($(NRD_PLATFORM_VARIANT), \
+ $(filter $(NRD_PLATFORM_VARIANT),$(RD_FREMONT_VARIANTS)))
+ $(error "NRD_PLATFORM_VARIANT for RD-FREMONT should be 0, 1, or 2,"
+ "currently set to ${NRD_PLATFORM_VARIANT}.")
+endif
+
+$(eval $(call CREATE_SEQ,SEQ,4))
+ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
+ $(error "Chip count for RD-Fremont-MC should be either $(SEQ) \
+ currently it is set to ${NRD_CHIP_COUNT}.")
+endif
+
+# Build options
+# Major and Minor versions
+override ARM_ARCH_MAJOR := 8
+override ARM_ARCH_MINOR := 7
+
+# Image flags
+override NEED_BL1 := yes
+override NEED_BL2 := yes
+override NEED_BL32 := no
+override NEED_RMM := no
+
+# Misc options
+override CTX_INCLUDE_AARCH32_REGS := 0
+
+# RD-Fremont platform uses GIC-700 which is based on GICv4.1
+GIC_ENABLE_V4_EXTN := 1
+
+# Enable GIC multichip extension only for multichip platforms
+ifeq (${NRD_PLATFORM_VARIANT}, 2)
+GICV3_IMPL_GIC600_MULTICHIP := 1
+endif
+
+# RD-Fremont uses MHUv3
+PLAT_MHU_VERSION := 3
+
+include plat/arm/board/neoverse_rd/common/nrd-common.mk
+include drivers/arm/rse/rse_comms.mk
+include drivers/auth/mbedtls/mbedtls_common.mk
+ifeq (${MEASURED_BOOT},1)
+include drivers/measured_boot/rse/rse_measured_boot.mk
+endif
+
+RDFREMONT_BASE = plat/arm/board/neoverse_rd/platform/rdfremont
+
+PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd3/ \
+ -I${RDFREMONT_BASE}/include/ \
+ -Iinclude/lib/psa
+
+NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_v3.S
+
+# Source files for RD-Fremont variants
+PLAT_BL_COMMON_SOURCES \
+ += ${NRD_COMMON_BASE}/nrd_plat3.c \
+ ${RDFREMONT_BASE}/rdfremont_common.c
+
+PLAT_MEASURED_BOOT_SOURCES \
+ := ${MEASURED_BOOT_SOURCES} \
+ ${RSE_COMMS_SOURCES} \
+ ${RDFREMONT_BASE}/rdfremont_common_measured_boot.c \
+ lib/psa/measured_boot.c
+
+BL1_SOURCES += ${NRD_CPU_SOURCES} \
+ ${RDFREMONT_BASE}/rdfremont_err.c \
+ ${RDFREMONT_BASE}/rdfremont_mhuv3.c
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+BL1_SOURCES += ${RDFREMONT_BASE}/rdfremont_trusted_boot.c
+endif
+ifeq (${MEASURED_BOOT},1)
+BL1_SOURCES += ${PLAT_MEASURED_BOOT_SOURCES} \
+ ${RDFREMONT_BASE}/rdfremont_bl1_measured_boot.c
+endif
+
+BL2_SOURCES += ${RDFREMONT_BASE}/rdfremont_bl2_setup.c \
+ ${RDFREMONT_BASE}/rdfremont_err.c \
+ ${RDFREMONT_BASE}/rdfremont_mhuv3.c \
+ ${RDFREMONT_BASE}/rdfremont_security.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+BL2_SOURCES += ${RDFREMONT_BASE}/rdfremont_trusted_boot.c
+endif
+ifeq (${MEASURED_BOOT},1)
+BL2_SOURCES += ${PLAT_MEASURED_BOOT_SOURCES} \
+ ${RDFREMONT_BASE}/rdfremont_bl2_measured_boot.c
+endif
+
+BL31_SOURCES += ${NRD_CPU_SOURCES} \
+ ${MBEDTLS_SOURCES} \
+ ${RSE_COMMS_SOURCES} \
+ ${RDFREMONT_BASE}/rdfremont_bl31_setup.c \
+ ${RDFREMONT_BASE}/rdfremont_mhuv3.c \
+ ${RDFREMONT_BASE}/rdfremont_topology.c \
+ ${RDFREMONT_BASE}/rdfremont_plat_attest_token.c \
+ ${RDFREMONT_BASE}/rdfremont_realm_attest_key.c \
+ drivers/arm/smmu/smmu_v3.c \
+ drivers/cfi/v2m/v2m_flash.c \
+ lib/psa/cca_attestation.c \
+ lib/psa/delegated_attestation.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_dyn_cfg.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+ifeq (${NRD_PLATFORM_VARIANT}, 2)
+BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
+endif
+
+# XLAT options for RD-Fremont variants
+BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
+BL2_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
+
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES += ${RDFREMONT_BASE}/fdts/${PLAT}_fw_config.dts \
+ ${RDFREMONT_BASE}/fdts/${PLAT}_tb_fw_config.dts \
+ ${RDFREMONT_BASE}/fdts/${PLAT}_nt_fw_config.dts
+
+FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
+TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
+NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
+
+# Add the FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
+# Add the NT_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
+
+# Features for RD-Fremont variants
+override ENABLE_FEAT_MPAM := 2
+override ENABLE_FEAT_AMU := 2
+override ENABLE_SVE_FOR_SWD := 1
+override ENABLE_SVE_FOR_NS := 2
+override ENABLE_FEAT_MTE2 := 2
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl1_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl1_measured_boot.c
new file mode 100644
index 0000000..92e96c2
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl1_measured_boot.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <drivers/arm/rse_comms.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
+#include <lib/psa/measured_boot.h>
+#include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
+
+#include <nrd_plat.h>
+#include <rdfremont_rse_comms.h>
+
+/*
+ * Platform specific table with image IDs and metadata. Intentionally not a
+ * const struct, some members might set by bootloaders during trusted boot.
+ */
+struct rse_mboot_metadata rdfremont_rse_mboot_metadata[] = {
+ {
+ .id = FW_CONFIG_ID,
+ .slot = U(8),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_FW_CONFIG_STRING,
+ .lock_measurement = false
+ },
+ {
+ .id = TB_FW_CONFIG_ID,
+ .slot = U(9),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_TB_FW_CONFIG_STRING,
+ .lock_measurement = false
+ },
+ {
+ .id = BL2_IMAGE_ID,
+ .slot = U(10),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_BL2_IMAGE_STRING,
+ .lock_measurement = false
+ },
+ {
+ .id = RSE_MBOOT_INVALID_ID
+ }
+};
+
+void bl1_plat_mboot_init(void)
+{
+ /* Initialize the communication channel between AP and RSE */
+ (void)plat_rse_comms_init();
+
+ rse_measured_boot_init(rdfremont_rse_mboot_metadata);
+}
+
+void bl1_plat_mboot_finish(void)
+{
+ /* Nothing to do. */
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_measured_boot.c
new file mode 100644
index 0000000..570c33a
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_measured_boot.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <drivers/arm/rse_comms.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
+#include <lib/psa/measured_boot.h>
+#include <plat/common/common_def.h>
+#include <platform_def.h>
+
+#include <nrd_plat.h>
+#include <rdfremont_rse_comms.h>
+
+/*
+ * Platform specific table with image IDs and metadata. Intentionally not a
+ * const struct, some members might set by bootloaders during trusted boot.
+ */
+struct rse_mboot_metadata rdfremont_rse_mboot_metadata[] = {
+ {
+ .id = BL31_IMAGE_ID,
+ .slot = U(11),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_BL31_IMAGE_STRING,
+ .lock_measurement = false
+ },
+ {
+ .id = HW_CONFIG_ID,
+ .slot = U(12),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_HW_CONFIG_STRING,
+ .lock_measurement = false
+ },
+ {
+ .id = SOC_FW_CONFIG_ID,
+ .slot = U(13),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_SOC_FW_CONFIG_STRING,
+ .lock_measurement = false
+ },
+#if ENABLE_RME
+ {
+ .id = RMM_IMAGE_ID,
+ .slot = U(14),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_RMM_IMAGE_STRING,
+ .lock_measurement = false
+ },
+#endif /* ENABLE_RME */
+ {
+ .id = RSE_MBOOT_INVALID_ID
+ }
+};
+
+void bl2_plat_mboot_init(void)
+{
+ /* Initialize the communication channel between AP and RSE */
+ (void)plat_rse_comms_init();
+
+ rse_measured_boot_init(rdfremont_rse_mboot_metadata);
+}
+
+void bl2_plat_mboot_finish(void)
+{
+ /* Nothing to do. */
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_setup.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_setup.c
new file mode 100644
index 0000000..8dac8d3
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_setup.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/gpt_rme/gpt_rme.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <nrd_plat.h>
+
+/*
+ * The GPT library might modify the gpt regions structure to optimize
+ * the layout, so the array cannot be constant.
+ */
+static pas_region_t pas_regions[] = {
+ NRD_PAS_SHARED_SRAM,
+ NRD_PAS_SYSTEM_NCI,
+ NRD_PAS_DEBUG_NIC,
+ NRD_PAS_NS_UART,
+ NRD_PAS_REALM_UART,
+ NRD_PAS_AP_NS_WDOG,
+ NRD_PAS_AP_ROOT_WDOG,
+ NRD_PAS_AP_SECURE_WDOG,
+ NRD_PAS_SECURE_SRAM_ERB_AP,
+ NRD_PAS_NS_SRAM_ERB_AP,
+ NRD_PAS_ROOT_SRAM_ERB_AP,
+ NRD_PAS_REALM_SRAM_ERB_AP,
+ NRD_PAS_SECURE_SRAM_ERB_SCP,
+ NRD_PAS_NS_SRAM_ERB_SCP,
+ NRD_PAS_ROOT_SRAM_ERB_SCP,
+ NRD_PAS_REALM_SRAM_ERB_SCP,
+ NRD_PAS_SECURE_SRAM_ERB_MCP,
+ NRD_PAS_NS_SRAM_ERB_MCP,
+ NRD_PAS_ROOT_SRAM_ERB_MCP,
+ NRD_PAS_REALM_SRAM_ERB_MCP,
+ NRD_PAS_SECURE_SRAM_ERB_RSE,
+ NRD_PAS_NS_SRAM_ERB_RSE,
+ NRD_PAS_ROOT_SRAM_ERB_RSE,
+ NRD_PAS_REALM_SRAM_ERB_RSE,
+ NRD_PAS_RSE_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_RSE_NS_SRAM_ERB_RSM,
+ NRD_PAS_SCP_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_SCP_NS_SRAM_ERB_RSM,
+ NRD_PAS_MCP_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_MCP_NS_SRAM_ERB_RSM,
+ NRD_PAS_AP_SCP_ROOT_MHU,
+ NRD_PAS_AP_MCP_NS_MHU,
+ NRD_PAS_AP_MCP_SECURE_MHU,
+ NRD_PAS_AP_MCP_ROOT_MHU,
+ NRD_PAS_AP_RSE_NS_MHU,
+ NRD_PAS_AP_RSE_SECURE_MHU,
+ NRD_PAS_AP_RSE_ROOT_MHU,
+ NRD_PAS_AP_RSE_REALM_MHU,
+ NRD_PAS_SCP_MCP_RSE_CROSS_CHIP_MHU,
+ NRD_PAS_SYNCNT_MSTUPDTVAL_ADDR,
+ NRD_PAS_STM_SYSTEM_ITS,
+ NRD_PAS_SCP_MCP_RSE_SHARED_SRAM,
+ NRD_PAS_GIC,
+ NRD_PAS_NS_DRAM,
+ NRD_PAS_RMM,
+ NRD_PAS_L1GPT,
+ NRD_PAS_CMN,
+ NRD_PAS_LCP_PERIPHERAL,
+ NRD_PAS_DDR_IO,
+ NRD_PAS_SMMU_NCI_IO,
+ NRD_PAS_DRAM2_CHIP0,
+#if NRD_CHIP_COUNT > 1
+ NRD_PAS_DRAM1_CHIP1,
+ NRD_PAS_DRAM2_CHIP1,
+#endif
+#if NRD_CHIP_COUNT > 2
+ NRD_PAS_DRAM1_CHIP2,
+ NRD_PAS_DRAM2_CHIP2,
+#endif
+#if NRD_CHIP_COUNT > 3
+ NRD_PAS_DRAM1_CHIP3,
+ NRD_PAS_DRAM2_CHIP3
+#endif
+};
+
+static const arm_gpt_info_t arm_gpt_info = {
+ .pas_region_base = pas_regions,
+ .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions),
+ .l0_base = (uintptr_t)ARM_L0_GPT_BASE,
+ .l1_base = (uintptr_t)ARM_L1_GPT_BASE,
+ .l0_size = (size_t)ARM_L0_GPT_SIZE,
+ .l1_size = (size_t)ARM_L1_GPT_SIZE,
+ .pps = GPCCR_PPS_256TB,
+ .pgs = GPCCR_PGS_4K
+};
+
+const arm_gpt_info_t *plat_arm_get_gpt_info(void)
+{
+ return &arm_gpt_info;
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
new file mode 100644
index 0000000..8544930
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/arm/gic600_multichip.h>
+#include <drivers/arm/rse_comms.h>
+#include <drivers/arm/smmu_v3.h>
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <nrd_plat.h>
+#include <nrd_variant.h>
+#include <rdfremont_rse_comms.h>
+
+#if (NRD_PLATFORM_VARIANT == 2)
+static const mmap_region_t rdfremontmc_dynamic_mmap[] = {
+#if NRD_CHIP_COUNT > 1
+ NRD_CSS_SHARED_RAM_MMAP(1),
+ NRD_CSS_PERIPH_MMAP(1),
+#endif
+#if NRD_CHIP_COUNT > 2
+ NRD_CSS_SHARED_RAM_MMAP(2),
+ NRD_CSS_PERIPH_MMAP(2),
+#endif
+#if NRD_CHIP_COUNT > 3
+ NRD_CSS_SHARED_RAM_MMAP(3),
+ NRD_CSS_PERIPH_MMAP(3),
+#endif
+};
+
+static struct gic600_multichip_data rdfremontmc_multichip_data __init = {
+ .rt_owner_base = PLAT_ARM_GICD_BASE,
+ .rt_owner = 0,
+ .chip_count = NRD_CHIP_COUNT,
+ .chip_addrs = {
+ PLAT_ARM_GICD_BASE >> 16,
+#if NRD_CHIP_COUNT > 1
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
+#endif
+#if NRD_CHIP_COUNT > 2
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
+#endif
+#if NRD_CHIP_COUNT > 3
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
+#endif
+ },
+ .spi_ids = {
+ {PLAT_ARM_GICD_BASE, 32, 511},
+#if NRD_CHIP_COUNT > 1
+ {PLAT_ARM_GICD_BASE, 512, 991},
+#endif
+#if NRD_CHIP_COUNT > 2
+ {PLAT_ARM_GICD_BASE, 4096, 4575},
+#endif
+#if NRD_CHIP_COUNT > 3
+ {PLAT_ARM_GICD_BASE, 4576, 5055},
+#endif
+ }
+};
+
+static uintptr_t rdfremontmc_multichip_gicr_frames[] = {
+ /* Chip 0's GICR Base */
+ PLAT_ARM_GICR_BASE,
+#if NRD_CHIP_COUNT > 1
+ /* Chip 1's GICR BASE */
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
+#endif
+#if NRD_CHIP_COUNT > 2
+ /* Chip 2's GICR BASE */
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
+#endif
+#if NRD_CHIP_COUNT > 3
+ /* Chip 3's GICR BASE */
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
+#endif
+ UL(0) /* Zero Termination */
+};
+#endif /* NRD_PLATFORM_VARIANT == 2 */
+
+void bl31_platform_setup(void)
+{
+ /*
+ * Perform SMMUv3 GPT configuration for the GPC SMMU present in system
+ * control block on RD-Fremont platforms. This SMMUv3 initialization is
+ * not fatal.
+ *
+ * Don't perform smmuv3_security_init() for this instance of SMMUv3 as
+ * the global aborts need not be configured to allow the components in
+ * system control block send transations downstream to SMMUv3.
+ */
+ if (smmuv3_init(NRD_CSS_GPC_SMMUV3_BASE) != 0) {
+ WARN("Failed initializing System SMMU.\n");
+ }
+
+#if (NRD_PLATFORM_VARIANT == 2)
+ int ret;
+ unsigned int i;
+
+ if (plat_arm_nrd_get_multi_chip_mode() == 0) {
+ ERROR("Chip Count is %u but multi-chip mode is not enabled\n",
+ NRD_CHIP_COUNT);
+ panic();
+ } else {
+ INFO("Enabling multi-chip support for RD-Fremont variant\n");
+
+ for (i = 0; i < ARRAY_SIZE(rdfremontmc_dynamic_mmap); i++) {
+ ret = mmap_add_dynamic_region(
+ rdfremontmc_dynamic_mmap[i].base_pa,
+ rdfremontmc_dynamic_mmap[i].base_va,
+ rdfremontmc_dynamic_mmap[i].size,
+ rdfremontmc_dynamic_mmap[i].attr);
+ if (ret != 0) {
+ ERROR("Failed to add entry i: %d (ret=%d)\n",
+ i, ret);
+ panic();
+ }
+ }
+
+ plat_arm_override_gicr_frames(
+ rdfremontmc_multichip_gicr_frames);
+ gic600_multichip_init(&rdfremontmc_multichip_data);
+ }
+#endif /* NRD_PLATFORM_VARIANT == 2 */
+ nrd_bl31_common_platform_setup();
+
+ if (plat_rse_comms_init() != 0) {
+ WARN("Failed initializing AP-RSE comms.\n");
+ }
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c
new file mode 100644
index 0000000..31cc2a0
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/arm/gic600_multichip.h>
+#include <drivers/arm/rse_comms.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+#include <nrd_plat.h>
+#include <rdfremont_mhuv3.h>
+#include <rdfremont_rse_comms.h>
+
+unsigned int plat_arm_nrd_get_platform_id(void)
+{
+ return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) &
+ SID_SYSTEM_ID_PART_NUM_MASK;
+}
+
+unsigned int plat_arm_nrd_get_config_id(void)
+{
+ return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
+}
+
+unsigned int plat_arm_nrd_get_multi_chip_mode(void)
+{
+ return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
+ SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
+}
+
+/*
+ * Get a pointer to the RMM-EL3 shared buffer and return it
+ * through the pointer passed as parameter.
+ *
+ * This function returns the size of the shared buffer.
+ */
+size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared)
+{
+ *shared = (uintptr_t)RMM_SHARED_BASE;
+
+ return (size_t)RMM_SHARED_SIZE;
+}
+
+int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
+{
+ uint64_t checksum, num_banks, num_consoles;
+ struct ns_dram_bank *bank_ptr;
+ struct console_info *console_ptr;
+
+ assert(manifest != NULL);
+
+ /* DRAM Bank-1 and Bank-2 */
+ num_banks = 2;
+ assert(num_banks <= ARM_DRAM_NUM_BANKS);
+
+ /* Set number of consoles */
+ num_consoles = NRD_CSS_RMM_CONSOLE_COUNT;
+
+ manifest->version = RMMD_MANIFEST_VERSION;
+ manifest->padding = 0U; /* RES0 */
+ manifest->plat_data = (uintptr_t)NULL;
+ manifest->plat_dram.num_banks = num_banks;
+ manifest->plat_console.num_consoles = num_consoles;
+
+ /*
+ * Boot Manifest structure illustration, with two dram banks and
+ * a single console.
+ *
+ * +----------------------------------------+
+ * | offset | field | comment |
+ * +--------+----------------+--------------+
+ * | 0 | version | 0x00000003 |
+ * +--------+----------------+--------------+
+ * | 4 | padding | 0x00000000 |
+ * +--------+----------------+--------------+
+ * | 8 | plat_data | NULL |
+ * +--------+----------------+--------------+
+ * | 16 | num_banks | |
+ * +--------+----------------+ |
+ * | 24 | banks | plat_dram |
+ * +--------+----------------+ |
+ * | 32 | checksum | |
+ * +--------+----------------+--------------+
+ * | 40 | num_consoles | |
+ * +--------+----------------+ |
+ * | 48 | consoles | plat_console |
+ * +--------+----------------+ |
+ * | 56 | checksum | |
+ * +--------+----------------+--------------+
+ * | 64 | base 0 | |
+ * +--------+----------------+ bank[0] |
+ * | 72 | size 0 | |
+ * +--------+----------------+--------------+
+ * | 80 | base 1 | |
+ * +--------+----------------+ bank[1] |
+ * | 88 | size 1 | |
+ * +--------+----------------+--------------+
+ * | 96 | base | |
+ * +--------+----------------+ |
+ * | 104 | map_pages | |
+ * +--------+----------------+ |
+ * | 112 | name | |
+ * +--------+----------------+ consoles[0] |
+ * | 120 | clk_in_hz | |
+ * +--------+----------------+ |
+ * | 128 | baud_rate | |
+ * +--------+----------------+ |
+ * | 136 | flags | |
+ * +--------+----------------+--------------+
+ */
+
+ bank_ptr = (struct ns_dram_bank *)
+ (((uintptr_t)manifest) + sizeof(*manifest));
+ console_ptr = (struct console_info *)
+ ((uintptr_t)bank_ptr + (num_banks * sizeof(*bank_ptr)));
+
+ manifest->plat_dram.banks = bank_ptr;
+ manifest->plat_console.consoles = console_ptr;
+
+ /* Ensure the manifest is not larger than the shared buffer */
+ assert((sizeof(struct rmm_manifest) +
+ (sizeof(struct console_info) *
+ manifest->plat_console.num_consoles) +
+ (sizeof(struct ns_dram_bank) * manifest->plat_dram.num_banks))
+ <= ARM_EL3_RMM_SHARED_SIZE);
+
+ /* Calculate checksum of plat_dram structure */
+ checksum = num_banks + (uint64_t)bank_ptr;
+
+ /* Store FVP DRAM banks data in Boot Manifest */
+ bank_ptr[0].base = ARM_NS_DRAM1_BASE;
+ bank_ptr[0].size = ARM_NS_DRAM1_SIZE;
+
+ bank_ptr[1].base = ARM_DRAM2_BASE;
+ bank_ptr[1].size = ARM_DRAM2_SIZE;
+
+ /* Update checksum */
+ checksum += bank_ptr[0].base + bank_ptr[0].size + bank_ptr[1].base +
+ bank_ptr[1].size;
+
+ /* Checksum must be 0 */
+ manifest->plat_dram.checksum = ~checksum + 1UL;
+
+ /* Calculate the checksum of the plat_consoles structure */
+ checksum = num_consoles + (uint64_t)console_ptr;
+
+ /* Zero out the console info struct */
+ memset((void *)console_ptr, '\0',
+ sizeof(struct console_info) * num_consoles);
+
+ console_ptr[0].map_pages = 1;
+ console_ptr[0].base = NRD_CSS_RMM_CONSOLE_BASE;
+ console_ptr[0].clk_in_hz = NRD_CSS_RMM_CONSOLE_CLK_IN_HZ;
+ console_ptr[0].baud_rate = NRD_CSS_RMM_CONSOLE_BAUD;
+
+ strlcpy(console_ptr[0].name, NRD_CSS_RMM_CONSOLE_NAME,
+ sizeof(console_ptr[0].name));
+
+ /* Update checksum */
+ checksum += console_ptr[0].base + console_ptr[0].map_pages +
+ console_ptr[0].clk_in_hz + console_ptr[0].baud_rate;
+
+ /* Checksum must be 0 */
+ manifest->plat_console.checksum = ~checksum + 1UL;
+
+ return 0;
+}
+
+int plat_rse_comms_init(void)
+{
+ uintptr_t snd_base, rcv_base;
+
+ /* Get sender and receiver frames for AP-RSE communication */
+ mhu_v3_get_secure_device_base(&snd_base, true);
+ mhu_v3_get_secure_device_base(&rcv_base, false);
+
+ VERBOSE("Initializing the rse_comms now\n");
+ /* Initialize the communication channel between AP and RSE */
+ return rse_comms_init(snd_base, rcv_base);
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common_measured_boot.c
new file mode 100644
index 0000000..e95c544
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common_measured_boot.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <common/desc_image_load.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
+
+extern struct rse_mboot_metadata rdfremont_rse_mboot_metadata[];
+
+struct rse_mboot_metadata *plat_rse_mboot_get_metadata(void)
+{
+ return rdfremont_rse_mboot_metadata;
+}
+
+int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
+{
+ int err;
+
+ /* Calculate image hash and record data in RSE */
+ err = rse_mboot_measure_and_record(rdfremont_rse_mboot_metadata,
+ image_data->image_base,
+ image_data->image_size,
+ image_id);
+ if (err != 0) {
+ ERROR("Measure and record failed for image id %u, err (%i)\n",
+ image_id, err);
+ }
+
+ return err;
+}
+
+int plat_mboot_measure_key(void *pk_oid, void *pk_ptr, unsigned int pk_len)
+{
+ return rse_mboot_set_signer_id(rdfremont_rse_mboot_metadata, pk_oid,
+ pk_ptr, pk_len);
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_err.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_err.c
new file mode 100644
index 0000000..de6cc68
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * rdfremont error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+ while (1) {
+ wfi();
+ }
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_mhuv3.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_mhuv3.c
new file mode 100644
index 0000000..41332cc
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_mhuv3.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include <nrd_css_def3.h>
+#include <nrd_plat.h>
+#include <rdfremont_mhuv3.h>
+
+void mhu_v3_get_secure_device_base(uintptr_t *base, bool sender)
+{
+ if (sender) {
+ *base = AP_RSE_ROOT_MHU_V3_PBX;
+ } else {
+ *base = AP_RSE_ROOT_MHU_V3_MBX;
+ }
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_plat_attest_token.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_plat_attest_token.c
new file mode 100644
index 0000000..188a09f
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_plat_attest_token.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <stdint.h>
+
+#include <cca_attestation.h>
+#include <common/debug.h>
+#include <psa/error.h>
+
+int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
+ uintptr_t hash, size_t hash_size)
+{
+ psa_status_t ret;
+
+ ret = cca_attestation_get_plat_token(buf, len, hash, hash_size);
+ if (ret != PSA_SUCCESS) {
+ ERROR("Unable to fetch CCA attestation token\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_realm_attest_key.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_realm_attest_key.c
new file mode 100644
index 0000000..224c20b
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_realm_attest_key.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <stdint.h>
+
+#include <cca_attestation.h>
+#include <common/debug.h>
+#include <psa/error.h>
+
+int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
+ unsigned int type)
+{
+ psa_status_t ret;
+
+ ret = cca_attestation_get_realm_key(buf, len, type);
+ if (ret != PSA_SUCCESS) {
+ ERROR("Unable to fetch CCA attestation key\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_security.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_security.c
new file mode 100644
index 0000000..a12d3e2
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_security.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Placeholder function to resolve build dependency */
+void plat_arm_security_setup(void)
+{
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c
new file mode 100644
index 0000000..e7931d4
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/arm/css/common/css_pm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ ******************************************************************************/
+const unsigned char rd_fremont_pd_tree_desc[] = {
+ (PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+#if (PLAT_ARM_CLUSTER_COUNT > 4 || \
+ (NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 1))
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+#endif
+#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
+ (NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 2))
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+#endif
+#if (PLAT_ARM_CLUSTER_COUNT > 12 || \
+ (NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 3))
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+#endif
+};
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return rd_fremont_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+#if (NRD_PLATFORM_VARIANT == 2)
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
+#if (NRD_CHIP_COUNT > 1)
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+#if (NRD_CHIP_COUNT > 2)
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+#if (NRD_CHIP_COUNT > 3)
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+};
+#else
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
+#if (NRD_PLATFORM_VARIANT == 0)
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
+#endif
+};
+#endif
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_trusted_boot.c
new file mode 100644
index 0000000..6aec208
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_trusted_boot.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * Return the ROTPK hash in the following ASN.1 structure in DER format:
+ *
+ * AlgorithmIdentifier ::= SEQUENCE {
+ * algorithm OBJECT IDENTIFIER,
+ * parameters ANY DEFINED BY algorithm OPTIONAL
+ * }
+ *
+ * DigestInfo ::= SEQUENCE {
+ * digestAlgorithm AlgorithmIdentifier,
+ * digest OCTET STRING
+ * }
+ */
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+ unsigned int *flags)
+{
+ return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
+}
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 0cf7500..38413ef 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -413,4 +413,37 @@
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK
#define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK
+#if TARGET_PLATFORM == 3
+#define NCI_BASE_ADDR UL(0x4F000000)
+#ifdef TARGET_FLAVOUR_FPGA
+#define MCN_ADDRESS_SPACE_SIZE 0x00120000
+#else
+#define MCN_ADDRESS_SPACE_SIZE 0x00130000
+#endif /* TARGET_FLAVOUR_FPGA */
+#define MCN_OFFSET_IN_NCI 0x00C90000
+#define MCN_BASE_ADDR (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI)
+#define MCN_PMU_OFFSET 0x000C4000
+#define MCN_MICROARCH_OFFSET 0x000E4000
+#define MCN_MICROARCH_BASE_ADDR (MCN_BASE_ADDR + MCN_MICROARCH_OFFSET)
+#define MCN_SCR_OFFSET 0x4
+#define MCN_SCR_PMU_BIT 10
+#define MCN_INSTANCES 4
+#define MCN_PMU_ADDR(n) (MCN_BASE_ADDR + \
+ (n * MCN_ADDRESS_SPACE_SIZE) + \
+ MCN_PMU_OFFSET)
+#define MCN_MPAM_NS_OFFSET 0x000D0000
+#define MCN_MPAM_NS_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_NS_OFFSET)
+#define MCN_MPAM_S_OFFSET 0x000D4000
+#define MCN_MPAM_S_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_S_OFFSET)
+#define MPAM_SLCCFG_CTL_OFFSET 0x00003018
+#define SLC_RDALLOCMODE_SHIFT 8
+#define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT)
+#define SLC_WRALLOCMODE_SHIFT 12
+#define SLC_WRALLOCMODE_MASK (3 << SLC_WRALLOCMODE_SHIFT)
+
+#define SLC_DONT_ALLOC 0
+#define SLC_ALWAYS_ALLOC 1
+#define SLC_ALLOC_BUS_SIGNAL_ATTR 2
+#endif /* TARGET_PLATFORM == 3 */
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index d6b0311..7d1bc9c 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -66,11 +66,51 @@
.db_modify_mask = 0x1,
.ring_doorbell = &mhu_ring_doorbell,
};
+
+static void enable_ns_mcn_pmu(void)
+{
+ /*
+ * Enable non-secure access to MCN PMU registers
+ */
+ for (int i = 0; i < MCN_INSTANCES; i++) {
+ uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR + MCN_SCR_OFFSET +
+ (i * MCN_ADDRESS_SPACE_SIZE);
+ mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT);
+ }
+}
+
+static void set_mcn_slc_alloc_mode(void)
+{
+ /*
+ * SLC WRALLOCMODE and RDALLOCMODE are configured by default to
+ * 0b01 (always alloc), configure both to 0b10 (use bus signal
+ * attribute from interface).
+ */
+ for (int i = 0; i < MCN_INSTANCES; i++) {
+ uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR +
+ (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
+ uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR +
+ (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
+
+ mmio_clrsetbits_32(slccfg_ctl_ns,
+ (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
+ (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
+ (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
+ mmio_clrsetbits_32(slccfg_ctl_s,
+ (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
+ (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
+ (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
+ }
+}
#endif
void bl31_platform_setup(void)
{
tc_bl31_common_platform_setup();
+#if TARGET_PLATFORM == 3
+ enable_ns_mcn_pmu();
+ set_mcn_slc_alloc_mode();
+#endif
}
scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused)
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 7ab39eb..7377a01 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -385,7 +385,12 @@
endif
endif
else ifeq (${COT},dualroot)
- AUTH_SOURCES += drivers/auth/dualroot/cot.c
+ BL1_SOURCES += drivers/auth/dualroot/cot.c
+ ifneq (${COT_DESC_IN_DTB},0)
+ BL2_SOURCES += lib/fconf/fconf_cot_getter.c
+ else
+ BL2_SOURCES += drivers/auth/dualroot/cot.c
+ endif
else ifeq (${COT},cca)
BL1_SOURCES += drivers/auth/cca/cot.c
ifneq (${COT_DESC_IN_DTB},0)
diff --git a/plat/marvell/armada/a3k/common/cm3_system_reset.c b/plat/marvell/armada/a3k/common/cm3_system_reset.c
index f105d59..030a614 100644
--- a/plat/marvell/armada/a3k/common/cm3_system_reset.c
+++ b/plat/marvell/armada/a3k/common/cm3_system_reset.c
@@ -8,11 +8,22 @@
#include <stdbool.h>
#include <common/debug.h>
+#include <drivers/arm/gic_common.h>
+#include <drivers/arm/gicv3.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <a3700_pm.h>
+#include <platform_def.h>
#include <mvebu_def.h>
+/* IO Decoder Error Interrupt Status Registers */
+#define MVEBU_DEC_WIN_REGS_BASE(p) (MVEBU_REGS_BASE + 0xC000 + \
+ (p) * 0x100)
+#define MVEBU_DEC_WIN_ERR_INT_STS_REG(p) (MVEBU_DEC_WIN_REGS_BASE(p) + \
+ 0xF8)
+
/* Cortex-M3 Secure Processor Mailbox Registers */
#define MVEBU_RWTM_PARAM0_REG (MVEBU_RWTM_REG_BASE)
#define MVEBU_RWTM_CMD_REG (MVEBU_RWTM_REG_BASE + 0x40)
@@ -23,6 +34,122 @@
#define MVEBU_RWTM_REBOOT_CMD 0x0009
#define MVEBU_RWTM_REBOOT_MAGIC 0xDEADBEEF
+static inline uint32_t a3700_gicd_read(uint32_t reg)
+{
+ return mmio_read_32(PLAT_MARVELL_GICD_BASE + reg);
+}
+
+static inline void a3700_gicd_write(uint32_t reg, uint32_t value)
+{
+ mmio_write_32(PLAT_MARVELL_GICD_BASE + reg, value);
+}
+
+static void a3700_gicd_ctlr_clear_bits(uint32_t bits)
+{
+ uint32_t val;
+
+ val = a3700_gicd_read(GICD_CTLR);
+ if ((val & bits) != 0U) {
+ a3700_gicd_write(GICD_CTLR, val & ~bits);
+ mdelay(1);
+
+ if ((a3700_gicd_read(GICD_CTLR) & GICD_CTLR_RWP_BIT) != 0U) {
+ ERROR("could not clear bits 0x%x in GIC distributor control\n",
+ bits);
+ }
+ }
+}
+
+static void a3700_gic_dist_disable_irqs(void)
+{
+ int i;
+
+ for (i = 32; i < 224; i += 32) {
+ a3700_gicd_write(GICD_ICENABLER + (i >> 3), GENMASK_32(31, 0));
+ }
+}
+
+static inline uintptr_t a3700_rdist_base(unsigned int proc)
+{
+ return PLAT_MARVELL_GICR_BASE + (proc << GICR_V3_PCPUBASE_SHIFT);
+}
+
+static inline uint32_t a3700_gicr_read(unsigned int proc, uint32_t reg)
+{
+ return mmio_read_32(a3700_rdist_base(proc) + reg);
+}
+
+static inline void a3700_gicr_write(unsigned int proc, uint32_t reg,
+ uint32_t value)
+{
+ mmio_write_32(a3700_rdist_base(proc) + reg, value);
+}
+
+static void a3700_gic_redist_disable_irqs(unsigned int proc)
+{
+ a3700_gicr_write(proc, GICR_ICENABLER0, GENMASK_32(31, 0));
+ mdelay(1);
+
+ if ((a3700_gicr_read(proc, GICR_CTLR) & GICR_CTLR_RWP_BIT) != 0U) {
+ ERROR("could not disable core %u PPIs & SGIs\n", proc);
+ }
+}
+
+static void a3700_gic_redist_mark_asleep(unsigned int proc)
+{
+ a3700_gicr_write(proc, GICR_WAKER,
+ a3700_gicr_read(proc, GICR_WAKER) | WAKER_PS_BIT);
+ mdelay(1);
+
+ if ((a3700_gicr_read(proc, GICR_WAKER) & WAKER_CA_BIT) == 0U) {
+ ERROR("could not mark core %u redistributor asleep\n", proc);
+ }
+}
+
+static void a3700_io_addr_dec_ack_err_irq(void)
+{
+ unsigned int periph;
+
+ for (periph = 0; periph < 16; ++periph) {
+ /* periph 6 does not exist */
+ if (periph == 6)
+ continue;
+
+ mmio_write_32(MVEBU_DEC_WIN_ERR_INT_STS_REG(periph),
+ GENMASK_32(1, 0));
+ }
+}
+
+static void a3700_gic_reset(void)
+{
+ a3700_gic_redist_disable_irqs(0);
+ a3700_gic_redist_disable_irqs(1);
+
+ a3700_gic_redist_mark_asleep(0);
+ a3700_gic_redist_mark_asleep(1);
+
+ a3700_io_addr_dec_ack_err_irq();
+
+ a3700_pm_ack_irq();
+
+ a3700_gic_dist_disable_irqs();
+
+ a3700_gicd_ctlr_clear_bits(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1NS_BIT |
+ CTLR_ENABLE_G1S_BIT);
+
+ /* Clearing ARE_S and ARE_NS bits is undefined in the specification, but
+ * works if the previous operations are successful. We need to do it in
+ * order to put GIC into the same state it was in just after reset. If
+ * this is successful, the rWTM firmware in the secure coprocessor will
+ * reset all other peripherals one by one, load new firmware and boot
+ * it, all without triggering the true warm reset via the WARM_RESET
+ * register (which may hang the board).
+ */
+
+ a3700_gicd_ctlr_clear_bits(CTLR_ARE_S_BIT);
+ a3700_gicd_ctlr_clear_bits(CTLR_ARE_NS_BIT);
+}
+
static inline bool rwtm_completed(void)
{
return (mmio_read_32(MVEBU_RWTM_HOST_INT_RESET_REG) &
@@ -43,6 +170,11 @@
{
int tries = 5;
+ /* Put GIC into the same state it was just after reset. This is needed
+ * for the reset issue workaround to work.
+ */
+ a3700_gic_reset();
+
for (; tries > 0; --tries) {
mmio_clrbits_32(MVEBU_RWTM_HOST_INT_RESET_REG,
MVEBU_RWTM_HOST_INT_SP_COMPLETE);
diff --git a/plat/marvell/armada/a3k/common/include/a3700_pm.h b/plat/marvell/armada/a3k/common/include/a3700_pm.h
index 44dbb9f..1be82b2 100644
--- a/plat/marvell/armada/a3k/common/include/a3700_pm.h
+++ b/plat/marvell/armada/a3k/common/include/a3700_pm.h
@@ -48,6 +48,8 @@
struct pm_wake_up_src_config *mv_wake_up_src_config_get(void);
+void a3700_pm_ack_irq(void);
+
void cm3_system_reset(void);
#endif /* A3700_PM_H */
diff --git a/plat/marvell/armada/a3k/common/plat_pm.c b/plat/marvell/armada/a3k/common/plat_pm.c
index e2d15ab..d573b79 100644
--- a/plat/marvell/armada/a3k/common/plat_pm.c
+++ b/plat/marvell/armada/a3k/common/plat_pm.c
@@ -197,7 +197,7 @@
{
}
-static void a3700_pm_ack_irq(void)
+void a3700_pm_ack_irq(void)
{
uint32_t reg;
diff --git a/plat/qemu/common/qemu_plat_attest_token.c b/plat/qemu/common/qemu_plat_attest_token.c
index f7d7e90..141ff57 100644
--- a/plat/qemu/common/qemu_plat_attest_token.c
+++ b/plat/qemu/common/qemu_plat_attest_token.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024, Linaro Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,91 +10,200 @@
#include <plat/common/platform.h>
+/*
+ * This is the CBOR serialization of the CCA platform token described at
+ * https://git.trustedfirmware.org/TF-M/tf-m-tools/+/refs/heads/main/iat-verifier/tests/data/cca_example_platform_token.yaml
+ */
static const uint8_t sample_platform_token[] = {
- 0xD2, 0x84, 0x44, 0xA1, 0x01, 0x38, 0x22, 0xA0,
- 0x59, 0x02, 0x33, 0xA9, 0x19, 0x01, 0x09, 0x78,
- 0x1C, 0x68, 0x74, 0x74, 0x70, 0x3A, 0x2F, 0x2F,
- 0x61, 0x72, 0x6D, 0x2E, 0x63, 0x6F, 0x6D, 0x2F,
- 0x43, 0x43, 0x41, 0x2D, 0x53, 0x53, 0x44, 0x2F,
- 0x31, 0x2E, 0x30, 0x2E, 0x30, 0x0A, 0x58, 0x20,
- 0xB5, 0x97, 0x3C, 0xB6, 0x8B, 0xAA, 0x9F, 0xC5,
- 0x55, 0x58, 0x78, 0x6B, 0x7E, 0xC6, 0x7F, 0x69,
- 0xE4, 0x0D, 0xF5, 0xBA, 0x5A, 0xA9, 0x21, 0xCD,
- 0x0C, 0x27, 0xF4, 0x05, 0x87, 0xA0, 0x11, 0xEA,
- 0x19, 0x09, 0x5C, 0x58, 0x20, 0x7F, 0x45, 0x4C,
+ 0xd2, 0x84, 0x44, 0xa1, 0x01, 0x38, 0x22, 0xa0,
+ 0x59, 0x05, 0x7a, 0xa9, 0x19, 0x01, 0x09, 0x78,
+ 0x1c, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f,
+ 0x61, 0x72, 0x6d, 0x2e, 0x63, 0x6f, 0x6d, 0x2f,
+ 0x43, 0x43, 0x41, 0x2d, 0x53, 0x53, 0x44, 0x2f,
+ 0x31, 0x2e, 0x30, 0x2e, 0x30, 0x0a, 0x58, 0x20,
+ 0xb5, 0x97, 0x3c, 0xb6, 0x8b, 0xaa, 0x9f, 0xc5,
+ 0x55, 0x58, 0x78, 0x6b, 0x7e, 0xc6, 0x7f, 0x69,
+ 0xe4, 0x0d, 0xf5, 0xba, 0x5a, 0xa9, 0x21, 0xcd,
+ 0x0c, 0x27, 0xf4, 0x05, 0x87, 0xa0, 0x11, 0xea,
+ 0x19, 0x09, 0x5c, 0x58, 0x20, 0x7f, 0x45, 0x4c,
0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3E,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3e,
0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00,
0x58, 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03,
- 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B,
- 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13,
- 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B,
- 0x1A, 0x19, 0x18, 0x19, 0x09, 0x61, 0x58, 0x21,
- 0x01, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
- 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09,
- 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
- 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
- 0x18, 0x19, 0x09, 0x5B, 0x19, 0x30, 0x03, 0x19,
- 0x09, 0x62, 0x67, 0x73, 0x68, 0x61, 0x2D, 0x32,
- 0x35, 0x36, 0x19, 0x09, 0x5F, 0x84, 0xA5, 0x01,
- 0x62, 0x42, 0x4C, 0x05, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
- 0x33, 0x2E, 0x34, 0x2E, 0x32, 0x02, 0x58, 0x20,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
- 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
- 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
- 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
- 0x06, 0x74, 0x54, 0x46, 0x2D, 0x4D, 0x5F, 0x53,
- 0x48, 0x41, 0x32, 0x35, 0x36, 0x4D, 0x65, 0x6D,
- 0x50, 0x72, 0x65, 0x58, 0x49, 0x50, 0xA4, 0x01,
- 0x62, 0x4D, 0x31, 0x05, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x63,
- 0x31, 0x2E, 0x32, 0x02, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, 0x01,
- 0x62, 0x4D, 0x32, 0x05, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
- 0x31, 0x2E, 0x32, 0x2E, 0x33, 0x02, 0x58, 0x20,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
- 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
- 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
- 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
- 0xA4, 0x01, 0x62, 0x4D, 0x33, 0x05, 0x58, 0x20,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
- 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
- 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
- 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
- 0x04, 0x61, 0x31, 0x02, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09,
- 0x60, 0x6C, 0x77, 0x68, 0x61, 0x74, 0x65, 0x76,
- 0x65, 0x72, 0x2E, 0x63, 0x6F, 0x6D, 0x58, 0x60,
- 0xE6, 0xB6, 0x38, 0x4F, 0xAE, 0x3F, 0x6E, 0x67,
- 0xF5, 0xD4, 0x97, 0x4B, 0x3F, 0xFD, 0x0A, 0xFA,
- 0x1D, 0xF0, 0x2F, 0x73, 0xB8, 0xFF, 0x5F, 0x02,
- 0xC0, 0x0F, 0x40, 0xAC, 0xF3, 0xA2, 0x9D, 0xB5,
- 0x31, 0x50, 0x16, 0x4F, 0xFA, 0x34, 0x3D, 0x0E,
- 0xAF, 0xE0, 0xD0, 0xD1, 0x6C, 0xF0, 0x9D, 0xC1,
- 0x01, 0x42, 0xA2, 0x3C, 0xCE, 0xD4, 0x4A, 0x59,
- 0xDC, 0x29, 0x0A, 0x30, 0x93, 0x5F, 0xB4, 0x98,
- 0x61, 0xBA, 0xE3, 0x91, 0x22, 0x95, 0x24, 0xF4,
- 0xAE, 0x47, 0x93, 0xD3, 0x84, 0xA3, 0x76, 0xD0,
- 0xC1, 0x26, 0x96, 0x53, 0xA3, 0x60, 0x3F, 0x6C,
- 0x75, 0x96, 0x90, 0x6A, 0xF9, 0x4E, 0xDA, 0x30
+ 0x02, 0x01, 0x00, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b,
+ 0x0a, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13,
+ 0x12, 0x11, 0x10, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b,
+ 0x1a, 0x19, 0x18, 0x19, 0x09, 0x61, 0x44, 0xcf,
+ 0xcf, 0xcf, 0xcf, 0x19, 0x09, 0x5b, 0x19, 0x30,
+ 0x03, 0x19, 0x09, 0x62, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0x19, 0x09, 0x60, 0x78,
+ 0x3a, 0x68, 0x74, 0x74, 0x70, 0x73, 0x3a, 0x2f,
+ 0x2f, 0x76, 0x65, 0x72, 0x61, 0x69, 0x73, 0x6f,
+ 0x6e, 0x2e, 0x65, 0x78, 0x61, 0x6d, 0x70, 0x6c,
+ 0x65, 0x2f, 0x2e, 0x77, 0x65, 0x6c, 0x6c, 0x2d,
+ 0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x2f, 0x76, 0x65,
+ 0x72, 0x61, 0x69, 0x73, 0x6f, 0x6e, 0x2f, 0x76,
+ 0x65, 0x72, 0x69, 0x66, 0x69, 0x63, 0x61, 0x74,
+ 0x69, 0x6f, 0x6e, 0x19, 0x09, 0x5f, 0x8d, 0xa4,
+ 0x01, 0x69, 0x52, 0x53, 0x45, 0x5f, 0x42, 0x4c,
+ 0x31, 0x5f, 0x32, 0x05, 0x58, 0x20, 0x53, 0x78,
+ 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
+ 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
+ 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
+ 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
+ 0x20, 0x9a, 0x27, 0x1f, 0x2a, 0x91, 0x6b, 0x0b,
+ 0x6e, 0xe6, 0xce, 0xcb, 0x24, 0x26, 0xf0, 0xb3,
+ 0x20, 0x6e, 0xf0, 0x74, 0x57, 0x8b, 0xe5, 0x5d,
+ 0x9b, 0xc9, 0x4f, 0x6f, 0x3f, 0xe3, 0xab, 0x86,
+ 0xaa, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
+ 0x35, 0x36, 0xa4, 0x01, 0x67, 0x52, 0x53, 0x45,
+ 0x5f, 0x42, 0x4c, 0x32, 0x05, 0x58, 0x20, 0x53,
+ 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec,
+ 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41,
+ 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22,
+ 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02,
+ 0x58, 0x20, 0x53, 0xc2, 0x34, 0xe5, 0xe8, 0x47,
+ 0x2b, 0x6a, 0xc5, 0x1c, 0x1a, 0xe1, 0xca, 0xb3,
+ 0xfe, 0x06, 0xfa, 0xd0, 0x53, 0xbe, 0xb8, 0xeb,
+ 0xfd, 0x89, 0x77, 0xb0, 0x10, 0x65, 0x5b, 0xfd,
+ 0xd3, 0xc3, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d,
+ 0x32, 0x35, 0x36, 0xa4, 0x01, 0x65, 0x52, 0x53,
+ 0x45, 0x5f, 0x53, 0x05, 0x58, 0x20, 0x53, 0x78,
+ 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
+ 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
+ 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
+ 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
+ 0x20, 0x11, 0x21, 0xcf, 0xcc, 0xd5, 0x91, 0x3f,
+ 0x0a, 0x63, 0xfe, 0xc4, 0x0a, 0x6f, 0xfd, 0x44,
+ 0xea, 0x64, 0xf9, 0xdc, 0x13, 0x5c, 0x66, 0x63,
+ 0x4b, 0xa0, 0x01, 0xd1, 0x0b, 0xcf, 0x43, 0x02,
+ 0xa2, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
+ 0x35, 0x36, 0xa4, 0x01, 0x66, 0x41, 0x50, 0x5f,
+ 0x42, 0x4c, 0x31, 0x05, 0x58, 0x20, 0x53, 0x78,
+ 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
+ 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
+ 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
+ 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
+ 0x20, 0x15, 0x71, 0xb5, 0xec, 0x78, 0xbd, 0x68,
+ 0x51, 0x2b, 0xf7, 0x83, 0x0b, 0xb6, 0xa2, 0xa4,
+ 0x4b, 0x20, 0x47, 0xc7, 0xdf, 0x57, 0xbc, 0xe7,
+ 0x9e, 0xb8, 0xa1, 0xc0, 0xe5, 0xbe, 0xa0, 0xa5,
+ 0x01, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
+ 0x35, 0x36, 0xa4, 0x01, 0x66, 0x41, 0x50, 0x5f,
+ 0x42, 0x4c, 0x32, 0x05, 0x58, 0x20, 0x53, 0x78,
+ 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
+ 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
+ 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
+ 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
+ 0x20, 0x10, 0x15, 0x9b, 0xaf, 0x26, 0x2b, 0x43,
+ 0xa9, 0x2d, 0x95, 0xdb, 0x59, 0xda, 0xe1, 0xf7,
+ 0x2c, 0x64, 0x51, 0x27, 0x30, 0x16, 0x61, 0xe0,
+ 0xa3, 0xce, 0x4e, 0x38, 0xb2, 0x95, 0xa9, 0x7c,
+ 0x58, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
+ 0x35, 0x36, 0xa4, 0x01, 0x67, 0x53, 0x43, 0x50,
+ 0x5f, 0x42, 0x4c, 0x31, 0x05, 0x58, 0x20, 0x53,
+ 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec,
+ 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41,
+ 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22,
+ 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02,
+ 0x58, 0x20, 0x10, 0x12, 0x2e, 0x85, 0x6b, 0x3f,
+ 0xcd, 0x49, 0xf0, 0x63, 0x63, 0x63, 0x17, 0x47,
+ 0x61, 0x49, 0xcb, 0x73, 0x0a, 0x1a, 0xa1, 0xcf,
+ 0xaa, 0xd8, 0x18, 0x55, 0x2b, 0x72, 0xf5, 0x6d,
+ 0x6f, 0x68, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d,
+ 0x32, 0x35, 0x36, 0xa4, 0x01, 0x67, 0x53, 0x43,
+ 0x50, 0x5f, 0x42, 0x4c, 0x32, 0x05, 0x58, 0x20,
+ 0xf1, 0x4b, 0x49, 0x87, 0x90, 0x4b, 0xcb, 0x58,
+ 0x14, 0xe4, 0x45, 0x9a, 0x05, 0x7e, 0xd4, 0xd2,
+ 0x0f, 0x58, 0xa6, 0x33, 0x15, 0x22, 0x88, 0xa7,
+ 0x61, 0x21, 0x4d, 0xcd, 0x28, 0x78, 0x0b, 0x56,
+ 0x02, 0x58, 0x20, 0xaa, 0x67, 0xa1, 0x69, 0xb0,
+ 0xbb, 0xa2, 0x17, 0xaa, 0x0a, 0xa8, 0x8a, 0x65,
+ 0x34, 0x69, 0x20, 0xc8, 0x4c, 0x42, 0x44, 0x7c,
+ 0x36, 0xba, 0x5f, 0x7e, 0xa6, 0x5f, 0x42, 0x2c,
+ 0x1f, 0xe5, 0xd8, 0x06, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x67, 0x41,
+ 0x50, 0x5f, 0x42, 0x4c, 0x33, 0x31, 0x05, 0x58,
+ 0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d,
+ 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc,
+ 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf,
+ 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a,
+ 0xa3, 0x02, 0x58, 0x20, 0x2e, 0x6d, 0x31, 0xa5,
+ 0x98, 0x3a, 0x91, 0x25, 0x1b, 0xfa, 0xe5, 0xae,
+ 0xfa, 0x1c, 0x0a, 0x19, 0xd8, 0xba, 0x3c, 0xf6,
+ 0x01, 0xd0, 0xe8, 0xa7, 0x06, 0xb4, 0xcf, 0xa9,
+ 0x66, 0x1a, 0x6b, 0x8a, 0x06, 0x67, 0x73, 0x68,
+ 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x63,
+ 0x52, 0x4d, 0x4d, 0x05, 0x58, 0x20, 0x53, 0x78,
+ 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
+ 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
+ 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
+ 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
+ 0x20, 0xa1, 0xfb, 0x50, 0xe6, 0xc8, 0x6f, 0xae,
+ 0x16, 0x79, 0xef, 0x33, 0x51, 0x29, 0x6f, 0xd6,
+ 0x71, 0x34, 0x11, 0xa0, 0x8c, 0xf8, 0xdd, 0x17,
+ 0x90, 0xa4, 0xfd, 0x05, 0xfa, 0xe8, 0x68, 0x81,
+ 0x64, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
+ 0x35, 0x36, 0xa4, 0x01, 0x69, 0x48, 0x57, 0x5f,
+ 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58,
+ 0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d,
+ 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc,
+ 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf,
+ 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a,
+ 0xa3, 0x02, 0x58, 0x20, 0x1a, 0x25, 0x24, 0x02,
+ 0x97, 0x2f, 0x60, 0x57, 0xfa, 0x53, 0xcc, 0x17,
+ 0x2b, 0x52, 0xb9, 0xff, 0xca, 0x69, 0x8e, 0x18,
+ 0x31, 0x1f, 0xac, 0xd0, 0xf3, 0xb0, 0x6e, 0xca,
+ 0xae, 0xf7, 0x9e, 0x17, 0x06, 0x67, 0x73, 0x68,
+ 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x69,
+ 0x46, 0x57, 0x5f, 0x43, 0x4f, 0x4e, 0x46, 0x49,
+ 0x47, 0x05, 0x58, 0x20, 0x53, 0x78, 0x79, 0x63,
+ 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d, 0x8b, 0x15,
+ 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41, 0x9c, 0x3d,
+ 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38, 0xc0, 0xfa,
+ 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58, 0x20, 0x9a,
+ 0x92, 0xad, 0xbc, 0x0c, 0xee, 0x38, 0xef, 0x65,
+ 0x8c, 0x71, 0xce, 0x1b, 0x1b, 0xf8, 0xc6, 0x56,
+ 0x68, 0xf1, 0x66, 0xbf, 0xb2, 0x13, 0x64, 0x4c,
+ 0x89, 0x5c, 0xcb, 0x1a, 0xd0, 0x7a, 0x25, 0x06,
+ 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36,
+ 0xa4, 0x01, 0x6c, 0x54, 0x42, 0x5f, 0x46, 0x57,
+ 0x5f, 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05,
+ 0x58, 0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53,
+ 0x5d, 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2,
+ 0xdc, 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60,
+ 0xcf, 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f,
+ 0x7a, 0xa3, 0x02, 0x58, 0x20, 0x23, 0x89, 0x03,
+ 0x18, 0x0c, 0xc1, 0x04, 0xec, 0x2c, 0x5d, 0x8b,
+ 0x3f, 0x20, 0xc5, 0xbc, 0x61, 0xb3, 0x89, 0xec,
+ 0x0a, 0x96, 0x7d, 0xf8, 0xcc, 0x20, 0x8c, 0xdc,
+ 0x7c, 0xd4, 0x54, 0x17, 0x4f, 0x06, 0x67, 0x73,
+ 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01,
+ 0x6d, 0x53, 0x4f, 0x43, 0x5f, 0x46, 0x57, 0x5f,
+ 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58,
+ 0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d,
+ 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc,
+ 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf,
+ 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a,
+ 0xa3, 0x02, 0x58, 0x20, 0xe6, 0xc2, 0x1e, 0x8d,
+ 0x26, 0x0f, 0xe7, 0x18, 0x82, 0xde, 0xbd, 0xb3,
+ 0x39, 0xd2, 0x40, 0x2a, 0x2c, 0xa7, 0x64, 0x85,
+ 0x29, 0xbc, 0x23, 0x03, 0xf4, 0x86, 0x49, 0xbc,
+ 0xe0, 0x38, 0x00, 0x17, 0x06, 0x67, 0x73, 0x68,
+ 0x61, 0x2d, 0x32, 0x35, 0x36, 0x58, 0x60, 0x21,
+ 0x51, 0x20, 0x92, 0xd6, 0xd0, 0x2a, 0xe6, 0xbe,
+ 0x2f, 0xe3, 0x93, 0x0e, 0xa5, 0x1f, 0xd6, 0x98,
+ 0x96, 0x32, 0x24, 0x56, 0xe9, 0xdf, 0xc7, 0x32,
+ 0x5e, 0x0b, 0x78, 0x68, 0xb6, 0x90, 0x73, 0x2a,
+ 0x0c, 0x0f, 0x07, 0x77, 0xc1, 0x15, 0x40, 0x4b,
+ 0xe1, 0xfc, 0x83, 0x9b, 0x7d, 0x30, 0x4f, 0x4f,
+ 0xe6, 0xfa, 0x46, 0xae, 0x12, 0xa3, 0x08, 0x3a,
+ 0xcf, 0x24, 0x06, 0x67, 0x91, 0x06, 0xbf, 0xae,
+ 0x50, 0x31, 0x79, 0xdd, 0x50, 0x33, 0x49, 0x12,
+ 0xbf, 0xc6, 0xda, 0x33, 0x6d, 0xd6, 0x18, 0x25,
+ 0x43, 0x54, 0x4d, 0xb5, 0x88, 0xd6, 0xae, 0x67,
+ 0x35, 0x7a, 0xfd, 0xb0, 0x5f, 0x95, 0xb7
};
/*
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 0d401f9..8a1d76d 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -634,6 +634,11 @@
#define PLAT_NB_FIXED_REGUS U(2)
/*******************************************************************************
+ * STM32MP1 CLOCKS
+ ******************************************************************************/
+#define PLL1_NOMINAL_FREQ_IN_KHZ U(650000) /* 650MHz */
+
+/*******************************************************************************
* Device Tree defines
******************************************************************************/
#if STM32MP13
