tree a9b3859a0a8864ac2d4275567583b65440a9cd45
parent dc4d3d6feddf4ca15bd7160aa1b4375bfa662605
author Caesar Wang <wxt@rock-chips.com> 1475025570 -0700
committer Caesar Wang <wxt@rock-chips.com> 1475081479 +0800

rockchip: fixes the clock select and divide register for rk3399

As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON
register.

As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the
CRU_CLKSEL_CON offset is 0x100,not 0x80.

Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529