diff --git a/plat/mediatek/drivers/dp/mt_dp.c b/plat/mediatek/drivers/dp/mt_dp.c
index 2cd5932..1bf2b44 100644
--- a/plat/mediatek/drivers/dp/mt_dp.c
+++ b/plat/mediatek/drivers/dp/mt_dp.c
@@ -15,7 +15,7 @@
 static uint32_t dp_write_sec_reg(uint32_t is_edp, uint32_t offset,
 				uint32_t value, uint32_t mask)
 {
-	uint32_t reg = (is_edp != 0U) ? eDP_SEC_BASE : DP_SEC_BASE;
+	uint32_t reg = (is_edp != 0U) ? EDP_SEC_BASE : DP_SEC_BASE;
 
 	mmio_clrsetbits_32(reg + offset, mask, value);
 
diff --git a/plat/mediatek/mt8195/aarch64/platform_common.c b/plat/mediatek/mt8195/aarch64/platform_common.c
index 2b95171..1f5c5fa 100644
--- a/plat/mediatek/mt8195/aarch64/platform_common.c
+++ b/plat/mediatek/mt8195/aarch64/platform_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,7 +19,7 @@
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(eDP_SEC_BASE, eDP_SEC_SIZE,
+	MAP_REGION_FLAT(EDP_SEC_BASE, EDP_SEC_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
index d4f2f83..2a2f559 100644
--- a/plat/mediatek/mt8195/include/platform_def.h
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -48,9 +48,9 @@
 /*******************************************************************************
  * DP/eDP related constants
  ******************************************************************************/
-#define eDP_SEC_BASE		(IO_PHYS + 0x0C504000)
+#define EDP_SEC_BASE		(IO_PHYS + 0x0C504000)
 #define DP_SEC_BASE		(IO_PHYS + 0x0C604000)
-#define eDP_SEC_SIZE		0x1000
+#define EDP_SEC_SIZE		0x1000
 #define DP_SEC_SIZE		0x1000
 
 /*******************************************************************************