diff --git a/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.c b/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.c
new file mode 100644
index 0000000..53e3cc8
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+
+#include <mtk_apusys.h>
+#include <plat/common/platform.h>
+
+int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
+			    uint32_t *ret1)
+{
+	int32_t ret = 0L;
+	uint32_t request_ops;
+
+	request_ops = (uint32_t)x1;
+
+	switch (request_ops) {
+	case MTK_SIP_APU_START_MCU:
+		/* setup addr[33:32] in reviser */
+		mmio_write_32(REVISER_SECUREFW_CTXT, 0U);
+		mmio_write_32(REVISER_USDRFW_CTXT, 0U);
+
+		/* setup secure sideband */
+		mmio_write_32(AO_SEC_FW,
+			      (SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) |
+			      (0U << SEC_FW_DOMAIN_SHIFT));
+
+		/* setup boot address */
+		mmio_write_32(AO_MD32_BOOT_CTRL, 0U);
+
+		/* setup pre-define region */
+		mmio_write_32(AO_MD32_PRE_DEFINE,
+			      (PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) |
+			      (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) |
+			      (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) |
+			      (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G));
+
+		/* release runstall */
+		mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN);
+
+		INFO("[APUSYS] rev(0x%08x,0x%08x)\n",
+		     mmio_read_32(REVISER_SECUREFW_CTXT),
+		     mmio_read_32(REVISER_USDRFW_CTXT));
+		INFO("[APUSYS] ao(0x%08x,0x%08x,0x%08x,0x%08x,0x%08x)\n",
+		     mmio_read_32(AO_SEC_FW),
+		     mmio_read_32(AO_SEC_USR_FW),
+		     mmio_read_32(AO_MD32_BOOT_CTRL),
+		     mmio_read_32(AO_MD32_PRE_DEFINE),
+		     mmio_read_32(AO_MD32_SYS_CTRL));
+		break;
+	case MTK_SIP_APU_STOP_MCU:
+		/* hold runstall */
+		mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL);
+
+		INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n",
+		     mmio_read_32(AO_MD32_BOOT_CTRL),
+		     mmio_read_32(AO_MD32_SYS_CTRL));
+		break;
+	default:
+		ERROR("%s, unknown request_ops=0x%x\n", __func__, request_ops);
+		break;
+	}
+
+	return ret;
+}
diff --git a/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.h b/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.h
new file mode 100644
index 0000000..2659daf
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_APUSYS_H
+#define MTK_APUSYS_H
+
+#include <stdint.h>
+
+/* setup the SMC command ops */
+#define MTK_SIP_APU_START_MCU	0x00U
+#define MTK_SIP_APU_STOP_MCU	0x01U
+
+/* AO Register */
+#define AO_MD32_PRE_DEFINE	(APUSYS_APU_S_S_4_BASE + 0x00)
+#define AO_MD32_BOOT_CTRL	(APUSYS_APU_S_S_4_BASE + 0x04)
+#define AO_MD32_SYS_CTRL	(APUSYS_APU_S_S_4_BASE + 0x08)
+#define AO_SEC_FW		(APUSYS_APU_S_S_4_BASE + 0x10)
+#define AO_SEC_USR_FW		(APUSYS_APU_S_S_4_BASE + 0x14)
+
+#define PRE_DEFINE_CACHE_TCM	0x3U
+#define PRE_DEFINE_CACHE	0x2U
+#define PRE_DEFINE_SHIFT_0G	0U
+#define PRE_DEFINE_SHIFT_1G	2U
+#define PRE_DEFINE_SHIFT_2G	4U
+#define PRE_DEFINE_SHIFT_3G	6U
+
+#define SEC_FW_NON_SECURE	1U
+#define SEC_FW_SHIFT_NS		4U
+#define SEC_FW_DOMAIN_SHIFT	0U
+
+#define SEC_USR_FW_NON_SECURE	1U
+#define SEC_USR_FW_SHIFT_NS	4U
+#define SEC_USR_FW_DOMAIN_SHIFT	0U
+
+#define SYS_CTRL_RUN		0U
+#define SYS_CTRL_STALL		1U
+
+/* Reviser Register */
+#define REVISER_SECUREFW_CTXT	(APUSYS_SCTRL_REVISER_BASE + 0x100)
+#define REVISER_USDRFW_CTXT	(APUSYS_SCTRL_REVISER_BASE + 0x104)
+
+int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
+			    uint32_t *ret1);
+#endif /* MTK_APUSYS_H */