layerscape: Initial TF-A support for LS1043ardb
This patch introduce TF-A support for NXP's ls1043a platform.
more details information of ls1043a chip and ls1043ardb board
can be found at docs/plat/ls1043a.rst.
Boot sequence on ls1043a is: bootrom loads bl1 firstly, then bl1
loads bl2, bl2 will load bl31, bl32 and bl33, bl31 will boot
bl32(tee os) and bl33(u-boot or uefi), bl33 boot Linux kernel.
Now TF-A on ls1043ardb platform has the following features in this patch:
* Support boot from Nor flash.
* TF-A can boot bl33 which runs in el2 of non-secure world.
* TF-A boot OPTee OS.
* Support PSCI
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Chenyin.Ha <Chenyin.Ha@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
Signed-off-by: Wen He <wen.he_1@nxp.com>
diff --git a/plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S b/plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S
new file mode 100644
index 0000000..80524fc
--- /dev/null
+++ b/plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+ .globl plat_reset_handler
+ .globl plat_my_core_pos
+ .globl platform_mem_init
+
+func plat_my_core_pos
+ mrs x0, mpidr_el1
+ and x1, x0, #MPIDR_CPU_MASK //reserve the last 8 bits
+ and x0, x0, #MPIDR_CLUSTER_MASK
+ add x0, x1, x0, LSR #4 //4 cores
+ ret
+endfunc plat_my_core_pos
+
+func platform_mem_init
+ mov x29, x30
+ bl inv_dcache_range
+
+//SDRAM_CFG
+ ldr w0, =0x1080000
+ ldr w1, =0x0c000c45
+ str w1, [x0, #0x110]
+//CS0_BNDS
+ ldr w1, =0x7f000000
+ str w1, [x0, #0x000]
+//CS0_CONFIG
+ ldr w1, =0x22030480
+ str w1, [x0, #0x080]
+//TIMING_CFG_0
+ ldr w1, =0x18005591
+ str w1, [x0, #0x104]
+//TIMING_CFG_1
+ ldr w1, =0x428cb4bb
+ str w1, [x0, #0x108]
+//TIMING_CFG_2
+ ldr w1, =0x11c14800
+ str w1, [x0, #0x10C]
+//TIMING_CFG_3
+ ldr w1, =0x00100c01
+ str w1, [x0, #0x100]
+//TIMING_CFG_4
+ ldr w1, =0x02000000
+ str w1, [x0, #0x160]
+//TIMING_CFG_5
+ ldr w1, =0x00144003
+ str w1, [x0, #0x164]
+//TIMING_CFG_7
+ ldr w1, =0x00003013
+ str w1, [x0, #0x16C]
+//TIMING_CFG_8
+ ldr w1, =0x00561102
+ str w1, [x0, #0x250]
+//SDRAM_CFG_2
+ ldr w1, =0x00114000
+ str w1, [x0, #0x114]
+//SDRAM_MODE
+ ldr w1, =0x10020103
+ str w1, [x0, #0x118]
+//SDRAM_MODE_2
+ ldr w1, =0x0
+ str w1, [x0, #0x11C]
+//SDRAM_INTERVAL
+ ldr w1, =0x18066018
+ str w1, [x0, #0x124]
+//DDR_WRLVL_CNTL
+ ldr w1, =0x07f675c6
+ str w1, [x0, #0x174]
+//DDR_WRLVL_CNTL_2
+ ldr w1, =0x00080907
+ str w1, [x0, #0x190]
+//DDR_WRLVL_CNTL_3
+ ldr w1, =0x0
+ str w1, [x0, #0x194]
+//DDR_CDR1
+ ldr w1, =0x00000480
+ str w1, [x0, #0xB28]
+//DDR_CDR2
+ ldr w1, =0x81a10000
+ str w1, [x0, #0xB2C]
+//SDRAM_CLK_CNTL
+ ldr w1, =0x00000003
+ str w1, [x0, #0x130]
+//DDR_ZQ_CNTL
+ ldr w1, =0x0507098a
+ str w1, [x0, #0x170]
+//SDRAM_MODE_9
+ ldr w1, =0x00050000
+ str w1, [x0, #0x220]
+//SDRAM_MODE_10
+ ldr w1, =0x00000004
+ str w1, [x0, #0x224]
+//CS0_CONFIG_2
+ ldr w1, =0x0
+ str w1, [x0, #0x0C0]
+//SDRAM_CFG
+ ldr w1, =0x08000cc5
+ str w1, [x0, #0x110]
+
+ mov w3,#0
+ ldr w4,=0xffffff01
+z_loop:
+delay_loop1:
+ sub w4, w4, #1
+ cmp w4, #0
+ b.gt delay_loop1
+
+ ldr w1, [x0, #0x114]
+ add w3, w3, #1
+ cmp w1, #0 //'\n'
+ b.eq 1f
+ cmp w3, #20
+ b.gt 1f
+ b z_loop
+
+1:
+ ldr w4,=0xffffff02
+delay_loop2:
+ sub w4, w4, #1
+ cmp w4, #0
+ b.gt delay_loop2
+
+ ldr w1, =0x00000000
+ str w1, [x0]
+
+ ret x29
+endfunc platform_mem_init
+
+func apply_platform_errata
+ /*TODO if needed*/
+ ret
+endfunc apply_platform_errata
+
+func plat_reset_handler
+ mov x29, x30
+ bl apply_platform_errata
+
+ mov x30, x29
+ ret
+endfunc plat_reset_handler
diff --git a/plat/layerscape/board/ls1043/include/ls_def.h b/plat/layerscape/board/ls1043/include/ls_def.h
new file mode 100644
index 0000000..1015129
--- /dev/null
+++ b/plat/layerscape/board/ls1043/include/ls_def.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __LS_DEF_H__
+#define __LS_DEF_H__
+
+#include <arch.h>
+#include <common_def.h>
+#include <platform_def.h>
+#include <tbbr_img_def.h>
+#include <utils_def.h>
+#include <xlat_tables_defs.h>
+
+
+/******************************************************************************
+ * Definitions common to all ARM standard platforms
+ *****************************************************************************/
+/* Special value used to verify platform parameters from BL2 to BL31 */
+#define LS_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
+
+#define LS_CACHE_WRITEBACK_SHIFT 6
+
+/*
+ * Macros mapping the MPIDR Affinity levels to Layerscape Platform Power levels. The
+ * power levels have a 1:1 mapping with the MPIDR affinity levels.
+ */
+#define LS_PWR_LVL0 MPIDR_AFFLVL0
+#define LS_PWR_LVL1 MPIDR_AFFLVL1
+#define LS_PWR_LVL2 MPIDR_AFFLVL2
+
+/*
+ * Macros for local power states in Layerscape platforms encoded by State-ID field
+ * within the power-state parameter.
+ */
+/* Local power state for power domains in Run state. */
+#define LS_LOCAL_STATE_RUN 0
+/* Local power state for retention. Valid only for CPU power domains */
+#define LS_LOCAL_STATE_RET 1
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains
+ */
+#define LS_LOCAL_STATE_OFF 2
+
+#define LS_MAP_NS_DRAM MAP_REGION_FLAT( \
+ (LS_NS_DRAM_BASE), \
+ LS_DRAM1_SIZE, \
+ MT_DEVICE | MT_RW | MT_NS)
+
+#define LS_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
+ TSP_SEC_MEM_BASE, \
+ TSP_SEC_MEM_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+
+#define LS_MAP_FLASH0_RW MAP_REGION_FLAT(PLAT_LS_FLASH_BASE,\
+ PLAT_LS_FLASH_SIZE, \
+ MT_DEVICE | MT_RW)
+
+#define LS_MAP_CCSR MAP_REGION_FLAT(PLAT_LS_CCSR_BASE, \
+ PLAT_LS_CCSR_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+
+#define LS_MAP_CONSOLE MAP_REGION_FLAT(PLAT_LS1043_DUART1_BASE, \
+ PLAT_LS1043_DUART_SIZE, \
+ MT_DEVICE | MT_RW | MT_NS)
+
+/*
+ * The number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+/******************************************************************************
+ * Required platform porting definitions common to all ARM standard platforms
+ *****************************************************************************/
+
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
+
+/*
+ * This macro defines the deepest retention state possible. A higher state
+ * id will represent an invalid or a power down state.
+ */
+#define PLAT_MAX_RET_STATE LS_LOCAL_STATE_RET
+
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE LS_LOCAL_STATE_OFF
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE (1 << LS_CACHE_WRITEBACK_SHIFT)
+
+/*
+ * One cache line needed for bakery locks on Layerscape platforms
+ */
+#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
+
+#endif /* __LS_DEF_H__ */
diff --git a/plat/layerscape/board/ls1043/include/ns_access.h b/plat/layerscape/board/ls1043/include/ns_access.h
new file mode 100644
index 0000000..6ed7bc0
--- /dev/null
+++ b/plat/layerscape/board/ls1043/include/ns_access.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+
+#include "fsl_csu.h"
+
+enum csu_cslx_ind {
+ CSU_CSLX_PCIE2_IO = 0,
+ CSU_CSLX_PCIE1_IO,
+ CSU_CSLX_MG2TPR_IP,
+ CSU_CSLX_IFC_MEM,
+ CSU_CSLX_OCRAM,
+ CSU_CSLX_GIC,
+ CSU_CSLX_PCIE1,
+ CSU_CSLX_OCRAM2,
+ CSU_CSLX_QSPI_MEM,
+ CSU_CSLX_PCIE2,
+ CSU_CSLX_SATA,
+ CSU_CSLX_USB1,
+ CSU_CSLX_QM_BM_SWPORTAL,
+ CSU_CSLX_PCIE3 = 16,
+ CSU_CSLX_PCIE3_IO,
+ CSU_CSLX_USB3 = 20,
+ CSU_CSLX_USB2,
+ CSU_CSLX_PFE = 23,
+ CSU_CSLX_SERDES = 32,
+ CSU_CSLX_QDMA,
+ CSU_CSLX_LPUART2,
+ CSU_CSLX_LPUART1,
+ CSU_CSLX_LPUART4,
+ CSU_CSLX_LPUART3,
+ CSU_CSLX_LPUART6,
+ CSU_CSLX_LPUART5,
+ CSU_CSLX_DSPI1 = 41,
+ CSU_CSLX_QSPI,
+ CSU_CSLX_ESDHC,
+ CSU_CSLX_IFC = 45,
+ CSU_CSLX_I2C1,
+ CSU_CSLX_USB_2,
+ CSU_CSLX_I2C3 = 48,
+ CSU_CSLX_I2C2,
+ CSU_CSLX_DUART2 = 50,
+ CSU_CSLX_DUART1,
+ CSU_CSLX_WDT2,
+ CSU_CSLX_WDT1,
+ CSU_CSLX_EDMA,
+ CSU_CSLX_SYS_CNT,
+ CSU_CSLX_DMA_MUX2,
+ CSU_CSLX_DMA_MUX1,
+ CSU_CSLX_DDR,
+ CSU_CSLX_QUICC,
+ CSU_CSLX_DCFG_CCU_RCPM = 60,
+ CSU_CSLX_SECURE_BOOTROM,
+ CSU_CSLX_SFP,
+ CSU_CSLX_TMU,
+ CSU_CSLX_SECURE_MONITOR,
+ CSU_CSLX_SCFG,
+ CSU_CSLX_FM = 66,
+ CSU_CSLX_SEC5_5,
+ CSU_CSLX_BM,
+ CSU_CSLX_QM,
+ CSU_CSLX_GPIO2 = 70,
+ CSU_CSLX_GPIO1,
+ CSU_CSLX_GPIO4,
+ CSU_CSLX_GPIO3,
+ CSU_CSLX_PLATFORM_CONT,
+ CSU_CSLX_CSU,
+ CSU_CSLX_IIC4 = 77,
+ CSU_CSLX_WDT4,
+ CSU_CSLX_WDT3,
+ CSU_CSLX_ESDHC2 = 80,
+ CSU_CSLX_WDT5 = 81,
+ CSU_CSLX_SAI2,
+ CSU_CSLX_SAI1,
+ CSU_CSLX_SAI4,
+ CSU_CSLX_SAI3,
+ CSU_CSLX_FTM2 = 86,
+ CSU_CSLX_FTM1,
+ CSU_CSLX_FTM4,
+ CSU_CSLX_FTM3,
+ CSU_CSLX_FTM6 = 90,
+ CSU_CSLX_FTM5,
+ CSU_CSLX_FTM8,
+ CSU_CSLX_FTM7,
+ CSU_CSLX_DSCR = 121,
+};
+
+static struct csu_ns_dev ns_dev[] = {
+ {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
+ {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
+ {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
+ {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM, CSU_ALL_RW},
+ {CSU_CSLX_GIC, CSU_ALL_RW},
+ {CSU_CSLX_PCIE1, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM2, CSU_ALL_RW},
+ {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
+ {CSU_CSLX_PCIE2, CSU_ALL_RW},
+ {CSU_CSLX_SATA, CSU_ALL_RW},
+ {CSU_CSLX_USB1, CSU_ALL_RW},
+ {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
+ {CSU_CSLX_PCIE3, CSU_ALL_RW},
+ {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
+ {CSU_CSLX_USB3, CSU_ALL_RW},
+ {CSU_CSLX_USB2, CSU_ALL_RW},
+ {CSU_CSLX_PFE, CSU_ALL_RW},
+ {CSU_CSLX_SERDES, CSU_ALL_RW},
+ {CSU_CSLX_QDMA, CSU_ALL_RW},
+ {CSU_CSLX_LPUART2, CSU_ALL_RW},
+ {CSU_CSLX_LPUART1, CSU_ALL_RW},
+ {CSU_CSLX_LPUART4, CSU_ALL_RW},
+ {CSU_CSLX_LPUART3, CSU_ALL_RW},
+ {CSU_CSLX_LPUART6, CSU_ALL_RW},
+ {CSU_CSLX_LPUART5, CSU_ALL_RW},
+ {CSU_CSLX_DSPI1, CSU_ALL_RW},
+ {CSU_CSLX_QSPI, CSU_ALL_RW},
+ {CSU_CSLX_ESDHC, CSU_ALL_RW},
+ {CSU_CSLX_IFC, CSU_ALL_RW},
+ {CSU_CSLX_I2C1, CSU_ALL_RW},
+ {CSU_CSLX_USB_2, CSU_ALL_RW},
+ {CSU_CSLX_I2C3, CSU_ALL_RW},
+ {CSU_CSLX_I2C2, CSU_ALL_RW},
+ {CSU_CSLX_DUART2, CSU_ALL_RW},
+ {CSU_CSLX_DUART1, CSU_ALL_RW},
+ {CSU_CSLX_WDT2, CSU_ALL_RW},
+ {CSU_CSLX_WDT1, CSU_ALL_RW},
+ {CSU_CSLX_EDMA, CSU_ALL_RW},
+ {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
+ {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
+ {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
+ {CSU_CSLX_DDR, CSU_ALL_RW},
+ {CSU_CSLX_QUICC, CSU_ALL_RW},
+ {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
+ {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
+ {CSU_CSLX_SFP, CSU_ALL_RW},
+ {CSU_CSLX_TMU, CSU_ALL_RW},
+ {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
+ {CSU_CSLX_SCFG, CSU_ALL_RW},
+ {CSU_CSLX_FM, CSU_ALL_RW},
+ {CSU_CSLX_SEC5_5, CSU_ALL_RW},
+ {CSU_CSLX_BM, CSU_ALL_RW},
+ {CSU_CSLX_QM, CSU_ALL_RW},
+ {CSU_CSLX_GPIO2, CSU_ALL_RW},
+ {CSU_CSLX_GPIO1, CSU_ALL_RW},
+ {CSU_CSLX_GPIO4, CSU_ALL_RW},
+ {CSU_CSLX_GPIO3, CSU_ALL_RW},
+ {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
+ {CSU_CSLX_CSU, CSU_ALL_RW},
+ {CSU_CSLX_IIC4, CSU_ALL_RW},
+ {CSU_CSLX_WDT4, CSU_ALL_RW},
+ {CSU_CSLX_WDT3, CSU_ALL_RW},
+ {CSU_CSLX_ESDHC2, CSU_ALL_RW},
+ {CSU_CSLX_WDT5, CSU_ALL_RW},
+ {CSU_CSLX_SAI2, CSU_ALL_RW},
+ {CSU_CSLX_SAI1, CSU_ALL_RW},
+ {CSU_CSLX_SAI4, CSU_ALL_RW},
+ {CSU_CSLX_SAI3, CSU_ALL_RW},
+ {CSU_CSLX_FTM2, CSU_ALL_RW},
+ {CSU_CSLX_FTM1, CSU_ALL_RW},
+ {CSU_CSLX_FTM4, CSU_ALL_RW},
+ {CSU_CSLX_FTM3, CSU_ALL_RW},
+ {CSU_CSLX_FTM6, CSU_ALL_RW},
+ {CSU_CSLX_FTM5, CSU_ALL_RW},
+ {CSU_CSLX_FTM8, CSU_ALL_RW},
+ {CSU_CSLX_FTM7, CSU_ALL_RW},
+ {CSU_CSLX_DSCR, CSU_ALL_RW},
+};
+
+#endif
diff --git a/plat/layerscape/board/ls1043/include/plat_macros.S b/plat/layerscape/board/ls1043/include/plat_macros.S
new file mode 100644
index 0000000..8163dc1
--- /dev/null
+++ b/plat/layerscape/board/ls1043/include/plat_macros.S
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLAT_MACROS_S__
+#define __PLAT_MACROS_S__
+
+ /* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant GIC and CCI registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ * Clobbers: x0 - x10, x16, x17, sp
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ .endm
+
+#endif /* __PLAT_MACROS_S__ */
diff --git a/plat/layerscape/board/ls1043/include/platform_def.h b/plat/layerscape/board/ls1043/include/platform_def.h
new file mode 100644
index 0000000..0e1cae6
--- /dev/null
+++ b/plat/layerscape/board/ls1043/include/platform_def.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <common_def.h>
+#include <tzc400.h>
+#include <utils.h>
+#include "ls_def.h"
+
+#define FIRMWARE_WELCOME_STR_LS1043 "Welcome to LS1043 BL1 Phase\n"
+#define FIRMWARE_WELCOME_STR_LS1043_BL2 "Welcome to LS1043 BL2 Phase\n"
+#define FIRMWARE_WELCOME_STR_LS1043_BL31 "Welcome to LS1043 BL31 Phase\n"
+#define FIRMWARE_WELCOME_STR_LS1043_BL32 "Welcome to LS1043 BL32 Phase, TSP\n"
+
+/* Required platform porting definitions */
+#define PLAT_PRIMARY_CPU 0x0
+#define PLAT_MAX_PWR_LVL LS_PWR_LVL1
+#define PLATFORM_CORE_COUNT 4
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
+
+/*
+ * Required LS standard platform porting definitions
+ */
+#define PLAT_LS_CLUSTER_COUNT 1
+#define PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX 4
+#define LS1043_CLUSTER_COUNT 1
+#define LS1043_MAX_CPUS_PER_CLUSTER 4
+
+#define LS_DRAM1_BASE 0x80000000
+#define LS_DRAM2_BASE 0x880000000
+#define LS_DRAM2_SIZE 0x780000000 /* 30G */
+#define LS_DRAM1_SIZE 0x80000000 /* 2G */
+#define LS_NS_DRAM_BASE LS_DRAM1_BASE
+/* 64M Secure Memory, in fact there a 2M non-secure hole on top of it */
+#define LS_SECURE_DRAM_SIZE (64 * 1024 * 1024)
+#define LS_SECURE_DRAM_BASE (LS_NS_DRAM_BASE + LS_DRAM1_SIZE - \
+ LS_SECURE_DRAM_SIZE)
+#define LS_NS_DRAM_SIZE (LS_DRAM1_SIZE - LS_SECURE_DRAM_SIZE)
+
+/*
+ * By default, BL2 is in DDR memory.
+ * If LS_BL2_IN_OCRAM is defined, BL2 will in OCRAM
+ */
+/* #define LS_BL2_IN_OCRAM */
+
+#ifndef LS_BL2_IN_OCRAM
+/*
+ * on top of SECURE memory is 2M non-secure hole for OPTee,
+ * 1M secure memory below this hole will be used for BL2.
+ */
+#define LS_BL2_DDR_BASE (LS_SECURE_DRAM_BASE + \
+ LS_SECURE_DRAM_SIZE \
+ - 3 * 1024 * 1024)
+#endif
+
+#define PLAT_LS_CCSR_BASE 0x1000000
+#define PLAT_LS_CCSR_SIZE 0xF000000
+
+/* Flash base address, currently ROM is not used for TF-A images on LS platforms */
+#define PLAT_LS_TRUSTED_ROM_BASE 0x60100000
+#define PLAT_LS_TRUSTED_ROM_SIZE 0x20000000 /* Flash size */
+#define PLAT_LS_FLASH_SIZE 0x20000000
+#define PLAT_LS_FLASH_BASE 0x60000000
+
+#define LS_SRAM_BASE 0x10000000
+#define LS_SRAM_LIMIT 0x10020000 /* 128K */
+#define LS_SRAM_SHARED_SIZE 0x1000 /* 4K */
+#define LS_SRAM_SIZE (LS_SRAM_LIMIT - LS_SRAM_BASE)
+#define LS_BL_RAM_BASE (LS_SRAM_BASE + LS_SRAM_SHARED_SIZE)
+
+#define PLAT_LS_FIP_MAX_SIZE 0x4000000
+
+/* Memory Layout */
+
+#define BL1_RO_BASE PLAT_LS_TRUSTED_ROM_BASE
+#define BL1_RO_LIMIT (PLAT_LS_TRUSTED_ROM_BASE \
+ + PLAT_LS_TRUSTED_ROM_SIZE)
+#define PLAT_LS_FIP_BASE 0x60120000
+
+#ifdef LS_BL2_IN_OCRAM
+/* BL2 is in OCRAM */
+#define PLAT_LS_MAX_BL1_RW_SIZE (52 * 1024) /* 52K */
+#define PLAT_LS_MAX_BL31_SIZE (64 * 1024) /* 64K */
+#define PLAT_LS_MAX_BL2_SIZE (44 * 1024) /* 44K */
+/* Reserve memory in OCRAM for BL31 Text and ROData segment */
+#define BL31_TEXT_RODATA_SIZE (32 * 1024) /* 32K */
+#else /* LS_BL2_IN_OCRAM */
+/* BL2 in DDR */
+#define PLAT_LS_MAX_BL1_RW_SIZE (64 * 1024) /* 64K */
+#define PLAT_LS_MAX_BL31_SIZE (64 * 1024) /* 64K */
+#define PLAT_LS_MAX_BL2_SIZE (1 * 1024 * 1024) /* 1M */
+#endif /* LS_BL2_IN_OCRAM */
+/*
+ * Put BL31 at the start of OCRAM.
+ */
+#define BL31_BASE LS_SRAM_BASE
+#define BL31_LIMIT (LS_SRAM_BASE + PLAT_LS_MAX_BL31_SIZE)
+
+#ifdef LS_BL2_IN_OCRAM
+/*
+ * BL2 follow BL31 Text and ROData region.
+ */
+#define BL2_BASE (BL31_BASE + BL31_TEXT_RODATA_SIZE)
+#define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
+
+#else
+/*
+ * BL2 in DDR memory.
+ */
+#define BL2_BASE LS_BL2_DDR_BASE
+#define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
+
+#endif
+
+/*
+ * Put BL1 RW at the top of the Trusted SRAM.
+ */
+#ifdef LS_BL2_IN_OCRAM
+#define BL1_RW_BASE BL2_LIMIT
+#else
+#define BL1_RW_BASE BL31_LIMIT
+#endif
+#define BL1_RW_LIMIT LS_SRAM_LIMIT
+
+/* Put BL32 in secure memory */
+#define BL32_BASE LS_SECURE_DRAM_BASE
+#define BL32_LIMIT (LS_SECURE_DRAM_BASE + LS_SECURE_DRAM_SIZE)
+/* BL33 memory region */
+#define BL33_BASE 0x82000000
+#define BL33_LIMIT (LS_NS_DRAM_BASE + LS_NS_DRAM_SIZE)
+
+/*******************************************************************************
+ * BL32 specific defines.
+ ******************************************************************************/
+/*
+ * On ARM standard platforms, the TSP can execute from Trusted SRAM,
+ * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
+ * controller.
+ */
+
+#define TSP_SEC_MEM_BASE BL32_BASE
+#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE)
+
+/*
+ * ID of the secure physical generic timer interrupt used by the TSP.
+ */
+#define TSP_IRQ_SEC_PHY_TIMER 29
+
+
+/*
+ * GIC related constants
+ */
+#define PLAT_LS1043_CCI_BASE 0x01180000
+#define GICD_BASE 0x01401000
+#define GICC_BASE 0x01402000
+#define GICD_BASE_64K 0x01410000
+#define GICC_BASE_64K 0x01420000
+
+#define DCFG_CCSR_SVR 0x1ee00a4
+#define REV1_0 0x10
+#define REV1_1 0x11
+#define GIC_ADDR_BIT 31
+#define SCFG_GIC400_ALIGN 0x1570188
+
+/* UART related definition */
+
+#define PLAT_LS1043_DUART1_BASE 0x021c0000
+#define PLAT_LS1043_DUART2_BASE 0x021d0000
+#define PLAT_LS1043_DUART_SIZE 0x10000
+
+#define PLAT_LS1043_UART_BASE 0x21c0500
+#define PLAT_LS1043_UART2_BASE 0x21c0600
+#define PLAT_LS1043_UART_CLOCK 400000000
+#define PLAT_LS1043_UART_BAUDRATE 115200
+/* Define UART to be used by TF-A log */
+#define LS_TF_UART_BASE PLAT_LS1043_UART_BASE
+#define LS_TF_UART_CLOCK PLAT_LS1043_UART_CLOCK
+#define LS_TF_UART_BAUDRATE PLAT_LS1043_UART_BAUDRATE
+
+#define LS1043_SYS_CNTCTL_BASE 0x2B00000
+
+#define CONFIG_SYS_IMMR 0x01000000
+#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL1)
+#define PLATFORM_STACK_SIZE 0x440
+#define MAX_MMAP_REGIONS 6
+#define MAX_XLAT_TABLES 4
+#elif defined(IMAGE_BL2)
+#define PLATFORM_STACK_SIZE 0x400
+#define MAX_MMAP_REGIONS 8
+#define MAX_XLAT_TABLES 6
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE 0x400
+#define MAX_MMAP_REGIONS 8
+#define MAX_XLAT_TABLES 4
+#elif defined(IMAGE_BL32)
+#define PLATFORM_STACK_SIZE 0x440
+#define MAX_MMAP_REGIONS 8
+#define MAX_XLAT_TABLES 9
+#endif
+
+#define MAX_IO_DEVICES 3
+#define MAX_IO_HANDLES 4
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/layerscape/board/ls1043/include/soc_tzasc.h b/plat/layerscape/board/ls1043/include/soc_tzasc.h
new file mode 100644
index 0000000..0039f2d
--- /dev/null
+++ b/plat/layerscape/board/ls1043/include/soc_tzasc.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _SOC_TZASC_H_
+#define _SOC_TZASC_H_
+
+#include "tzc380.h"
+
+#define MAX_NUM_TZC_REGION 3
+
+/* TZASC related constants */
+#define TZASC_CONFIGURATION_REG 0x000
+#define TZASC_SECURITY_INV_REG 0x034
+#define TZASC_SECURITY_INV_EN 0x1
+#define TZASC_REGIONS_REG 0x100
+/* As region address should address atleast 32KB memory. */
+#define TZASC_REGION_LOWADDR_MASK 0xFFFF8000
+#define TZASC_REGION_LOWADDR_OFFSET 0x0
+#define TZASC_REGION_HIGHADDR_OFFSET 0x4
+#define TZASC_REGION_ATTR_OFFSET 0x8
+#define TZASC_REGION_ENABLED 1
+#define TZASC_REGION_DISABLED 0
+#define TZASC_REGION_SIZE_32KB 0xE
+#define TZASC_REGION_SIZE_64KB 0xF
+#define TZASC_REGION_SIZE_128KB 0x10
+#define TZASC_REGION_SIZE_256KB 0x11
+#define TZASC_REGION_SIZE_512KB 0x12
+#define TZASC_REGION_SIZE_1MB 0x13
+#define TZASC_REGION_SIZE_2MB 0x14
+#define TZASC_REGION_SIZE_4MB 0x15
+#define TZASC_REGION_SIZE_8MB 0x16
+#define TZASC_REGION_SIZE_16MB 0x17
+#define TZASC_REGION_SIZE_32MB 0x18
+#define TZASC_REGION_SIZE_64MB 0x19
+#define TZASC_REGION_SIZE_128MB 0x1A
+#define TZASC_REGION_SIZE_256MB 0x1B
+#define TZASC_REGION_SIZE_512MB 0x1C
+#define TZASC_REGION_SIZE_1GB 0x1D
+#define TZASC_REGION_SIZE_2GB 0x1E
+#define TZASC_REGION_SIZE_4GB 0x1F
+#define TZASC_REGION_SIZE_8GB 0x20
+#define TZASC_REGION_SIZE_16GB 0x21
+#define TZASC_REGION_SIZE_32GB 0x22
+#define TZASC_REGION_SECURITY_SR (1 << 3)
+#define TZASC_REGION_SECURITY_SW (1 << 2)
+#define TZASC_REGION_SECURITY_SRW (TZASC_REGION_SECURITY_SR| \
+ TZASC_REGION_SECURITY_SW)
+#define TZASC_REGION_SECURITY_NSR (1 << 1)
+#define TZASC_REGION_SECURITY_NSW 1
+#define TZASC_REGION_SECURITY_NSRW (TZASC_REGION_SECURITY_NSR| \
+ TZASC_REGION_SECURITY_NSW)
+
+#define CSU_SEC_ACCESS_REG_OFFSET 0x21C
+#define TZASC_BYPASS_MUX_DISABLE 0x4
+#define CCI_TERMINATE_BARRIER_TX 0x8
+#define CONFIG_SYS_FSL_TZASC_ADDR 0x1500000
+
+/* List of MAX_NUM_TZC_REGION TZC regions' boundaries and configurations. */
+
+static const struct tzc380_reg tzc380_reg_list[] = {
+ {
+ TZASC_REGION_SECURITY_NSRW, /* .secure attr */
+ 0x0, /* .enabled */
+ 0x0, /* .lowaddr */
+ 0x0, /* .highaddr */
+ 0x0, /* .size */
+ 0x0, /* .submask */
+ },
+ {
+ TZASC_REGION_SECURITY_SRW,
+ TZASC_REGION_ENABLED,
+ 0xFC000000,
+ 0x0,
+ TZASC_REGION_SIZE_64MB,
+ 0x80, /* Disable region 7 */
+ },
+ /* reserve 2M non-scure memory for OPTEE public memory */
+ {
+ TZASC_REGION_SECURITY_SRW,
+ TZASC_REGION_ENABLED,
+ 0xFF800000,
+ 0x0,
+ TZASC_REGION_SIZE_8MB,
+ 0xC0, /* Disable region 6 & 7 */
+ },
+
+ {}
+};
+
+#endif /* _SOC_TZASC_H_ */
diff --git a/plat/layerscape/board/ls1043/ls1043_bl1_setup.c b/plat/layerscape/board/ls1043/ls1043_bl1_setup.c
new file mode 100644
index 0000000..e82a1fb
--- /dev/null
+++ b/plat/layerscape/board/ls1043/ls1043_bl1_setup.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cci.h>
+#include <debug.h>
+#include <mmio.h>
+#include "plat_ls.h"
+
+static const int cci_map[] = {
+ PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX
+};
+
+void bl1_platform_setup(void)
+{
+ NOTICE(FIRMWARE_WELCOME_STR_LS1043);
+
+ ls_bl1_platform_setup();
+
+ /*
+ * Initialize system level generic timer for Layerscape Socs.
+ */
+ ls_delay_timer_init();
+
+ /* TODO: remove these DDR code */
+ VERBOSE("CS0_BNDS = %x\n", mmio_read_32(0x1080000 + 0x000));
+ mmio_write_32(0x1080000 + 0x000, 0x7f000000);
+ VERBOSE("CS0_BNDS = %x\n", mmio_read_32(0x1080000 + 0x000));
+}
+
+/*******************************************************************************
+ * Perform any BL1 specific platform actions.
+ ******************************************************************************/
+void bl1_early_platform_setup(void)
+{
+ ls_bl1_early_platform_setup();
+
+ /*
+ * Initialize Interconnect for this cluster during cold boot.
+ * No need for locks as no other CPU is active.
+ */
+ cci_init(PLAT_LS1043_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
+
+ /*
+ * Enable coherency in Interconnect for the primary CPU's cluster.
+ */
+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+
+}
+
+unsigned int bl1_plat_get_next_image_id(void)
+{
+ return BL2_IMAGE_ID;
+}
diff --git a/plat/layerscape/board/ls1043/ls1043_bl2_setup.c b/plat/layerscape/board/ls1043/ls1043_bl2_setup.c
new file mode 100644
index 0000000..b529aa5
--- /dev/null
+++ b/plat/layerscape/board/ls1043/ls1043_bl2_setup.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <debug.h>
+#include "plat_ls.h"
+
+void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ ls_bl2_early_platform_setup((meminfo_t *)arg1);
+
+ /*
+ * Initialize system level generic timer for Layerscape Socs.
+ */
+ ls_delay_timer_init();
+}
+
+void bl2_platform_setup(void)
+{
+ NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL2);
+}
diff --git a/plat/layerscape/board/ls1043/ls1043_bl31_setup.c b/plat/layerscape/board/ls1043/ls1043_bl31_setup.c
new file mode 100644
index 0000000..3473d98
--- /dev/null
+++ b/plat/layerscape/board/ls1043/ls1043_bl31_setup.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cci.h>
+#include <debug.h>
+#include "plat_ls.h"
+#include "fsl_csu.h"
+
+/* slave interfaces according to the RM */
+static const int cci_map[] = {
+ 4,
+};
+
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+#ifdef LS_BL2_IN_OCRAM
+ unsigned long romem_base = (unsigned long)(&__TEXT_START__);
+ unsigned long romem_size = (unsigned long)(&__RODATA_END__)
+ - romem_base;
+
+ /* Check the Text and RO-Data region size */
+ if (romem_size > BL31_TEXT_RODATA_SIZE) {
+ ERROR("BL31 Text and RO-Data region size exceed reserved memory size\n");
+ panic();
+ }
+#endif
+
+ /*
+ * Initialize system level generic timer for Layerscape Socs.
+ */
+ ls_delay_timer_init();
+
+ ls_bl31_early_platform_setup((void *)arg0, (void *)arg3);
+
+ /*
+ * Initialize the correct interconnect for this cluster during cold
+ * boot. No need for locks as no other CPU is active.
+ */
+ cci_init(PLAT_LS1043_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
+
+ /*
+ * Enable coherency in interconnect for the primary CPU's cluster.
+ * Earlier bootloader stages might already do this (e.g. Trusted
+ * Firmware's BL1 does it) but we can't assume so. There is no harm in
+ * executing this code twice anyway.
+ */
+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+
+ /* Init CSU to enable non-secure access to peripherals */
+ enable_layerscape_ns_access();
+}
diff --git a/plat/layerscape/board/ls1043/ls1043_err.c b/plat/layerscape/board/ls1043/ls1043_err.c
new file mode 100644
index 0000000..e4a2cae
--- /dev/null
+++ b/plat/layerscape/board/ls1043/ls1043_err.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <debug.h>
+#include <errno.h>
+#include <stdint.h>
+
+/*
+ * Error handler
+ */
+void plat_error_handler(int err)
+{
+ switch (err) {
+ case -ENOENT:
+ case -EAUTH:
+ /* ToDo */
+ break;
+ default:
+ /* Unexpected error */
+ break;
+ }
+
+ /* Loop until the watchdog resets the system */
+ for (;;)
+ wfi();
+}
diff --git a/plat/layerscape/board/ls1043/ls1043_psci.c b/plat/layerscape/board/ls1043/ls1043_psci.c
new file mode 100644
index 0000000..a41e79e
--- /dev/null
+++ b/plat/layerscape/board/ls1043/ls1043_psci.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <debug.h>
+#include <errno.h>
+#include <assert.h>
+#include <platform.h>
+#include <psci.h>
+#include <mmio.h>
+#include <sys/endian.h>
+#include <gicv2.h>
+#include <delay_timer.h>
+#include "platform_def.h"
+
+#define LS_SCFG_BASE 0x01570000
+/* register to store warm boot entry, big endian, higher 32bit */
+#define LS_SCFG_SCRATCHRW0_OFFSET 0x600
+/* register to store warm boot entry, big endian, lower 32bit */
+#define LS_SCFG_SCRATCHRW1_OFFSET 0x604
+#define LS_SCFG_COREBCR_OFFSET 0x680
+
+#define LS_DCFG_BASE 0x01EE0000
+#define LS_DCFG_RSTCR_OFFSET 0x0B0
+#define LS_DCFG_RSTRQMR1_OFFSET 0x0C0
+#define LS_DCFG_BRR_OFFSET 0x0E4
+
+#define LS_SCFG_CORE0_SFT_RST_OFFSET 0x130
+#define LS_SCFG_CORE1_SFT_RST_OFFSET 0x134
+#define LS_SCFG_CORE2_SFT_RST_OFFSET 0x138
+#define LS_SCFG_CORE3_SFT_RST_OFFSET 0x13C
+
+#define LS_SCFG_CORESRENCR_OFFSET 0x204
+
+#define LS_SCFG_RVBAR0_0_OFFSET 0x220
+#define LS_SCFG_RVBAR0_1_OFFSET 0x224
+
+#define LS_SCFG_RVBAR1_0_OFFSET 0x228
+#define LS_SCFG_RVBAR1_1_OFFSET 0x22C
+
+#define LS_SCFG_RVBAR2_0_OFFSET 0x230
+#define LS_SCFG_RVBAR2_1_OFFSET 0x234
+
+#define LS_SCFG_RVBAR3_0_OFFSET 0x238
+#define LS_SCFG_RVBAR3_1_OFFSET 0x23C
+
+/* the entry for core warm boot */
+static uintptr_t warmboot_entry;
+
+/* warm reset single core */
+static void ls1043_reset_core(int core_pos)
+{
+ assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
+
+ /* set 0 in RVBAR, boot from bootrom at 0x0 */
+ mmio_write_32(LS_SCFG_BASE + LS_SCFG_RVBAR0_0_OFFSET + core_pos * 8,
+ 0);
+ mmio_write_32(LS_SCFG_BASE + LS_SCFG_RVBAR0_1_OFFSET + core_pos * 8,
+ 0);
+
+ dsb();
+ /* enable core soft reset */
+ mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORESRENCR_OFFSET,
+ htobe32(1 << 31));
+ dsb();
+ isb();
+ /* reset core */
+ mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORE0_SFT_RST_OFFSET +
+ core_pos * 4, htobe32(1 << 31));
+ mdelay(10);
+}
+
+static void __dead2 ls1043_system_reset(void)
+{
+ /* clear reset request mask bits */
+ mmio_write_32(LS_DCFG_BASE + LS_DCFG_RSTRQMR1_OFFSET, 0);
+
+ /* set reset request bit */
+ mmio_write_32(LS_DCFG_BASE + LS_DCFG_RSTCR_OFFSET,
+ htobe32((uint32_t)0x2));
+
+ /* system will reset; if fail, enter wfi */
+ dsb();
+ isb();
+ wfi();
+
+ panic();
+}
+
+
+static int ls1043_pwr_domain_on(u_register_t mpidr)
+{
+ int core_pos = plat_core_pos_by_mpidr(mpidr);
+ uint32_t core_mask = 1 << core_pos;
+ uint32_t brr;
+
+ assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
+
+ /* set warm boot entry */
+ mmio_write_32(LS_SCFG_BASE + LS_SCFG_SCRATCHRW0_OFFSET,
+ htobe32((uint32_t)(warmboot_entry >> 32)));
+
+ mmio_write_32(LS_SCFG_BASE + LS_SCFG_SCRATCHRW1_OFFSET,
+ htobe32((uint32_t)warmboot_entry));
+
+ dsb();
+
+ brr = be32toh(mmio_read_32(LS_DCFG_BASE + LS_DCFG_BRR_OFFSET));
+ if (brr & core_mask) {
+ /* core has been released, must reset it to restart */
+ ls1043_reset_core(core_pos);
+
+ /* set bit in core boot control register to enable boot */
+ mmio_write_32(LS_SCFG_BASE + LS_SCFG_COREBCR_OFFSET,
+ htobe32(core_mask));
+
+ } else {
+ /* set bit in core boot control register to enable boot */
+ mmio_write_32(LS_SCFG_BASE + LS_SCFG_COREBCR_OFFSET,
+ htobe32(core_mask));
+
+ /* release core */
+ mmio_write_32(LS_DCFG_BASE + LS_DCFG_BRR_OFFSET,
+ htobe32(brr | core_mask));
+ }
+
+ mdelay(20);
+
+ /* wake core in case it is in wfe */
+ dsb();
+ isb();
+ sev();
+
+ return PSCI_E_SUCCESS;
+}
+
+static void ls1043_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ /* Per cpu gic distributor setup */
+ gicv2_pcpu_distif_init();
+
+ /* Enable the gic CPU interface */
+ gicv2_cpuif_enable();
+}
+
+static void ls1043_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ /* Disable the gic CPU interface */
+ gicv2_cpuif_disable();
+}
+
+static plat_psci_ops_t ls1043_psci_pm_ops = {
+ .system_reset = ls1043_system_reset,
+ .pwr_domain_on = ls1043_pwr_domain_on,
+ .pwr_domain_on_finish = ls1043_pwr_domain_on_finish,
+ .pwr_domain_off = ls1043_pwr_domain_off,
+};
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ warmboot_entry = sec_entrypoint;
+ *psci_ops = &ls1043_psci_pm_ops;
+ return 0;
+}
diff --git a/plat/layerscape/board/ls1043/ls1043_security.c b/plat/layerscape/board/ls1043/ls1043_security.c
new file mode 100644
index 0000000..18ae56e
--- /dev/null
+++ b/plat/layerscape/board/ls1043/ls1043_security.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "plat_ls.h"
+
+/*
+ * We assume that all security programming is done by the primary core.
+ */
+void plat_ls_security_setup(void)
+{
+ tzc380_setup();
+}
diff --git a/plat/layerscape/board/ls1043/ls1043_stack_protector.c b/plat/layerscape/board/ls1043/ls1043_stack_protector.c
new file mode 100644
index 0000000..50f463b
--- /dev/null
+++ b/plat/layerscape/board/ls1043/ls1043_stack_protector.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <stdint.h>
+
+#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL)
+
+u_register_t plat_get_stack_protector_canary(void)
+{
+ /*
+ * Ideally, a random number should be returned instead of the
+ * combination of a timer's value and a compile-time constant. As the
+ * FVP does not have any random number generator, this is better than
+ * nothing but not necessarily really secure.
+ */
+ return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
+}
diff --git a/plat/layerscape/board/ls1043/ls1043_topology.c b/plat/layerscape/board/ls1043/ls1043_topology.c
new file mode 100644
index 0000000..12d2830
--- /dev/null
+++ b/plat/layerscape/board/ls1043/ls1043_topology.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <cassert.h>
+#include "plat_ls.h"
+#include "platform_def.h"
+
+unsigned char ls1043_power_domain_tree_desc[LS1043_CLUSTER_COUNT + 1];
+
+
+CASSERT(LS1043_CLUSTER_COUNT && LS1043_CLUSTER_COUNT <= 256,
+ assert_invalid_ls1043_cluster_count);
+
+/*******************************************************************************
+ * This function dynamically constructs the topology according to
+ * LS1043_CLUSTER_COUNT and returns it.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ int i;
+
+ ls1043_power_domain_tree_desc[0] = LS1043_CLUSTER_COUNT;
+
+ for (i = 0; i < LS1043_CLUSTER_COUNT; i++)
+ ls1043_power_domain_tree_desc[i + 1] =
+ LS1043_MAX_CPUS_PER_CLUSTER;
+
+ return ls1043_power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * This function returns the core count within the cluster corresponding to
+ * `mpidr`.
+ ******************************************************************************/
+unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
+{
+ return LS1043_MAX_CPUS_PER_CLUSTER;
+}
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ if (ls_check_mpidr(mpidr) == -1)
+ return -1;
+
+ return plat_ls_calc_core_pos(mpidr);
+}
diff --git a/plat/layerscape/board/ls1043/ls_gic.c b/plat/layerscape/board/ls1043/ls_gic.c
new file mode 100644
index 0000000..3986153
--- /dev/null
+++ b/plat/layerscape/board/ls1043/ls_gic.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <debug.h>
+#include <endian.h>
+#include "platform_def.h"
+#include "soc.h"
+
+/*
+ * Get GIC offset
+ * For LS1043a rev1.0, GIC base address align with 4k.
+ * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
+ * is set, GIC base address align with 4K, or else align
+ * with 64k.
+ */
+void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base)
+{
+
+ uint32_t *ccsr_svr = (uint32_t *)DCFG_CCSR_SVR;
+ uint32_t *gic_align = (uint32_t *)SCFG_GIC400_ALIGN;
+ uint32_t val;
+ uint32_t soc_dev_id;
+
+ val = be32toh(mmio_read_32((uintptr_t)ccsr_svr));
+ soc_dev_id = val & (SVR_WO_E << 8);
+
+ if ((soc_dev_id == (SVR_LS1043A << 8) ||
+ soc_dev_id == (SVR_LS1043AE << 8)) &&
+ ((val & 0xff) == REV1_1)) {
+ val = be32toh(mmio_read_32((uintptr_t)gic_align));
+ if (val & (1 << GIC_ADDR_BIT)) {
+ *gicc_base = GICC_BASE;
+ *gicd_base = GICD_BASE;
+ } else {
+ *gicc_base = GICC_BASE_64K;
+ *gicd_base = GICD_BASE_64K;
+ }
+ } else {
+ *gicc_base = GICC_BASE;
+ *gicd_base = GICD_BASE;
+ }
+}
diff --git a/plat/layerscape/board/ls1043/platform.mk b/plat/layerscape/board/ls1043/platform.mk
new file mode 100644
index 0000000..163d25e
--- /dev/null
+++ b/plat/layerscape/board/ls1043/platform.mk
@@ -0,0 +1,80 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# indicate the reset vector address can be programmed
+PROGRAMMABLE_RESET_ADDRESS := 1
+USE_COHERENT_MEM := 0
+RESET_TO_BL31 := 0
+ENABLE_STACK_PROTECTOR := 0
+LS1043_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
+ drivers/arm/gic/v2/gicv2_main.c \
+ drivers/arm/gic/v2/gicv2_helpers.c \
+ plat/common/plat_gicv2.c \
+ plat/layerscape/board/ls1043/ls_gic.c
+
+
+LS1043_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c
+
+LS1043_SECURITY_SOURCES := plat/layerscape/common/ls_tzc380.c \
+ plat/layerscape/board/ls1043/ls1043_security.c
+
+PLAT_INCLUDES := -Iplat/layerscape/board/ls1043/include \
+ -Iinclude/plat/arm/common \
+ -Iplat/layerscape/common/include \
+ -Iinclude/drivers/arm \
+ -Iinclude/lib \
+ -Iinclude/drivers/io
+
+
+PLAT_BL_COMMON_SOURCES := drivers/console/aarch64/console.S \
+ plat/layerscape/common/aarch64/ls_console.S
+
+LS1043_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
+
+LS1043_CPU_LIBS += lib/cpus/aarch64/cortex_a53.S
+
+BL1_SOURCES += plat/layerscape/board/ls1043/ls1043_bl1_setup.c \
+ plat/layerscape/board/ls1043/ls1043_err.c \
+ drivers/delay_timer/delay_timer.c \
+
+BL1_SOURCES += plat/layerscape/board/ls1043/${ARCH}/ls1043_helpers.S \
+ ${LS1043_CPU_LIBS} \
+ ${LS1043_INTERCONNECT_SOURCES} \
+ $(LS1043_SECURITY_SOURCES)
+
+
+BL2_SOURCES += drivers/delay_timer/delay_timer.c \
+ plat/layerscape/board/ls1043/ls1043_bl2_setup.c \
+ plat/layerscape/board/ls1043/ls1043_err.c \
+ ${LS1043_SECURITY_SOURCES}
+
+
+BL31_SOURCES += plat/layerscape/board/ls1043/ls1043_bl31_setup.c \
+ plat/layerscape/board/ls1043/ls1043_topology.c \
+ plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S \
+ plat/layerscape/board/ls1043/ls1043_psci.c \
+ drivers/delay_timer/delay_timer.c \
+ ${LS1043_CPU_LIBS} \
+ ${LS1043_GIC_SOURCES} \
+ ${LS1043_INTERCONNECT_SOURCES} \
+ ${LS1043_SECURITY_SOURCES}
+
+# Disable the PSCI platform compatibility layer
+ENABLE_PLAT_COMPAT := 0
+MULTI_CONSOLE_API := 1
+
+# Enable workarounds for selected Cortex-A53 erratas.
+ERRATA_A53_855873 := 1
+
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+PLAT_BL_COMMON_SOURCES += plat/layerscape/board/ls1043/ls1043_stack_protector.c
+endif
+
+ifeq (${ARCH},aarch32)
+ NEED_BL32 := yes
+endif
+
+include plat/layerscape/common/ls_common.mk
diff --git a/plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c b/plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c
new file mode 100644
index 0000000..4fc019c
--- /dev/null
+++ b/plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "plat_ls.h"
+
+void tsp_early_platform_setup(void)
+{
+ ls_tsp_early_platform_setup();
+
+ /*Todo: Initialize the platform config for future decision making */
+}
diff --git a/plat/layerscape/board/ls1043/tsp/tsp-ls1043.mk b/plat/layerscape/board/ls1043/tsp/tsp-ls1043.mk
new file mode 100644
index 0000000..3941427
--- /dev/null
+++ b/plat/layerscape/board/ls1043/tsp/tsp-ls1043.mk
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# TSP source files specific to FVP platform
+BL32_SOURCES += plat/layerscape/board/ls1043/ls1043_topology.c \
+ plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c \
+ ${LS1043_GIC_SOURCES}
+
+include plat/layerscape/common/tsp/ls_tsp.mk