tree 0c78e4a1940cc16e9684cbd4f758d7b559f1da1c
parent a10d64e2aabbc63561cfbaa928bd0bfe1f645240
author Jeenu Viswambharan <jeenu.viswambharan@arm.com> 1483612641 +0000
committer Jeenu Viswambharan <jeenu.viswambharan@arm.com> 1488452420 +0000

Enable data caches early with hardware-assisted coherency

At present, warm-booted CPUs keep their caches disabled when enabling
MMU, and remains so until they enter coherency later.

On systems with hardware-assisted coherency, for which
HW_ASSISTED_COHERENCY build flag would be enabled, warm-booted CPUs can
have both caches and MMU enabled at once.

Change-Id: Icb0adb026e01aecf34beadf49c88faa9dd368327
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>