Tegra194: rename secure scratch register macros
This patch renames all the secure scratch registers to reflect
their usage.
This is a list of all the macros being renamed:
- SECURE_SCRATCH_RSV44_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV97 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV99_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV109_* -> SCRATCH_RESET_VECTOR_*
Change-Id: I838ece3da39bc4be8f349782e99bac777755fa39
Signed-off-by: Steven Kao <skao@nvidia.com>
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 2b578d5..0037b49 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -156,16 +156,21 @@
* Tegra scratch registers constants
******************************************************************************/
#define TEGRA_SCRATCH_BASE U(0x0C390000)
-#define SECURE_SCRATCH_RSV1_LO U(0x06C)
-#define SECURE_SCRATCH_RSV1_HI U(0x070)
-#define SECURE_SCRATCH_RSV6 U(0x094)
-#define SECURE_SCRATCH_RSV11_LO U(0x0BC)
-#define SECURE_SCRATCH_RSV11_HI U(0x0C0)
-#define SECURE_SCRATCH_RSV53_LO U(0x20C)
-#define SECURE_SCRATCH_RSV53_HI U(0x210)
-#define SECURE_SCRATCH_RSV54_HI U(0x218)
-#define SECURE_SCRATCH_RSV55_LO U(0x21C)
-#define SECURE_SCRATCH_RSV55_HI U(0x220)
+#define SECURE_SCRATCH_RSV44_LO U(0x1C4)
+#define SECURE_SCRATCH_RSV44_HI U(0x1C8)
+#define SECURE_SCRATCH_RSV97 U(0x36C)
+#define SECURE_SCRATCH_RSV99_LO U(0x37C)
+#define SECURE_SCRATCH_RSV99_HI U(0x380)
+#define SECURE_SCRATCH_RSV109_LO U(0x3CC)
+#define SECURE_SCRATCH_RSV109_HI U(0x3D0)
+
+#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV44_LO
+#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV44_HI
+#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97
+#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO
+#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI
+#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO
+#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI
/*******************************************************************************
* Tegra Memory Mapped Control Register Access Bus constants