Tegra194: memctrl: enable mc coalescer
This patch enable the Memory Controller's "Coalescer" feature to
improve performance of memory transactions.
Change-Id: I50ba0354116284f85d9e170c293ce77e9f3fb4d8
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
index 1433a2e..86ab859 100644
--- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
@@ -530,6 +530,9 @@
#define MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB (1U << 25)
#define MC_CLIENT_HOTRESET_STATUS2 0x1898U
+#define MC_COALESCE_CTRL 0x2930U
+#define MC_COALESCE_CTRL_COALESCER_ENABLE (1U << 31)
+
/*******************************************************************************
* Tegra TSA Controller constants
******************************************************************************/
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
index 54dbe7c..a59cd11 100644
--- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -617,6 +617,9 @@
wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL;
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
+
+ reg_val = MC_COALESCE_CTRL_COALESCER_ENABLE;
+ tegra_mc_write_32(MC_COALESCE_CTRL, reg_val);
}
/*******************************************************************************