diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c
deleted file mode 100644
index 1754344..0000000
--- a/plat/renesas/rcar/bl2_cpg_init.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "cpg_registers.h"
-#include "rcar_def.h"
-#include "rcar_private.h"
-
-static void bl2_secure_cpg_init(void);
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
-static void bl2_realtime_cpg_init_h3(void);
-static void bl2_system_cpg_init_h3(void);
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
-static void bl2_realtime_cpg_init_m3(void);
-static void bl2_system_cpg_init_m3(void);
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
-static void bl2_realtime_cpg_init_m3n(void);
-static void bl2_system_cpg_init_m3n(void);
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M)
-static void bl2_realtime_cpg_init_v3m(void);
-static void bl2_system_cpg_init_v3m(void);
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
-static void bl2_realtime_cpg_init_e3(void);
-static void bl2_system_cpg_init_e3(void);
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
-static void bl2_realtime_cpg_init_d3(void);
-static void bl2_system_cpg_init_d3(void);
-#endif
-
-typedef struct {
-	uintptr_t adr;
-	uint32_t val;
-} reg_setting_t;
-
-static void bl2_secure_cpg_init(void)
-{
-	uint32_t stop_cr2, reset_cr2;
-	uint32_t stop_cr4, reset_cr4;
-	uint32_t stop_cr5, reset_cr5;
-
-#if (RCAR_LSI == RCAR_D3)
-	reset_cr2 = 0x00000000U;
-	stop_cr2 = 0xFFFFFFFFU;
-#elif (RCAR_LSI == RCAR_E3)
-	reset_cr2 = 0x10000000U;
-	stop_cr2 = 0xEFFFFFFFU;
-#else
-	reset_cr2 = 0x14000000U;
-	stop_cr2 = 0xEBFFFFFFU;
-#endif
-
-#if (RCAR_LSI == RCAR_D3)
-	reset_cr4 = 0x00000000U;
-	stop_cr4 = 0xFFFFFFFFU;
-	reset_cr5 = 0x00000000U;
-	stop_cr5 = 0xFFFFFFFFU;
-#else
-	reset_cr4 = 0x80000003U;
-	stop_cr4 = 0x7FFFFFFFU;
-	reset_cr5 = 0x40000000U;
-	stop_cr5 = 0xBFFFFFFFU;
-#endif
-
-	/* Secure Module Stop Control Registers */
-	cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
-	cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(SCMSTPCR2, stop_cr2);
-	cpg_write(SCMSTPCR3, 0xFFFFFFFFU);
-	cpg_write(SCMSTPCR4, stop_cr4);
-	cpg_write(SCMSTPCR5, stop_cr5);
-	cpg_write(SCMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(SCMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(SCMSTPCR8, 0xFFFFFFFFU);
-	cpg_write(SCMSTPCR9, 0xFFFDFFFFU);
-	cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
-	cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
-
-	/* Secure Software Reset Access Enable Control Registers */
-	cpg_write(SCSRSTECR0, 0x00000000U);
-	cpg_write(SCSRSTECR1, 0x00000000U);
-	cpg_write(SCSRSTECR2, reset_cr2);
-	cpg_write(SCSRSTECR3, 0x00000000U);
-	cpg_write(SCSRSTECR4, reset_cr4);
-	cpg_write(SCSRSTECR5, reset_cr5);
-	cpg_write(SCSRSTECR6, 0x00000000U);
-	cpg_write(SCSRSTECR7, 0x00000000U);
-	cpg_write(SCSRSTECR8, 0x00000000U);
-	cpg_write(SCSRSTECR9, 0x00020000U);
-	cpg_write(SCSRSTECR10, 0x00000000U);
-	cpg_write(SCSRSTECR11, 0x00000000U);
-}
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
-static void bl2_realtime_cpg_init_h3(void)
-{
-	uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
-	uint32_t cr0, cr8;
-
-	cr0 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ?
-	    0x00200000U : 0x00210000U;
-	cr8 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ?
-	    0x01F1FFF4U : 0x01F1FFF7U;
-
-	cpg_write(RMSTPCR0, cr0);
-	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR2, 0x040E0FDCU);
-	cpg_write(RMSTPCR3, 0xFFFFFFDFU);
-	cpg_write(RMSTPCR4, 0x80000004U);
-	cpg_write(RMSTPCR5, 0xC3FFFFFFU);
-	cpg_write(RMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR8, cr8);
-	cpg_write(RMSTPCR9, 0xFFFFFFFEU);
-	cpg_write(RMSTPCR10, 0xFFFEFFE0U);
-	cpg_write(RMSTPCR11, 0x000000B7U);
-}
-
-static void bl2_system_cpg_init_h3(void)
-{
-	/** System Module Stop Control Registers */
-	cpg_write(SMSTPCR0, 0x00210000U);
-	cpg_write(SMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR2, 0x040E2FDCU);
-	cpg_write(SMSTPCR3, 0xFFFFFBDFU);
-	cpg_write(SMSTPCR4, 0x80000004U);
-	cpg_write(SMSTPCR5, 0xC3FFFFFFU);
-	cpg_write(SMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR8, 0x01F1FFF5U);
-	cpg_write(SMSTPCR9, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR10, 0xFFFEFFE0U);
-	cpg_write(SMSTPCR11, 0x000000B7U);
-}
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
-static void bl2_realtime_cpg_init_m3(void)
-{
-	/* Realtime Module Stop Control Registers */
-	cpg_write(RMSTPCR0, 0x00200000U);
-	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR2, 0x040E0FDCU);
-	cpg_write(RMSTPCR3, 0xFFFFFFDFU);
-	cpg_write(RMSTPCR4, 0x80000004U);
-	cpg_write(RMSTPCR5, 0xC3FFFFFFU);
-	cpg_write(RMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR8, 0x01F1FFF7U);
-	cpg_write(RMSTPCR9, 0xFFFFFFFEU);
-	cpg_write(RMSTPCR10, 0xFFFEFFE0U);
-	cpg_write(RMSTPCR11, 0x000000B7U);
-}
-
-static void bl2_system_cpg_init_m3(void)
-{
-	/* System Module Stop Control Registers */
-	cpg_write(SMSTPCR0, 0x00200000U);
-	cpg_write(SMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR2, 0x040E2FDCU);
-	cpg_write(SMSTPCR3, 0xFFFFFBDFU);
-	cpg_write(SMSTPCR4, 0x80000004U);
-	cpg_write(SMSTPCR5, 0xC3FFFFFFU);
-	cpg_write(SMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR8, 0x01F1FFF7U);
-	cpg_write(SMSTPCR9, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR10, 0xFFFEFFE0U);
-	cpg_write(SMSTPCR11, 0x000000B7U);
-}
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
-static void bl2_realtime_cpg_init_m3n(void)
-{
-	/* Realtime Module Stop Control Registers */
-	cpg_write(RMSTPCR0, 0x00210000U);
-	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR2, 0x040E0FDCU);
-	cpg_write(RMSTPCR3, 0xFFFFFFDFU);
-	cpg_write(RMSTPCR4, 0x80000004U);
-	cpg_write(RMSTPCR5, 0xC3FFFFFFU);
-	cpg_write(RMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR8, 0x00F1FFF7U);
-	cpg_write(RMSTPCR9, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR10, 0xFFFFFFE0U);
-	cpg_write(RMSTPCR11, 0x000000B7U);
-}
-
-static void bl2_system_cpg_init_m3n(void)
-{
-	/* System Module Stop Control Registers */
-	cpg_write(SMSTPCR0, 0x00210000U);
-	cpg_write(SMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR2, 0x040E2FDCU);
-	cpg_write(SMSTPCR3, 0xFFFFFBDFU);
-	cpg_write(SMSTPCR4, 0x80000004U);
-	cpg_write(SMSTPCR5, 0xC3FFFFFFU);
-	cpg_write(SMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR8, 0x00F1FFF7U);
-	cpg_write(SMSTPCR9, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR10, 0xFFFFFFE0U);
-	cpg_write(SMSTPCR11, 0x000000B7U);
-}
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M)
-static void bl2_realtime_cpg_init_v3m(void)
-{
-	/* Realtime Module Stop Control Registers */
-	cpg_write(RMSTPCR0, 0x00230000U);
-	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR2, 0x14062FD8U);
-	cpg_write(RMSTPCR3, 0xFFFFFFDFU);
-	cpg_write(RMSTPCR4, 0x80000184U);
-	cpg_write(RMSTPCR5, 0x83FFFFFFU);
-	cpg_write(RMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR8, 0x7FF3FFF4U);
-	cpg_write(RMSTPCR9, 0xFFFFFFFEU);
-}
-
-static void bl2_system_cpg_init_v3m(void)
-{
-	/* System Module Stop Control Registers */
-	cpg_write(SMSTPCR0, 0x00210000U);
-	cpg_write(SMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR2, 0x340E2FDCU);
-	cpg_write(SMSTPCR3, 0xFFFFFBDFU);
-	cpg_write(SMSTPCR4, 0x80000004U);
-	cpg_write(SMSTPCR5, 0xC3FFFFFFU);
-	cpg_write(SMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR8, 0x01F1FFF5U);
-	cpg_write(SMSTPCR9, 0xFFFFFFFEU);
-}
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
-static void bl2_realtime_cpg_init_e3(void)
-{
-	/* Realtime Module Stop Control Registers */
-	cpg_write(RMSTPCR0, 0x00210000U);
-	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR2, 0x000E0FDCU);
-	cpg_write(RMSTPCR3, 0xFFFFFFDFU);
-	cpg_write(RMSTPCR4, 0x80000004U);
-	cpg_write(RMSTPCR5, 0xC3FFFFFFU);
-	cpg_write(RMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR8, 0x00F1FFF7U);
-	cpg_write(RMSTPCR9, 0xFFFFFFDFU);
-	cpg_write(RMSTPCR10, 0xFFFFFFE8U);
-	cpg_write(RMSTPCR11, 0x000000B7U);
-}
-
-static void bl2_system_cpg_init_e3(void)
-{
-	/* System Module Stop Control Registers */
-	cpg_write(SMSTPCR0, 0x00210000U);
-	cpg_write(SMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR2, 0x000E2FDCU);
-	cpg_write(SMSTPCR3, 0xFFFFFBDFU);
-	cpg_write(SMSTPCR4, 0x80000004U);
-	cpg_write(SMSTPCR5, 0xC3FFFFFFU);
-	cpg_write(SMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR8, 0x00F1FFF7U);
-	cpg_write(SMSTPCR9, 0xFFFFFFDFU);
-	cpg_write(SMSTPCR10, 0xFFFFFFE8U);
-	cpg_write(SMSTPCR11, 0x000000B7U);
-}
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
-static void bl2_realtime_cpg_init_d3(void)
-{
-	/* Realtime Module Stop Control Registers */
-	cpg_write(RMSTPCR0, 0x00010000U);
-	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR2, 0x00060FDCU);
-	cpg_write(RMSTPCR3, 0xFFFFFFDFU);
-	cpg_write(RMSTPCR4, 0x80000184U);
-	cpg_write(RMSTPCR5, 0x83FFFFFFU);
-	cpg_write(RMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(RMSTPCR8, 0x00F1FFF7U);
-	cpg_write(RMSTPCR9, 0xF3F5E016U);
-	cpg_write(RMSTPCR10, 0xFFFEFFE0U);
-	cpg_write(RMSTPCR11, 0x000000B7U);
-}
-
-static void bl2_system_cpg_init_d3(void)
-{
-	/* System Module Stop Control Registers */
-	cpg_write(SMSTPCR0, 0x00010000U);
-	cpg_write(SMSTPCR1, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR2, 0x00060FDCU);
-	cpg_write(SMSTPCR3, 0xFFFFFBDFU);
-	cpg_write(SMSTPCR4, 0x00000084U);
-	cpg_write(SMSTPCR5, 0x83FFFFFFU);
-	cpg_write(SMSTPCR6, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR7, 0xFFFFFFFFU);
-	cpg_write(SMSTPCR8, 0x00F1FFF7U);
-	cpg_write(SMSTPCR9, 0xF3F5E016U);
-	cpg_write(SMSTPCR10, 0xFFFEFFE0U);
-	cpg_write(SMSTPCR11, 0x000000B7U);
-}
-#endif
-
-void bl2_cpg_init(void)
-{
-	uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK;
-#if RCAR_LSI == RCAR_AUTO
-	uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
-#endif
-	bl2_secure_cpg_init();
-
-	if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
-	    boot_cpu == MODEMR_BOOT_CPU_CA53) {
-#if RCAR_LSI == RCAR_AUTO
-
-		switch (product) {
-		case PRR_PRODUCT_H3:
-			bl2_realtime_cpg_init_h3();
-			break;
-		case PRR_PRODUCT_M3:
-			bl2_realtime_cpg_init_m3();
-			break;
-		case PRR_PRODUCT_M3N:
-			bl2_realtime_cpg_init_m3n();
-			break;
-		case PRR_PRODUCT_V3M:
-			bl2_realtime_cpg_init_v3m();
-			break;
-		case PRR_PRODUCT_E3:
-			bl2_realtime_cpg_init_e3();
-			break;
-		case PRR_PRODUCT_D3:
-			bl2_realtime_cpg_init_d3();
-			break;
-		default:
-			panic();
-			break;
-		}
-#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
-		bl2_realtime_cpg_init_h3();
-#elif RCAR_LSI == RCAR_M3
-		bl2_realtime_cpg_init_m3();
-#elif RCAR_LSI == RCAR_M3N
-		bl2_realtime_cpg_init_m3n();
-#elif RCAR_LSI == RCAR_V3M
-		bl2_realtime_cpg_init_v3m();
-#elif RCAR_LSI == RCAR_E3
-		bl2_realtime_cpg_init_e3();
-#elif RCAR_LSI == RCAR_D3
-		bl2_realtime_cpg_init_d3();
-#else
-#error "Don't have CPG initialize routine(unknown)."
-#endif
-	}
-}
-
-void bl2_system_cpg_init(void)
-{
-#if RCAR_LSI == RCAR_AUTO
-	uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
-
-	switch (product) {
-	case PRR_PRODUCT_H3:
-		bl2_system_cpg_init_h3();
-		break;
-	case PRR_PRODUCT_M3:
-		bl2_system_cpg_init_m3();
-		break;
-	case PRR_PRODUCT_M3N:
-		bl2_system_cpg_init_m3n();
-		break;
-	case PRR_PRODUCT_V3M:
-		bl2_system_cpg_init_v3m();
-		break;
-	case PRR_PRODUCT_E3:
-		bl2_system_cpg_init_e3();
-		break;
-	case PRR_PRODUCT_D3:
-		bl2_system_cpg_init_d3();
-		break;
-	default:
-		panic();
-		break;
-	}
-#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
-	bl2_system_cpg_init_h3();
-#elif RCAR_LSI == RCAR_M3
-	bl2_system_cpg_init_m3();
-#elif RCAR_LSI == RCAR_M3N
-	bl2_system_cpg_init_m3n();
-#elif RCAR_LSI == RCAR_V3M
-	bl2_system_cpg_init_v3m();
-#elif RCAR_LSI == RCAR_E3
-	bl2_system_cpg_init_e3();
-#elif RCAR_LSI == RCAR_D3
-	bl2_system_cpg_init_d3();
-#else
-#error "Don't have CPG initialize routine(unknown)."
-#endif
-}
diff --git a/plat/renesas/rcar/bl2_interrupt_error.c b/plat/renesas/rcar/bl2_interrupt_error.c
deleted file mode 100644
index d9a4b8e..0000000
--- a/plat/renesas/rcar/bl2_interrupt_error.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <drivers/arm/gicv2.h>
-#include <lib/mmio.h>
-
-#include "rcar_def.h"
-
-#define SWDT_ERROR_ID	(1024U)
-#define SWDT_ERROR_TYPE	(16U)
-#define SWDT_CHAR_MAX	(13U)
-
-extern void rcar_swdt_release(void);
-
-void bl2_interrupt_error_id(uint32_t int_id)
-{
-	ERROR("\n");
-	if (int_id >= SWDT_ERROR_ID) {
-		ERROR("Unhandled exception occurred.\n");
-		ERROR("     Exception type = FIQ_SP_EL0\n");
-		panic();
-	}
-
-	/* Clear the interrupt request */
-	gicv2_end_of_interrupt((uint32_t) int_id);
-	rcar_swdt_release();
-	ERROR("Unhandled exception occurred.\n");
-	ERROR("     Exception type = FIQ_SP_EL0\n");
-	ERROR("     SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
-	ERROR("     ELR_EL3  = 0x%x\n", (uint32_t) read_elr_el3());
-	ERROR("     ESR_EL3  = 0x%x\n", (uint32_t) read_esr_el3());
-	ERROR("     FAR_EL3  = 0x%x\n", (uint32_t) read_far_el3());
-	ERROR("\n");
-	panic();
-}
-
-void bl2_interrupt_error_type(uint32_t ex_type)
-{
-	const uint8_t interrupt_ex[SWDT_ERROR_TYPE][SWDT_CHAR_MAX] = {
-		"SYNC SP EL0",
-		"IRQ SP EL0",
-		"FIQ SP EL0",
-		"SERR SP EL0",
-		"SYNC SP ELx",
-		"IRQ SP ELx",
-		"FIQ SP ELx",
-		"SERR SP ELx",
-		"SYNC AARCH64",
-		"IRQ AARCH64",
-		"FIQ AARCH64",
-		"SERR AARCH64",
-		"SYNC AARCH32",
-		"IRQ AARCH32",
-		"FIQ AARCH32",
-		"SERR AARCH32"
-	};
-	char msg[128];
-
-	/* Clear the interrupt request  */
-	if (ex_type >= SWDT_ERROR_TYPE) {
-		ERROR("\n");
-		ERROR("Unhandled exception occurred.\n");
-		ERROR("     Exception type = Unknown (%d)\n", ex_type);
-		goto loop;
-	}
-
-	rcar_swdt_release();
-	ERROR("\n");
-	ERROR("Unhandled exception occurred.\n");
-	snprintf(msg, sizeof(msg), "     Exception type = %s\n",
-		 &interrupt_ex[ex_type][0]);
-	ERROR("%s", msg);
-	switch (ex_type) {
-	case SYNC_EXCEPTION_SP_EL0:
-		ERROR("     SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
-		ERROR("     ELR_EL3  = 0x%x\n", (uint32_t) read_elr_el3());
-		ERROR("     ESR_EL3  = 0x%x\n", (uint32_t) read_esr_el3());
-		ERROR("     FAR_EL3  = 0x%x\n", (uint32_t) read_far_el3());
-		break;
-	case IRQ_SP_EL0:
-		ERROR("     SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
-		ERROR("     ELR_EL3  = 0x%x\n", (uint32_t) read_elr_el3());
-		ERROR("     IAR_EL3  = 0x%x\n", gicv2_acknowledge_interrupt());
-		break;
-	case FIQ_SP_EL0:
-		ERROR("     SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
-		ERROR("     ELR_EL3  = 0x%x\n", (uint32_t) read_elr_el3());
-		ERROR("     IAR_EL3  = 0x%x\n", gicv2_acknowledge_interrupt());
-		break;
-	case SERROR_SP_EL0:
-		ERROR("     SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
-		ERROR("     ELR_EL3  = 0x%x\n", (uint32_t) read_elr_el3());
-		ERROR("     ESR_EL3  = 0x%x\n", (uint32_t) read_esr_el3());
-		ERROR("     FAR_EL3  = 0x%x\n", (uint32_t) read_far_el3());
-		break;
-	default:
-		break;
-	}
-loop:
-	ERROR("\n");
-	panic();
-}
diff --git a/plat/renesas/rcar/bl2_plat_mem_params_desc.c b/plat/renesas/rcar/bl2_plat_mem_params_desc.c
deleted file mode 100644
index bf2706d..0000000
--- a/plat/renesas/rcar/bl2_plat_mem_params_desc.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/bl_common.h>
-#include <common/desc_image_load.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <plat/common/platform.h>
-
-#if (RCAR_BL33_EXECUTION_EL != 0) && (RCAR_BL33_EXECUTION_EL != 1)
-#error
-#endif
-
-#if (RCAR_BL33_EXECUTION_EL == 0)
-#define BL33_MODE MODE_EL1
-#else
-#define BL33_MODE MODE_EL2
-#endif
-
-extern uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)];
-
-static bl_mem_params_node_t bl2_mem_params_descs[] = {
-	{
-		.image_id = BL31_IMAGE_ID,
-
-		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
-			entry_point_info_t, SECURE | EXECUTABLE | EP_FIRST_EXE),
-		.ep_info.spsr = SPSR_64(MODE_EL3,
-			MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
-		.ep_info.pc = BL31_BASE,
-
-
-		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
-			image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
-		.image_info.image_base = BL31_BASE,
-
-# ifdef BL32_BASE
-		.next_handoff_image_id = BL32_IMAGE_ID,
-# else
-		.next_handoff_image_id = BL33_IMAGE_ID,
-# endif
-	},
-# ifdef BL32_BASE
-	{
-		.image_id = BL32_IMAGE_ID,
-
-		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
-			entry_point_info_t, SECURE | EXECUTABLE),
-		.ep_info.pc = BL32_BASE,
-		.ep_info.spsr = 0,
-		.ep_info.args.arg3 = (uintptr_t)fdt_blob,
-
-		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
-			image_info_t, 0),
-		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
-		.image_info.image_base = BL32_BASE,
-
-		.next_handoff_image_id = BL33_IMAGE_ID,
-	},
-#endif
-	{
-		.image_id = BL33_IMAGE_ID,
-
-		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
-			entry_point_info_t, NON_SECURE | EXECUTABLE),
-		.ep_info.spsr = SPSR_64(BL33_MODE, MODE_SP_ELX,
-			DISABLE_ALL_EXCEPTIONS),
-		.ep_info.pc = BL33_BASE,
-#ifdef RCAR_BL33_ARG0
-		.ep_info.args.arg0 = RCAR_BL33_ARG0,
-#endif
-		.ep_info.args.arg1 = (uintptr_t)fdt_blob,
-		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
-			image_info_t, 0),
-		.image_info.image_max_size =
-				(uint32_t) (DRAM_LIMIT - BL33_BASE),
-		.image_info.image_base = BL33_BASE,
-
-		.next_handoff_image_id = INVALID_IMAGE_ID,
-	}
-};
-
-REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/renesas/rcar/bl2_secure_setting.c b/plat/renesas/rcar/bl2_secure_setting.c
deleted file mode 100644
index 095d1f6..0000000
--- a/plat/renesas/rcar/bl2_secure_setting.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-#include <lib/utils_def.h>
-
-#include "axi_registers.h"
-#include "lifec_registers.h"
-#include "micro_delay.h"
-
-static void lifec_security_setting(void);
-static void axi_security_setting(void);
-
-static const struct {
-	uint32_t reg;
-	uint32_t val;
-} lifec[] = {
-	/*
-	 * LIFEC0 (SECURITY) settings
-	 * Security attribute setting for master ports
-	 * Bit 0: ARM realtime core (Cortex-R7) master port
-	 *        0: Non-Secure
-	 */
-	{ SEC_SRC, 0x0000001EU },
-	/*
-	 * Security attribute setting for slave ports 0 to 15
-	 *      {SEC_SEL0,              0xFFFFFFFFU},
-	 *      {SEC_SEL1,              0xFFFFFFFFU},
-	 *	{SEC_SEL2,              0xFFFFFFFFU},
-	 * Bit19: AXI-Bus (Main Memory domain AXI) slave ports
-	 *        0: registers accessed from secure resource only
-	 * Bit 9: DBSC4 register access slave ports.
-	 *        0: registers accessed from secure resource only.
-	 */
-#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
-	{ SEC_SEL3, 0xFFF7FDFFU },
-#else /* LIFEC_DBSC_PROTECT_ENABLE == 1 */
-	{ SEC_SEL3, 0xFFFFFFFFU },
-#endif /* LIFEC_DBSC_PROTECT_ENABLE == 1 */
-	/*
-	 *	{SEC_SEL4,              0xFFFFFFFFU},
-	 * Bit 6: Boot ROM slave ports.
-	 *        0: registers accessed from secure resource only
-	 */
-	{ SEC_SEL5, 0xFFFFFFBFU },
-	/*
-	 * Bit13: SCEG PKA (secure APB) slave ports
-	 *        0: registers accessed from secure resource only
-	 *        1: Reserved[R-Car E3]
-	 * Bit12: SCEG PKA (public APB) slave ports
-	 *	  0: registers accessed from secure resource only
-	 *	  1: Reserved[R-Car E3]
-	 * Bit10: SCEG Secure Core slave ports
-	 *	  0: registers accessed from secure resource only
-	 */
-#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
-	{ SEC_SEL6, 0xFFFFFBFFU },
-#else /*  (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) */
-	{ SEC_SEL6, 0xFFFFCBFFU },
-#endif /*  (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) */
-	/*
-	 *	{SEC_SEL7,              0xFFFFFFFFU},
-	 *	{SEC_SEL8,              0xFFFFFFFFU},
-	 *	{SEC_SEL9,              0xFFFFFFFFU},
-	 *	{SEC_SEL10,             0xFFFFFFFFU},
-	 *	{SEC_SEL11,             0xFFFFFFFFU},
-	 *	{SEC_SEL12,             0xFFFFFFFFU},
-	 * Bit22: RPC slave ports.
-	 *	  0: registers accessed from secure resource only.
-	 */
-#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
-	{ SEC_SEL13, 0xFFBFFFFFU },
-#endif /* (RCAR_RPC_HYPERFLASH_LOCKED == 1) */
-	/*
-	 * Bit27: System Timer (SCMT) slave ports
-	 *	  0: registers accessed from secure resource only
-	 * Bit26: System Watchdog Timer (SWDT) slave ports
-	 *	  0: registers accessed from secure resource only
-	 */
-	{ SEC_SEL14, 0xF3FFFFFFU },
-	/*
-	 * Bit13: RST slave ports.
-	 *	  0: registers accessed from secure resource only
-	 * Bit 7: Life Cycle 0 slave ports
-	 *	  0: registers accessed from secure resource only
-	 */
-	{ SEC_SEL15, 0xFFFFFF3FU },
-	/*
-	 * Security group 0 attribute setting for master ports 0
-	 * Security group 1 attribute setting for master ports 0
-	 *	{SEC_GRP0CR0,           0x00000000U},
-	 *	{SEC_GRP1CR0,           0x00000000U},
-	 * Security group 0 attribute setting for master ports 1
-	 * Security group 1 attribute setting for master ports 1
-	 *	{SEC_GRP0CR1,           0x00000000U},
-	 *	{SEC_GRP1CR1,           0x00000000U},
-	 * Security group 0 attribute setting for master ports 2
-	 * Security group 1 attribute setting for master ports 2
-	 * Bit17: SCEG Secure Core master ports.
-	 *	  SecurityGroup3
-	 */
-	{ SEC_GRP0CR2, 0x00020000U },
-	{ SEC_GRP1CR2, 0x00020000U },
-	/*
-	 * Security group 0 attribute setting for master ports 3
-	 * Security group 1 attribute setting for master ports 3
-	 *	{SEC_GRP0CR3,           0x00000000U},
-	 *	{SEC_GRP1CR3,           0x00000000U},
-	 * Security group 0 attribute setting for slave ports 0
-	 * Security group 1 attribute setting for slave ports 0
-	 *	{SEC_GRP0COND0,         0x00000000U},
-	 *	{SEC_GRP1COND0,         0x00000000U},
-	 * Security group 0 attribute setting for slave ports 1
-	 * Security group 1 attribute setting for slave ports 1
-	 *	{SEC_GRP0COND1,         0x00000000U},
-	 *	{SEC_GRP1COND1,         0x00000000U},
-	 * Security group 0 attribute setting for slave ports 2
-	 * Security group 1 attribute setting for slave ports 2
-	 *	{SEC_GRP0COND2,         0x00000000U},
-	 *	{SEC_GRP1COND2,         0x00000000U},
-	 * Security group 0 attribute setting for slave ports 3
-	 * Security group 1 attribute setting for slave ports 3
-	 * Bit19: AXI-Bus (Main Memory domain AXI) slave ports.
-	 *	  SecurityGroup3
-	 * Bit 9: DBSC4 register access slave ports.
-	 *        SecurityGroup3
-	 */
-#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
-	{ SEC_GRP0COND3, 0x00080200U },
-	{ SEC_GRP1COND3, 0x00080200U },
-#else /* (LIFEC_DBSC_PROTECT_ENABLE == 1) */
-	{ SEC_GRP0COND3, 0x00000000U },
-	{ SEC_GRP1COND3, 0x00000000U },
-#endif /* (LIFEC_DBSC_PROTECT_ENABLE == 1) */
-	/*
-	 * Security group 0 attribute setting for slave ports 4
-	 * Security group 1 attribute setting for slave ports 4
-	 *	{SEC_GRP0COND4,         0x00000000U},
-	 *	{SEC_GRP1COND4,         0x00000000U},
-	 * Security group 0 attribute setting for slave ports 5
-	 * Security group 1 attribute setting for slave ports 5
-	 * Bit 6: Boot ROM slave ports
-	 *	  SecurityGroup3
-	 */
-	{ SEC_GRP0COND5, 0x00000040U },
-	{ SEC_GRP1COND5, 0x00000040U },
-	/*
-	 * Security group 0 attribute setting for slave ports 6
-	 * Security group 1 attribute setting for slave ports 6
-	 * Bit13: SCEG PKA (secure APB) slave ports
-	 *	  SecurityGroup3
-	 *	  Reserved[R-Car E3]
-	 * Bit12: SCEG PKA (public APB) slave ports
-	 *	  SecurityGroup3
-	 *	  Reserved[R-Car E3]
-	 * Bit10: SCEG Secure Core slave ports
-	 *	  SecurityGroup3
-	 */
-#if RCAR_LSI == RCAR_E3
-	{ SEC_GRP0COND6, 0x00000400U },
-	{ SEC_GRP1COND6, 0x00000400U },
-#else /* RCAR_LSI == RCAR_E3 */
-	{ SEC_GRP0COND6, 0x00003400U },
-	{ SEC_GRP1COND6, 0x00003400U },
-#endif /* RCAR_LSI == RCAR_E3 */
-	/*
-	 * Security group 0 attribute setting for slave ports 7
-	 * Security group 1 attribute setting for slave ports 7
-	 *	{SEC_GRP0COND7,         0x00000000U},
-	 *	{SEC_GRP1COND7,         0x00000000U},
-	 * Security group 0 attribute setting for slave ports 8
-	 * Security group 1 attribute setting for slave ports 8
-	 *	{SEC_GRP0COND8,         0x00000000U},
-	 *	{SEC_GRP1COND8,         0x00000000U},
-	 * Security group 0 attribute setting for slave ports 9
-	 * Security group 1 attribute setting for slave ports 9
-	 *	{SEC_GRP0COND9,         0x00000000U},
-	 *	{SEC_GRP1COND9,         0x00000000U},
-	 * Security group 0 attribute setting for slave ports 10
-	 * Security group 1 attribute setting for slave ports 10
-	 *	{SEC_GRP0COND10,        0x00000000U},
-	 *	{SEC_GRP1COND10,        0x00000000U},
-	 * Security group 0 attribute setting for slave ports 11
-	 * Security group 1 attribute setting for slave ports 11
-	 *	{SEC_GRP0COND11,        0x00000000U},
-	 *	{SEC_GRP1COND11,        0x00000000U},
-	 * Security group 0 attribute setting for slave ports 12
-	 * Security group 1 attribute setting for slave ports 12
-	 *	{SEC_GRP0COND12,        0x00000000U},
-	 *	{SEC_GRP1COND12,        0x00000000U},
-	 * Security group 0 attribute setting for slave ports 13
-	 * Security group 1 attribute setting for slave ports 13
-	 * Bit22: RPC slave ports.
-	 *	  SecurityGroup3
-	 */
-#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
-	    { SEC_GRP0COND13,     0x00400000U },
-	    { SEC_GRP1COND13,     0x00400000U },
-#endif /* (RCAR_RPC_HYPERFLASH_LOCKED == 1) */
-	/*
-	 * Security group 0 attribute setting for slave ports 14
-	 * Security group 1 attribute setting for slave ports 14
-	 * Bit26: System Timer (SCMT) slave ports
-	 *	  SecurityGroup3
-	 * Bit27: System Watchdog Timer (SWDT) slave ports
-	 *	  SecurityGroup3
-	 */
-	{ SEC_GRP0COND14, 0x0C000000U },
-	{ SEC_GRP1COND14, 0x0C000000U },
-	/*
-	 * Security group 0 attribute setting for slave ports 15
-	 * Security group 1 attribute setting for slave ports 15
-	 * Bit13: RST slave ports
-	 *	  SecurityGroup3
-	 * Bit 7: Life Cycle 0 slave ports
-	 *	  SecurityGroup3
-	 * Bit 6: TDBG slave ports
-	 *	  SecurityGroup3
-	 */
-	{ SEC_GRP0COND15, 0x000000C0U },
-	{ SEC_GRP1COND15, 0x000000C0U },
-	/*
-	 * Security write protection attribute setting slave ports 0
-	 *	{SEC_READONLY0,         0x00000000U},
-	 * Security write protection attribute setting slave ports 1
-	 *	{SEC_READONLY1,         0x00000000U},
-	 * Security write protection attribute setting slave ports 2
-	 *	{SEC_READONLY2,         0x00000000U},
-	 * Security write protection attribute setting slave ports 3
-	 *	{SEC_READONLY3,         0x00000000U},
-	 * Security write protection attribute setting slave ports 4
-	 *	{SEC_READONLY4,         0x00000000U},
-	 * Security write protection attribute setting slave ports 5
-	 *	{SEC_READONLY5,         0x00000000U},
-	 * Security write protection attribute setting slave ports 6
-	 *	{SEC_READONLY6,         0x00000000U},
-	 * Security write protection attribute setting slave ports 7
-	 *	{SEC_READONLY7,         0x00000000U},
-	 * Security write protection attribute setting slave ports 8
-	 *	{SEC_READONLY8,         0x00000000U},
-	 * Security write protection attribute setting slave ports 9
-	 *	{SEC_READONLY9,         0x00000000U},
-	 * Security write protection attribute setting slave ports 10
-	 *	{SEC_READONLY10,        0x00000000U},
-	 * Security write protection attribute setting slave ports 11
-	 *	{SEC_READONLY11,        0x00000000U},
-	 * Security write protection attribute setting slave ports 12
-	 *	{SEC_READONLY12,        0x00000000U},
-	 * Security write protection attribute setting slave ports 13
-	 *	{SEC_READONLY13,        0x00000000U},
-	 * Security write protection attribute setting slave ports 14
-	 *	{SEC_READONLY14,        0x00000000U},
-	 * Security write protection attribute setting slave ports 15
-	 *	{SEC_READONLY15,        0x00000000U}
-	 */
-};
-
-/* AXI settings */
-static const struct {
-	uint32_t reg;
-	uint32_t val;
-} axi[] = {
-	/*
-	 * DRAM protection
-	 * AXI dram protected area division
-	 */
-	{AXI_DPTDIVCR0,  0x0E0403F0U},
-	{AXI_DPTDIVCR1,  0x0E0407E0U},
-	{AXI_DPTDIVCR2,  0x0E080000U},
-	{AXI_DPTDIVCR3,  0x0E080000U},
-	{AXI_DPTDIVCR4,  0x0E080000U},
-	{AXI_DPTDIVCR5,  0x0E080000U},
-	{AXI_DPTDIVCR6,  0x0E080000U},
-	{AXI_DPTDIVCR7,  0x0E080000U},
-	{AXI_DPTDIVCR8,  0x0E080000U},
-	{AXI_DPTDIVCR9,  0x0E080000U},
-	{AXI_DPTDIVCR10, 0x0E080000U},
-	{AXI_DPTDIVCR11, 0x0E080000U},
-	{AXI_DPTDIVCR12, 0x0E080000U},
-	{AXI_DPTDIVCR13, 0x0E080000U},
-	{AXI_DPTDIVCR14, 0x0E080000U},
-	/* AXI dram protected area setting */
-	{AXI_DPTCR0,  0x0E000000U},
-	{AXI_DPTCR1,  0x0E000E0EU},
-	{AXI_DPTCR2,  0x0E000000U},
-	{AXI_DPTCR3,  0x0E000000U},
-	{AXI_DPTCR4,  0x0E000000U},
-	{AXI_DPTCR5,  0x0E000000U},
-	{AXI_DPTCR6,  0x0E000000U},
-	{AXI_DPTCR7,  0x0E000000U},
-	{AXI_DPTCR8,  0x0E000000U},
-	{AXI_DPTCR9,  0x0E000000U},
-	{AXI_DPTCR10, 0x0E000000U},
-	{AXI_DPTCR11, 0x0E000000U},
-	{AXI_DPTCR12, 0x0E000000U},
-	{AXI_DPTCR13, 0x0E000000U},
-	{AXI_DPTCR14, 0x0E000000U},
-	{AXI_DPTCR15, 0x0E000000U},
-	/*
-	 * SRAM ptotection
-	 * AXI sram protected area division
-	 */
-	{AXI_SPTDIVCR0,  0x0E0E6304U},
-	{AXI_SPTDIVCR1,  0x0E0E6360U},
-	{AXI_SPTDIVCR2,  0x0E0E6360U},
-	{AXI_SPTDIVCR3,  0x0E0E6360U},
-	{AXI_SPTDIVCR4,  0x0E0E6360U},
-	{AXI_SPTDIVCR5,  0x0E0E6360U},
-	{AXI_SPTDIVCR6,  0x0E0E6360U},
-	{AXI_SPTDIVCR7,  0x0E0E6360U},
-	{AXI_SPTDIVCR8,  0x0E0E6360U},
-	{AXI_SPTDIVCR9,  0x0E0E6360U},
-	{AXI_SPTDIVCR10, 0x0E0E6360U},
-	{AXI_SPTDIVCR11, 0x0E0E6360U},
-	{AXI_SPTDIVCR12, 0x0E0E6360U},
-	{AXI_SPTDIVCR13, 0x0E0E6360U},
-	{AXI_SPTDIVCR14, 0x0E0E6360U},
-	/* AXI sram protected area setting */
-	{AXI_SPTCR0,  0x0E000E0EU},
-	{AXI_SPTCR1,  0x0E000000U},
-	{AXI_SPTCR2,  0x0E000000U},
-	{AXI_SPTCR3,  0x0E000000U},
-	{AXI_SPTCR4,  0x0E000000U},
-	{AXI_SPTCR5,  0x0E000000U},
-	{AXI_SPTCR6,  0x0E000000U},
-	{AXI_SPTCR7,  0x0E000000U},
-	{AXI_SPTCR8,  0x0E000000U},
-	{AXI_SPTCR9,  0x0E000000U},
-	{AXI_SPTCR10, 0x0E000000U},
-	{AXI_SPTCR11, 0x0E000000U},
-	{AXI_SPTCR12, 0x0E000000U},
-	{AXI_SPTCR13, 0x0E000000U},
-	{AXI_SPTCR14, 0x0E000000U},
-	{AXI_SPTCR15, 0x0E000000U}
-};
-
-static void lifec_security_setting(void)
-{
-	uint32_t i;
-
-	for (i = 0; i < ARRAY_SIZE(lifec); i++)
-		mmio_write_32(lifec[i].reg, lifec[i].val);
-}
-
-/* SRAM/DRAM protection setting */
-static void axi_security_setting(void)
-{
-	uint32_t i;
-
-	for (i = 0; i < ARRAY_SIZE(axi); i++)
-		mmio_write_32(axi[i].reg, axi[i].val);
-}
-
-void bl2_secure_setting(void)
-{
-	lifec_security_setting();
-	axi_security_setting();
-	rcar_micro_delay(10U);
-}
diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c
deleted file mode 100644
index 93798ac..0000000
--- a/plat/renesas/rcar/bl31_plat_setup.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stddef.h>
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <bl31/bl31.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/cci.h>
-#include <drivers/console.h>
-#include <lib/mmio.h>
-#include <plat/common/platform.h>
-
-#include "pwrc.h"
-#include "rcar_def.h"
-#include "rcar_private.h"
-#include "rcar_version.h"
-
-static const uint64_t BL31_RO_BASE		= BL_CODE_BASE;
-static const uint64_t BL31_RO_LIMIT		= BL_CODE_END;
-
-#if USE_COHERENT_MEM
-static const uint64_t BL31_COHERENT_RAM_BASE	= BL_COHERENT_RAM_BASE;
-static const uint64_t BL31_COHERENT_RAM_LIMIT	= BL_COHERENT_RAM_END;
-#endif /* USE_COHERENT_MEM */
-
-extern void plat_rcar_gic_driver_init(void);
-extern void plat_rcar_gic_init(void);
-
-u_register_t rcar_boot_mpidr;
-
-static int cci_map[] = {
-	CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3,
-	CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3
-};
-
-void plat_cci_init(void)
-{
-	uint32_t prd;
-
-	prd = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
-
-	if (PRR_PRODUCT_H3_CUT10 == prd || PRR_PRODUCT_H3_CUT11 == prd) {
-		cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX;
-		cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX;
-	}
-
-	cci_init(RCAR_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
-}
-
-void plat_cci_enable(void)
-{
-	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
-}
-
-void plat_cci_disable(void)
-{
-	cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
-}
-
-struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
-{
-	bl2_to_bl31_params_mem_t *from_bl2 = (bl2_to_bl31_params_mem_t *)
-					     PARAMS_BASE;
-	entry_point_info_t *next_image_info;
-
-	next_image_info = (type == NON_SECURE) ?
-		&from_bl2->bl33_ep_info : &from_bl2->bl32_ep_info;
-
-	return next_image_info->pc ? next_image_info : NULL;
-}
-
-void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
-				u_register_t arg2, u_register_t arg3)
-{
-	rcar_console_runtime_init();
-
-	NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
-
-#if RCAR_LSI != RCAR_D3
-	if (rcar_pwrc_get_cluster() == RCAR_CLUSTER_A53A57) {
-		plat_cci_init();
-		plat_cci_enable();
-	}
-#endif /* RCAR_LSI != RCAR_D3 */
-}
-
-void bl31_plat_arch_setup(void)
-{
-	rcar_configure_mmu_el3(BL31_BASE,
-			       BL31_LIMIT - BL31_BASE,
-			       BL31_RO_BASE, BL31_RO_LIMIT
-#if USE_COHERENT_MEM
-			       , BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT
-#endif /* USE_COHERENT_MEM */
-	    );
-	rcar_pwrc_code_copy_to_system_ram();
-}
-
-void bl31_platform_setup(void)
-{
-	plat_rcar_gic_driver_init();
-	plat_rcar_gic_init();
-
-	/* enable the system level generic timer */
-	mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
-
-	rcar_pwrc_setup();
-#if 0
-	/*
-	 * TODO: there is a broad number of rcar-gen3 SoC configurations; to
-	 * support all of them, Renesas use the pwrc driver to discover what
-	 * cores are on/off before announcing the topology.
-	 * This code hasnt been ported yet
-	 */
-
-	rcar_setup_topology();
-#endif
-
-	/*
-	 * mask should match the kernel's MPIDR_HWID_BITMASK so the core can be
-	 * identified during cpuhotplug (check the kernel's psci migrate set of
-	 * functions
-	 */
-	rcar_boot_mpidr = read_mpidr_el1() & 0x0000ffffU;
-}
diff --git a/plat/renesas/rcar/plat_image_load.c b/plat/renesas/rcar/plat_image_load.c
deleted file mode 100644
index 9d814a6..0000000
--- a/plat/renesas/rcar/plat_image_load.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/bl_common.h>
-#include <common/desc_image_load.h>
-#include <plat/common/platform.h>
-
-extern void bl2_plat_flush_bl31_params(void);
-
-/*******************************************************************************
- * This function flushes the data structures so that they are visible
- * in memory for the next BL image.
- ******************************************************************************/
-void plat_flush_next_bl_params(void)
-{
-#if IMAGE_BL2
-	bl2_plat_flush_bl31_params();
-#endif
-}
-
-/*******************************************************************************
- * This function returns the list of loadable images.
- ******************************************************************************/
-bl_load_info_t *plat_get_bl_image_load_info(void)
-{
-	return get_bl_load_info_from_mem_params_desc();
-}
-
-/*******************************************************************************
- * This function returns the list of executable images.
- ******************************************************************************/
-bl_params_t *plat_get_next_bl_params(void)
-{
-	return get_next_bl_params_from_mem_params_desc();
-}
diff --git a/plat/renesas/rcar/plat_pm.c b/plat/renesas/rcar/plat_pm.c
deleted file mode 100644
index 7ec78cc..0000000
--- a/plat/renesas/rcar/plat_pm.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <errno.h>
-
-#include <arch_helpers.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/cci.h>
-#include <drivers/arm/gicv2.h>
-#include <lib/bakery_lock.h>
-#include <lib/mmio.h>
-#include <lib/psci/psci.h>
-#include <plat/common/platform.h>
-
-#include "iic_dvfs.h"
-#include "platform_def.h"
-#include "pwrc.h"
-#include "rcar_def.h"
-#include "rcar_private.h"
-#include "ulcb_cpld.h"
-
-#define DVFS_SET_VID_0V		(0x00)
-#define P_ALL_OFF		(0x80)
-#define KEEPON_DDR1C		(0x08)
-#define KEEPON_DDR0C		(0x04)
-#define KEEPON_DDR1		(0x02)
-#define KEEPON_DDR0		(0x01)
-
-#define SYSTEM_PWR_STATE(s)	((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
-#define CLUSTER_PWR_STATE(s)	((s)->pwr_domain_state[MPIDR_AFFLVL1])
-#define CORE_PWR_STATE(s)	((s)->pwr_domain_state[MPIDR_AFFLVL0])
-
-extern void rcar_pwrc_restore_generic_timer(uint64_t *stack);
-extern void plat_rcar_gic_driver_init(void);
-extern void plat_rcar_gic_init(void);
-extern u_register_t rcar_boot_mpidr;
-
-static uintptr_t rcar_sec_entrypoint;
-
-static void rcar_program_mailbox(uint64_t mpidr, uint64_t address)
-{
-	mailbox_t *rcar_mboxes = (mailbox_t *) MBOX_BASE;
-	uint64_t linear_id = plat_core_pos_by_mpidr(mpidr);
-	unsigned long range;
-
-	rcar_mboxes[linear_id].value = address;
-	range = (unsigned long)&rcar_mboxes[linear_id];
-
-	flush_dcache_range(range, sizeof(range));
-}
-
-static void rcar_cpu_standby(plat_local_state_t cpu_state)
-{
-	u_register_t scr_el3 = read_scr_el3();
-
-	write_scr_el3(scr_el3 | SCR_IRQ_BIT);
-	dsb();
-	wfi();
-	write_scr_el3(scr_el3);
-}
-
-static int rcar_pwr_domain_on(u_register_t mpidr)
-{
-	rcar_program_mailbox(mpidr, rcar_sec_entrypoint);
-	rcar_pwrc_cpuon(mpidr);
-
-	return PSCI_E_SUCCESS;
-}
-
-static void rcar_pwr_domain_on_finish(const psci_power_state_t *target_state)
-{
-	uint32_t cluster_type = rcar_pwrc_get_cluster();
-	unsigned long mpidr = read_mpidr_el1();
-
-	if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
-		if (cluster_type == RCAR_CLUSTER_A53A57)
-			plat_cci_enable();
-
-	rcar_pwrc_disable_interrupt_wakeup(mpidr);
-	rcar_program_mailbox(mpidr, 0);
-
-	gicv2_cpuif_enable();
-	gicv2_pcpu_distif_init();
-}
-
-static void rcar_pwr_domain_off(const psci_power_state_t *target_state)
-{
-#if RCAR_LSI != RCAR_D3
-	uint32_t cluster_type = rcar_pwrc_get_cluster();
-#endif
-	unsigned long mpidr = read_mpidr_el1();
-
-	gicv2_cpuif_disable();
-	rcar_pwrc_cpuoff(mpidr);
-
-#if RCAR_LSI != RCAR_D3
-	if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
-		if (cluster_type == RCAR_CLUSTER_A53A57)
-			plat_cci_disable();
-
-		rcar_pwrc_clusteroff(mpidr);
-	}
-#endif
-}
-
-static void rcar_pwr_domain_suspend(const psci_power_state_t *target_state)
-{
-	uint32_t cluster_type = rcar_pwrc_get_cluster();
-	unsigned long mpidr = read_mpidr_el1();
-
-	if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
-		return;
-
-	rcar_program_mailbox(mpidr, rcar_sec_entrypoint);
-	rcar_pwrc_enable_interrupt_wakeup(mpidr);
-	gicv2_cpuif_disable();
-	rcar_pwrc_cpuoff(mpidr);
-
-	if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
-		if (cluster_type == RCAR_CLUSTER_A53A57)
-			plat_cci_disable();
-
-		rcar_pwrc_clusteroff(mpidr);
-	}
-
-#if RCAR_SYSTEM_SUSPEND
-	if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
-		rcar_pwrc_suspend_to_ram();
-#endif
-}
-
-static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
-					   *target_state)
-{
-	uint32_t cluster_type = rcar_pwrc_get_cluster();
-
-	if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
-		goto finish;
-
-	plat_rcar_gic_driver_init();
-	plat_rcar_gic_init();
-
-	if (cluster_type == RCAR_CLUSTER_A53A57)
-		plat_cci_init();
-
-	rcar_pwrc_restore_timer_state();
-	rcar_pwrc_setup();
-	rcar_pwrc_code_copy_to_system_ram();
-
-#if RCAR_SYSTEM_SUSPEND
-	rcar_pwrc_init_suspend_to_ram();
-#endif
-finish:
-	rcar_pwr_domain_on_finish(target_state);
-}
-
-static void __dead2 rcar_system_off(void)
-{
-#if PMIC_ROHM_BD9571
-#if PMIC_LEVEL_MODE
-	if (rcar_iic_dvfs_send(PMIC, DVFS_SET_VID, DVFS_SET_VID_0V))
-		ERROR("BL3-1:Failed the SYSTEM-OFF.\n");
-#else
-	if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
-		ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
-#endif
-#else
-	uint64_t cpu = read_mpidr_el1() & 0x0000ffff;
-	int32_t rtn_on;
-
-	rtn_on = rcar_pwrc_cpu_on_check(cpu);
-
-	if (cpu == rcar_boot_mpidr)
-		panic();
-
-	if (rtn_on)
-		panic();
-
-	rcar_pwrc_cpuoff(cpu);
-	rcar_pwrc_clusteroff(cpu);
-
-#endif /* PMIC_ROHM_BD9571 */
-	wfi();
-	ERROR("RCAR System Off: operation not handled.\n");
-	panic();
-}
-
-static void __dead2 rcar_system_reset(void)
-{
-#if PMIC_ROHM_BD9571
-#if PMIC_LEVEL_MODE
-#if RCAR_SYSTEM_RESET_KEEPON_DDR
-	uint8_t mode;
-	int32_t error;
-
-	error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, KEEP10_MAGIC);
-	if (error) {
-		ERROR("Failed send KEEP10 magic ret=%d\n", error);
-		goto done;
-	}
-
-	error = rcar_iic_dvfs_receive(PMIC, BKUP_MODE_CNT, &mode);
-	if (error) {
-		ERROR("Failed receive BKUP_Mode_Cnt ret=%d\n", error);
-		goto done;
-	}
-
-	mode |= KEEPON_DDR1C | KEEPON_DDR0C | KEEPON_DDR1 | KEEPON_DDR0;
-	error = rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, mode);
-	if (error) {
-		ERROR("Failed send KEEPON_DDRx ret=%d\n", error);
-		goto done;
-	}
-
-	rcar_pwrc_set_suspend_to_ram();
-done:
-#else
-	if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
-		ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
-#endif
-#else
-#if (RCAR_GEN3_ULCB == 1)
-	rcar_cpld_reset_cpu();
-#endif
-#endif
-#else
-	rcar_pwrc_system_reset();
-#endif
-	wfi();
-
-	ERROR("RCAR System Reset: operation not handled.\n");
-	panic();
-}
-
-static int rcar_validate_power_state(unsigned int power_state,
-				    psci_power_state_t *req_state)
-{
-	unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
-	unsigned int pstate = psci_get_pstate_type(power_state);
-	uint32_t i;
-
-	if (pstate == PSTATE_TYPE_STANDBY) {
-		if (pwr_lvl != MPIDR_AFFLVL0)
-			return PSCI_E_INVALID_PARAMS;
-
-		req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
-	} else {
-		for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++)
-			req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
-	}
-
-	if (psci_get_pstate_id(power_state))
-		return PSCI_E_INVALID_PARAMS;
-
-	return PSCI_E_SUCCESS;
-}
-
-#if RCAR_SYSTEM_SUSPEND
-static void rcar_get_sys_suspend_power_state(psci_power_state_t *req_state)
-{
-	unsigned long mpidr = read_mpidr_el1() & 0x0000ffffU;
-	int i;
-
-	if (mpidr != rcar_boot_mpidr)
-		goto deny;
-
-	for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
-		req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
-
-	return;
-deny:
-	/* deny system suspend entry */
-	req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSCI_LOCAL_STATE_RUN;
-	for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
-		req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE;
-}
-#endif
-
-static const plat_psci_ops_t rcar_plat_psci_ops = {
-	.cpu_standby			= rcar_cpu_standby,
-	.pwr_domain_on			= rcar_pwr_domain_on,
-	.pwr_domain_off			= rcar_pwr_domain_off,
-	.pwr_domain_suspend		= rcar_pwr_domain_suspend,
-	.pwr_domain_on_finish		= rcar_pwr_domain_on_finish,
-	.pwr_domain_suspend_finish	= rcar_pwr_domain_suspend_finish,
-	.system_off			= rcar_system_off,
-	.system_reset			= rcar_system_reset,
-	.validate_power_state		= rcar_validate_power_state,
-#if RCAR_SYSTEM_SUSPEND
-	.get_sys_suspend_power_state	= rcar_get_sys_suspend_power_state,
-#endif
-};
-
-int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops)
-{
-	*psci_ops = &rcar_plat_psci_ops;
-	rcar_sec_entrypoint = sec_entrypoint;
-
-#if RCAR_SYSTEM_SUSPEND
-	rcar_pwrc_init_suspend_to_ram();
-#endif
-	return 0;
-}
-
diff --git a/plat/renesas/rcar/plat_storage.c b/plat/renesas/rcar/plat_storage.c
deleted file mode 100644
index 6524561..0000000
--- a/plat/renesas/rcar/plat_storage.c
+++ /dev/null
@@ -1,417 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <string.h>
-
-#include <common/debug.h>
-#include <drivers/io/io_driver.h>
-#include <drivers/io/io_storage.h>
-#include <drivers/io/io_semihosting.h>
-
-#include "io_common.h"
-#include "io_memdrv.h"
-#include "io_emmcdrv.h"
-#include "io_private.h"
-#include "io_rcar.h"
-#include <platform_def.h>
-
-static uintptr_t emmcdrv_dev_handle;
-static uintptr_t memdrv_dev_handle;
-static uintptr_t rcar_dev_handle;
-
-static uintptr_t boot_io_drv_id;
-
-static const io_block_spec_t rcar_block_spec = {
-	.offset = FLASH0_BASE,
-	.length = FLASH0_SIZE
-};
-
-static const io_block_spec_t bl2_file_spec = {
-	.offset = BL2_IMAGE_ID,
-};
-
-static const io_block_spec_t bl31_file_spec = {
-	.offset = BL31_IMAGE_ID,
-};
-
-static const io_block_spec_t bl32_file_spec = {
-	.offset = BL32_IMAGE_ID,
-};
-
-static const io_block_spec_t bl33_file_spec = {
-	.offset = BL33_IMAGE_ID,
-};
-
-static const io_block_spec_t bl332_file_spec = {
-	.offset = BL332_IMAGE_ID,
-};
-
-static const io_block_spec_t bl333_file_spec = {
-	.offset = BL333_IMAGE_ID,
-};
-
-static const io_block_spec_t bl334_file_spec = {
-	.offset = BL334_IMAGE_ID,
-};
-
-static const io_block_spec_t bl335_file_spec = {
-	.offset = BL335_IMAGE_ID,
-};
-
-static const io_block_spec_t bl336_file_spec = {
-	.offset = BL336_IMAGE_ID,
-};
-
-static const io_block_spec_t bl337_file_spec = {
-	.offset = BL337_IMAGE_ID,
-};
-
-static const io_block_spec_t bl338_file_spec = {
-	.offset = BL338_IMAGE_ID,
-};
-
-#if TRUSTED_BOARD_BOOT
-static const io_block_spec_t trusted_key_cert_file_spec = {
-	.offset = TRUSTED_KEY_CERT_ID,
-};
-
-static const io_block_spec_t bl31_key_cert_file_spec = {
-	.offset = SOC_FW_KEY_CERT_ID,
-};
-
-static const io_block_spec_t bl32_key_cert_file_spec = {
-	.offset = TRUSTED_OS_FW_KEY_CERT_ID,
-};
-
-static const io_block_spec_t bl33_key_cert_file_spec = {
-	.offset = NON_TRUSTED_FW_KEY_CERT_ID,
-};
-
-static const io_block_spec_t bl332_key_cert_file_spec = {
-	.offset = BL332_KEY_CERT_ID,
-};
-
-static const io_block_spec_t bl333_key_cert_file_spec = {
-	.offset = BL333_KEY_CERT_ID,
-};
-
-static const io_block_spec_t bl334_key_cert_file_spec = {
-	.offset = BL334_KEY_CERT_ID,
-};
-
-static const io_block_spec_t bl335_key_cert_file_spec = {
-	.offset = BL335_KEY_CERT_ID,
-};
-
-static const io_block_spec_t bl336_key_cert_file_spec = {
-	.offset = BL336_KEY_CERT_ID,
-};
-
-static const io_block_spec_t bl337_key_cert_file_spec = {
-	.offset = BL337_KEY_CERT_ID,
-};
-
-static const io_block_spec_t bl338_key_cert_file_spec = {
-	.offset = BL338_KEY_CERT_ID,
-};
-
-static const io_block_spec_t bl31_cert_file_spec = {
-	.offset = SOC_FW_CONTENT_CERT_ID,
-};
-
-static const io_block_spec_t bl32_cert_file_spec = {
-	.offset = TRUSTED_OS_FW_CONTENT_CERT_ID,
-};
-
-static const io_block_spec_t bl33_cert_file_spec = {
-	.offset = NON_TRUSTED_FW_CONTENT_CERT_ID,
-};
-
-static const io_block_spec_t bl332_cert_file_spec = {
-	.offset = BL332_CERT_ID,
-};
-
-static const io_block_spec_t bl333_cert_file_spec = {
-	.offset = BL333_CERT_ID,
-};
-
-static const io_block_spec_t bl334_cert_file_spec = {
-	.offset = BL334_CERT_ID,
-};
-
-static const io_block_spec_t bl335_cert_file_spec = {
-	.offset = BL335_CERT_ID,
-};
-
-static const io_block_spec_t bl336_cert_file_spec = {
-	.offset = BL336_CERT_ID,
-};
-
-static const io_block_spec_t bl337_cert_file_spec = {
-	.offset = BL337_CERT_ID,
-};
-
-static const io_block_spec_t bl338_cert_file_spec = {
-	.offset = BL338_CERT_ID,
-};
-#endif
-
-static int32_t open_emmcdrv(const uintptr_t spec);
-static int32_t open_memmap(const uintptr_t spec);
-static int32_t open_rcar(const uintptr_t spec);
-
-struct plat_io_policy {
-	uintptr_t *dev_handle;
-	uintptr_t image_spec;
-	int32_t (*check)(const uintptr_t spec);
-};
-
-static const struct plat_io_policy policies[] = {
-	[FIP_IMAGE_ID] = {
-			  &memdrv_dev_handle,
-			  (uintptr_t) &rcar_block_spec,
-			  &open_memmap},
-	[BL2_IMAGE_ID] = {
-			  &rcar_dev_handle,
-			  (uintptr_t) &bl2_file_spec,
-			  &open_rcar},
-	[BL31_IMAGE_ID] = {
-			   &rcar_dev_handle,
-			   (uintptr_t) &bl31_file_spec,
-			   &open_rcar},
-	[BL32_IMAGE_ID] = {
-			   &rcar_dev_handle,
-			   (uintptr_t) &bl32_file_spec,
-			   &open_rcar},
-	[BL33_IMAGE_ID] = {
-			   &rcar_dev_handle,
-			   (uintptr_t) &bl33_file_spec,
-			   &open_rcar},
-	[BL332_IMAGE_ID] = {
-			    &rcar_dev_handle,
-			    (uintptr_t) &bl332_file_spec,
-			    &open_rcar},
-	[BL333_IMAGE_ID] = {
-			    &rcar_dev_handle,
-			    (uintptr_t) &bl333_file_spec,
-			    &open_rcar},
-	[BL334_IMAGE_ID] = {
-			    &rcar_dev_handle,
-			    (uintptr_t) &bl334_file_spec,
-			    &open_rcar},
-	[BL335_IMAGE_ID] = {
-			    &rcar_dev_handle,
-			    (uintptr_t) &bl335_file_spec,
-			    &open_rcar},
-	[BL336_IMAGE_ID] = {
-			    &rcar_dev_handle,
-			    (uintptr_t) &bl336_file_spec,
-			    &open_rcar},
-	[BL337_IMAGE_ID] = {
-			    &rcar_dev_handle,
-			    (uintptr_t) &bl337_file_spec,
-			    &open_rcar},
-	[BL338_IMAGE_ID] = {
-			    &rcar_dev_handle,
-			    (uintptr_t) &bl338_file_spec,
-			    &open_rcar},
-#if TRUSTED_BOARD_BOOT
-	[TRUSTED_KEY_CERT_ID] = {
-				 &rcar_dev_handle,
-				 (uintptr_t) &trusted_key_cert_file_spec,
-				 &open_rcar},
-	[SOC_FW_KEY_CERT_ID] = {
-				&rcar_dev_handle,
-				(uintptr_t) &bl31_key_cert_file_spec,
-				&open_rcar},
-	[TRUSTED_OS_FW_KEY_CERT_ID] = {
-				       &rcar_dev_handle,
-				       (uintptr_t) &bl32_key_cert_file_spec,
-				       &open_rcar},
-	[NON_TRUSTED_FW_KEY_CERT_ID] = {
-					&rcar_dev_handle,
-					(uintptr_t) &bl33_key_cert_file_spec,
-					&open_rcar},
-	[BL332_KEY_CERT_ID] = {
-			       &rcar_dev_handle,
-			       (uintptr_t) &bl332_key_cert_file_spec,
-			       &open_rcar},
-	[BL333_KEY_CERT_ID] = {
-			       &rcar_dev_handle,
-			       (uintptr_t) &bl333_key_cert_file_spec,
-			       &open_rcar},
-	[BL334_KEY_CERT_ID] = {
-			       &rcar_dev_handle,
-			       (uintptr_t) &bl334_key_cert_file_spec,
-			       &open_rcar},
-	[BL335_KEY_CERT_ID] = {
-			       &rcar_dev_handle,
-			       (uintptr_t) &bl335_key_cert_file_spec,
-			       &open_rcar},
-	[BL336_KEY_CERT_ID] = {
-			       &rcar_dev_handle,
-			       (uintptr_t) &bl336_key_cert_file_spec,
-			       &open_rcar},
-	[BL337_KEY_CERT_ID] = {
-			       &rcar_dev_handle,
-			       (uintptr_t) &bl337_key_cert_file_spec,
-			       &open_rcar},
-	[BL338_KEY_CERT_ID] = {
-			       &rcar_dev_handle,
-			       (uintptr_t) &bl338_key_cert_file_spec,
-			       &open_rcar},
-	[SOC_FW_CONTENT_CERT_ID] = {
-				    &rcar_dev_handle,
-				    (uintptr_t) &bl31_cert_file_spec,
-				    &open_rcar},
-	[TRUSTED_OS_FW_CONTENT_CERT_ID] = {
-					   &rcar_dev_handle,
-					   (uintptr_t) &bl32_cert_file_spec,
-					   &open_rcar},
-	[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
-					    &rcar_dev_handle,
-					    (uintptr_t) &bl33_cert_file_spec,
-					    &open_rcar},
-	[BL332_CERT_ID] = {
-			   &rcar_dev_handle,
-			   (uintptr_t) &bl332_cert_file_spec,
-			   &open_rcar},
-	[BL333_CERT_ID] = {
-			   &rcar_dev_handle,
-			   (uintptr_t) &bl333_cert_file_spec,
-			   &open_rcar},
-	[BL334_CERT_ID] = {
-			   &rcar_dev_handle,
-			   (uintptr_t) &bl334_cert_file_spec,
-			   &open_rcar},
-	[BL335_CERT_ID] = {
-			   &rcar_dev_handle,
-			   (uintptr_t) &bl335_cert_file_spec,
-			   &open_rcar},
-	[BL336_CERT_ID] = {
-			   &rcar_dev_handle,
-			   (uintptr_t) &bl336_cert_file_spec,
-			   &open_rcar},
-	[BL337_CERT_ID] = {
-			   &rcar_dev_handle,
-			   (uintptr_t) &bl337_cert_file_spec,
-			   &open_rcar},
-	[BL338_CERT_ID] = {
-			   &rcar_dev_handle,
-			   (uintptr_t) &bl338_cert_file_spec,
-			   &open_rcar}, {
-#else
-					{
-#endif
-					 0, 0, 0}
-};
-
-static io_drv_spec_t io_drv_spec_memdrv = {
-	FLASH0_BASE,
-	FLASH0_SIZE,
-	0,
-};
-
-static io_drv_spec_t io_drv_spec_emmcdrv = {
-	0,
-	0,
-	0,
-};
-
-static struct plat_io_policy drv_policies[] __attribute__ ((section(".data"))) = {
-	/* FLASH_DEV_ID */
-	{ &memdrv_dev_handle, (uintptr_t) &io_drv_spec_memdrv, &open_memmap, },
-	/* EMMC_DEV_ID */
-	{ &emmcdrv_dev_handle, (uintptr_t) &io_drv_spec_emmcdrv, &open_emmcdrv, }
-};
-
-static int32_t open_rcar(const uintptr_t spec)
-{
-	return io_dev_init(rcar_dev_handle, boot_io_drv_id);
-}
-
-static int32_t open_memmap(const uintptr_t spec)
-{
-	uintptr_t handle;
-	int32_t result;
-
-	result = io_dev_init(memdrv_dev_handle, 0);
-	if (result != IO_SUCCESS)
-		return result;
-
-	result = io_open(memdrv_dev_handle, spec, &handle);
-	if (result == IO_SUCCESS)
-		io_close(handle);
-
-	return result;
-}
-
-static int32_t open_emmcdrv(const uintptr_t spec)
-{
-	return io_dev_init(emmcdrv_dev_handle, 0);
-}
-
-void rcar_io_setup(void)
-{
-	const io_dev_connector_t *memmap;
-	const io_dev_connector_t *rcar;
-
-	boot_io_drv_id = FLASH_DEV_ID;
-
-	rcar_register_io_dev(&rcar);
-	rcar_register_io_dev_memdrv(&memmap);
-	io_dev_open(rcar, 0, &rcar_dev_handle);
-	io_dev_open(memmap, 0, &memdrv_dev_handle);
-}
-
-void rcar_io_emmc_setup(void)
-{
-	const io_dev_connector_t *rcar;
-	const io_dev_connector_t *emmc;
-
-	boot_io_drv_id = EMMC_DEV_ID;
-
-	rcar_register_io_dev(&rcar);
-	rcar_register_io_dev_emmcdrv(&emmc);
-	io_dev_open(rcar, 0, &rcar_dev_handle);
-	io_dev_open(emmc, 0, &emmcdrv_dev_handle);
-}
-
-int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
-			  uintptr_t *image_spec)
-{
-	const struct plat_io_policy *policy;
-	int result;
-
-	policy = &policies[image_id];
-
-	result = policy->check(policy->image_spec);
-	if (result != IO_SUCCESS)
-		return result;
-
-	*image_spec = policy->image_spec;
-	*dev_handle = *(policy->dev_handle);
-
-	return IO_SUCCESS;
-}
-
-int32_t plat_get_drv_source(uint32_t io_drv_id, uintptr_t *dev_handle,
-			    uintptr_t *image_spec)
-{
-	const struct plat_io_policy *policy;
-	int32_t result;
-
-	policy = &drv_policies[io_drv_id];
-
-	result = policy->check(policy->image_spec);
-	if (result != IO_SUCCESS)
-		return result;
-
-	*image_spec = policy->image_spec;
-	*dev_handle = *(policy->dev_handle);
-
-	return IO_SUCCESS;
-}
diff --git a/plat/renesas/rcar/plat_topology.c b/plat/renesas/rcar/plat_topology.c
deleted file mode 100644
index 0d5880d..0000000
--- a/plat/renesas/rcar/plat_topology.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <lib/psci/psci.h>
-
-static const unsigned char rcar_power_domain_tree_desc[] = {
-	1,
-	PLATFORM_CLUSTER_COUNT,
-	PLATFORM_CLUSTER0_CORE_COUNT,
-	PLATFORM_CLUSTER1_CORE_COUNT
-};
-
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
-	return rcar_power_domain_tree_desc;
-}
-
-int plat_core_pos_by_mpidr(u_register_t mpidr)
-{
-	unsigned int cluster_id, cpu_id;
-
-	mpidr &= MPIDR_AFFINITY_MASK;
-
-	if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
-		return -1;
-
-	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
-	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
-
-	if (cluster_id >= PLATFORM_CLUSTER_COUNT)
-		return -1;
-
-	if (cluster_id == 0 && cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT)
-		return -1;
-
-	if (cluster_id == 1 && cpu_id >= PLATFORM_CLUSTER1_CORE_COUNT)
-		return -1;
-
-	return (cpu_id + cluster_id * PLATFORM_CLUSTER0_CORE_COUNT);
-}
-
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index ee393f2..5e4978c 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -312,19 +312,9 @@
 			-Idrivers/renesas/common/pwrc		\
 			-Idrivers/renesas/common/io
 
-BL2_SOURCES	+=	plat/renesas/rcar/bl2_interrupt_error.c		\
-			plat/renesas/rcar/bl2_secure_setting.c		\
-			plat/renesas/rcar/bl2_plat_setup.c		\
-			plat/renesas/rcar/plat_storage.c		\
-			plat/renesas/rcar/bl2_plat_mem_params_desc.c	\
-			plat/renesas/rcar/plat_image_load.c		\
-			plat/renesas/rcar/bl2_cpg_init.c		\
+BL2_SOURCES	+=	plat/renesas/rcar/bl2_plat_setup.c	\
 			drivers/renesas/rcar/board/board.c
 
-BL31_SOURCES	+=	plat/renesas/rcar/plat_topology.c		\
-			plat/renesas/rcar/bl31_plat_setup.c		\
-			plat/renesas/rcar/plat_pm.c
-
 ifeq (${RCAR_GEN3_ULCB},1)
 BL31_SOURCES		+=	drivers/renesas/rcar/cpld/ulcb_cpld.c
 endif