feat(mt8188): add SPM feature support
Add SPM low power functions, such as system suspend.
Change-Id: I6d1ad847a81ba9c347ab6fb8a8cb8c69004b7add
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.c
new file mode 100644
index 0000000..257caa3
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lpm/mt_lpm_smc.h>
+#include <mt_spm.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+
+int spm_rc_condition_modifier(unsigned int id, unsigned int act,
+ const void *val,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct mt_spm_cond_tables * const tlb)
+{
+ unsigned int rc_id, cond_id, cond;
+ int res = 0;
+
+ spin_lock(&spm_lock);
+ rc_id = SPM_RC_UPDATE_COND_RC_ID_GET(id);
+ cond_id = SPM_RC_UPDATE_COND_ID_GET(id);
+
+ do {
+ if ((dest_rc_id != rc_id) || (val == NULL) || (tlb == NULL)) {
+ res = -1;
+ break;
+ }
+
+ cond = *((unsigned int *)val);
+
+ if (cond_id < PLAT_SPM_COND_MAX) {
+ if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+ SPM_RC_BITS_SET(tlb->table_cg[cond_id], cond);
+ } else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(tlb->table_cg[cond_id], cond);
+ } else {
+ res = -1;
+ }
+ } else if ((cond_id - PLAT_SPM_COND_MAX) < PLAT_SPM_COND_PLL_MAX) {
+ unsigned int pll_idx = cond_id - PLAT_SPM_COND_MAX;
+
+ cond = !!cond;
+ if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+ SPM_RC_BITS_SET(tlb->table_pll, (cond << pll_idx));
+ } else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(tlb->table_pll, (cond << pll_idx));
+ } else {
+ res = -1;
+ }
+ } else {
+ res = -1;
+ }
+ } while (0);
+
+ spin_unlock(&spm_lock);
+
+ return res;
+}
+
+int spm_rc_constraint_status_get(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL) ||
+ (src == NULL)) {
+ return -1;
+ }
+ spin_lock(&spm_lock);
+
+ switch (type) {
+ case CONSTRAINT_GET_ENTER_CNT:
+ if (id == MT_RM_CONSTRAINT_ID_ALL) {
+ dest->enter_cnt += src->enter_cnt;
+ } else {
+ dest->enter_cnt = src->enter_cnt;
+ }
+ break;
+ case CONSTRAINT_GET_VALID:
+ dest->is_valid = src->is_valid;
+ break;
+ case CONSTRAINT_COND_BLOCK:
+ dest->is_cond_block = src->is_cond_block;
+ dest->all_pll_dump = src->all_pll_dump;
+ break;
+ case CONSTRAINT_GET_COND_BLOCK_DETAIL:
+ dest->cond_res = src->cond_res;
+ break;
+ case CONSTRAINT_GET_RESIDNECY:
+ dest->residency = src->residency;
+ if (act & MT_LPM_SMC_ACT_CLR) {
+ src->residency = 0;
+ }
+ break;
+ default:
+ break;
+ }
+
+ spin_unlock(&spm_lock);
+ return 0;
+}
+
+int spm_rc_constraint_status_set(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+ return -1;
+ }
+
+ spin_lock(&spm_lock);
+
+ switch (type) {
+ case CONSTRAINT_UPDATE_VALID:
+ if (src != NULL) {
+ if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
+ SPM_RC_BITS_SET(dest->is_valid, src->is_valid);
+ } else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(dest->is_valid, src->is_valid);
+ }
+ }
+ break;
+ case CONSTRAINT_RESIDNECY:
+ if (act & MT_LPM_SMC_ACT_CLR) {
+ dest->residency = 0;
+ }
+ break;
+ default:
+ break;
+ }
+
+ spin_unlock(&spm_lock);
+
+ return 0;
+}
+
+int spm_rc_constraint_valid_set(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+ return -1;
+ }
+
+ spin_lock(&spm_lock);
+ SPM_RC_BITS_SET(dest->is_valid, valid);
+ spin_unlock(&spm_lock);
+
+ return 0;
+}
+
+int spm_rc_constraint_valid_clr(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest)
+{
+ if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
+ return -1;
+ }
+
+ spin_lock(&spm_lock);
+ SPM_RC_BITS_CLR(dest->is_valid, valid);
+ spin_unlock(&spm_lock);
+
+ return 0;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.h b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.h
new file mode 100644
index 0000000..0736ca3
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_API_H
+#define MT_SPM_RC_API_H
+
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_internal.h>
+
+#define SPM_RC_BITS_SET(dest, src) ({ (dest) |= (src); })
+#define SPM_RC_BITS_CLR(dest, src) ({ (dest) &= (~src); })
+
+int spm_rc_condition_modifier(unsigned int id, unsigned int act,
+ const void *val,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct mt_spm_cond_tables * const tlb);
+
+int spm_rc_constraint_status_get(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest);
+
+int spm_rc_constraint_status_set(unsigned int id, unsigned int type,
+ unsigned int act,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ struct constraint_status * const src,
+ struct constraint_status * const dest);
+
+int spm_rc_constraint_valid_set(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest);
+
+int spm_rc_constraint_valid_clr(enum mt_spm_rm_rc_type id,
+ enum mt_spm_rm_rc_type dest_rc_id,
+ unsigned int valid,
+ struct constraint_status * const dest);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
new file mode 100644
index 0000000..0b792ab
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#ifndef MTK_PLAT_CIRQ_UNSUPPORT
+#include <mtk_cirq.h>
+#endif
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_BUS26M_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
+ MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
+ MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG1 (SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
+
+/* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
+#if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
+#define CONSTRAINT_BUS26M_RESOURCE_REQ (MT_SPM_26M)
+#else
+#define CONSTRAINT_BUS26M_RESOURCE_REQ (0)
+#endif
+
+static unsigned int bus26m_ext_opand;
+static unsigned int bus26m_ext_opand2;
+
+static struct mt_irqremain *refer2remain_irq;
+
+static struct mt_spm_cond_tables cond_bus26m = {
+ .table_cg = {
+ 0xFF5DD002, /* MTCMOS1 */
+ 0x0000003C, /* MTCMOS2 */
+ 0x27AF8000, /* INFRA0 */
+ 0x22010876, /* INFRA1 */
+ 0x86000650, /* INFRA2 */
+ 0x30008020, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x01002A3B, /* PERI0 */
+ 0x00090000, /* VPPSYS0_0 */
+ 0x38FF3E69, /* VPPSYS0_1 */
+ 0xF0081450, /* VPPSYS1_0 */
+ 0x00003000, /* VPPSYS1_1 */
+ 0x00000000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x000001FF, /* VDOSYS1_0 */
+ 0x000001E0, /* VDOSYS1_1 */
+ 0x00FB0007, /* VDOSYS1_2 */
+ },
+ .table_pll = (PLL_BIT_UNIVPLL |
+ PLL_BIT_MFGPLL |
+ PLL_BIT_MSDCPLL |
+ PLL_BIT_TVDPLL1 |
+ PLL_BIT_TVDPLL2 |
+ PLL_BIT_MMPLL |
+ PLL_BIT_ETHPLL |
+ PLL_BIT_IMGPLL |
+ PLL_BIT_APLL1 |
+ PLL_BIT_APLL2 |
+ PLL_BIT_APLL3 |
+ PLL_BIT_APLL4 |
+ PLL_BIT_APLL5),
+};
+
+static struct mt_spm_cond_tables cond_bus26m_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_BUS26M,
+ .is_valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_CHECK |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_TRACE_TIME),
+ .is_cond_block = 0U,
+ .enter_cnt = 0U,
+ .all_pll_dump = 0U,
+ .cond_res = &cond_bus26m_res,
+ .residency = 0ULL,
+};
+
+#ifdef MTK_PLAT_CIRQ_UNSUPPORT
+#define do_irqs_delivery()
+#else
+static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
+ unsigned int irq_index,
+ struct wake_status *wakeup)
+{
+ if ((irqs == NULL) || (wakeup == NULL)) {
+ return;
+ }
+
+ INFO("[SPM] r12=0x%08x(0x%08x), flag=0x%08x 0x%08x 0x%08x, irq:%u(0x%08x) set pending\n",
+ wakeup->tr.comm.r12,
+ wakeup->md32pcm_wakeup_sta,
+ wakeup->tr.comm.debug_flag,
+ wakeup->tr.comm.b_sw_flag0,
+ wakeup->tr.comm.b_sw_flag1,
+ irqs->wakeupsrc[irq_index],
+ irqs->irqs[irq_index]);
+}
+
+static void do_irqs_delivery(void)
+{
+ unsigned int idx;
+ struct wake_status *wakeup = NULL;
+ struct mt_irqremain *irqs = refer2remain_irq;
+
+ if (irqs == NULL) {
+ return;
+ }
+
+ if (spm_conservation_get_result(&wakeup) == 0) {
+ if (wakeup != NULL) {
+ for (idx = 0; idx < irqs->count; idx++) {
+ if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
+ ((wakeup->tr.comm.raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
+ if ((irqs->wakeupsrc_cat[idx] &
+ MT_IRQ_REMAIN_CAT_LOG) != 0U) {
+ mt_spm_irq_remain_dump(irqs, idx, wakeup);
+ }
+ mt_irq_set_pending(irqs->irqs[idx]);
+ }
+ }
+ }
+ }
+}
+#endif
+
+int spm_bus26m_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_BUS26M_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
+{
+ return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
+ IS_MT_RM_RC_READY(status.is_valid) &&
+ (IS_PLAT_SUSPEND_ID(state_id) || (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+ const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
+ const struct mt_spm_cond_tables *tlb_check =
+ (const struct mt_spm_cond_tables *)&cond_bus26m;
+
+ if (tlb == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_bus26m_res : NULL);
+ status.all_pll_dump = mt_spm_dump_all_pll(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_bus26m_res : NULL);
+ return MT_RM_STATUS_OK;
+}
+
+static void update_rc_remain_irqs(const void *val)
+{
+ refer2remain_irq = (struct mt_irqremain *)val;
+}
+
+static void update_rc_fmaudio_adsp(int type, const void *val)
+{
+ int *flag = (int *)val;
+ unsigned int ext_op = (type == PLAT_RC_IS_ADSP) ?
+ (MT_SPM_EX_OP_SET_IS_ADSP | MT_SPM_EX_OP_SET_SUSPEND_MODE) :
+ MT_SPM_EX_OP_SET_SUSPEND_MODE;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(bus26m_ext_opand, ext_op);
+ } else {
+ SPM_RC_BITS_CLR(bus26m_ext_opand, ext_op);
+ }
+}
+
+static void update_rc_usb_peri(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(bus26m_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ } else {
+ SPM_RC_BITS_CLR(bus26m_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ }
+}
+
+static void update_rc_usb_infra(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(bus26m_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ } else {
+ SPM_RC_BITS_CLR(bus26m_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ }
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st;
+
+ st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+ struct mt_spm_cond_tables * const tlb = &cond_bus26m;
+
+ spm_rc_condition_modifier(st->id, st->act, st->value,
+ MT_RM_CONSTRAINT_ID_BUS26M, tlb);
+ } else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+ (st->type == CONSTRAINT_RESIDNECY)) {
+ spm_rc_constraint_status_set(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_BUS26M,
+ (struct constraint_status * const)st->value,
+ (struct constraint_status * const)&status);
+ } else {
+ INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+ }
+}
+
+int spm_update_rc_bus26m(int state_id, int type, const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ switch (type) {
+ case PLAT_RC_UPDATE_CONDITION:
+ res = update_rc_condition(val);
+ break;
+ case PLAT_RC_UPDATE_REMAIN_IRQS:
+ update_rc_remain_irqs(val);
+ break;
+ case PLAT_RC_IS_FMAUDIO:
+ case PLAT_RC_IS_ADSP:
+ update_rc_fmaudio_adsp(type, val);
+ break;
+ case PLAT_RC_IS_USB_PERI:
+ update_rc_usb_peri(val);
+ break;
+ case PLAT_RC_IS_USB_INFRA:
+ update_rc_usb_infra(val);
+ break;
+ case PLAT_RC_STATUS:
+ update_rc_status(val);
+ break;
+ default:
+ INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+ break;
+ }
+ return res;
+}
+
+unsigned int spm_allow_rc_bus26m(int state_id)
+{
+ return CONSTRAINT_BUS26M_ALLOW;
+}
+
+int spm_run_rc_bus26m(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
+#endif
+ if (status.is_valid & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT |
+ bus26m_ext_opand |
+ bus26m_ext_opand2),
+ CONSTRAINT_BUS26M_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_bus26m_conduct);
+ }
+ return MT_RM_STATUS_OK;
+}
+
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0);
+#endif
+ if (status.is_valid & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (bus26m_ext_opand | bus26m_ext_opand2 |
+ MT_SPM_EX_OP_SET_WDT | ext_op),
+ NULL);
+ bus26m_ext_opand = 0;
+ } else {
+ struct wake_status *waken = NULL;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+ ext_op |= MT_SPM_EX_OP_TRACE_LP;
+ }
+
+ mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+ status.enter_cnt++;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+ status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+ }
+ }
+
+ do_irqs_delivery();
+
+ return MT_RM_STATUS_OK;
+}
+
+int spm_get_status_rc_bus26m(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type == PLAT_RC_STATUS) {
+ int res = 0;
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ res = spm_rc_constraint_status_get(st->id, st->type,
+ st->act, MT_RM_CONSTRAINT_ID_BUS26M,
+ (struct constraint_status * const)&status,
+ (struct constraint_status * const)st->value);
+ if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ }
+ return ret;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c
new file mode 100644
index 0000000..1bcd509
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lpm_smc.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG1 (0)
+
+#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ (MT_SPM_DRAM_S1 | \
+ MT_SPM_DRAM_S0 | \
+ MT_SPM_SYSPLL | \
+ MT_SPM_INFRA | \
+ MT_SPM_26M | \
+ MT_SPM_XO_FPM)
+
+static unsigned int cpubuckldo_status = (MT_SPM_RC_VALID_SW | MT_SPM_RC_VALID_TRACE_TIME);
+static unsigned int cpubuckldo_enter_cnt;
+
+int spm_cpu_bcuk_ldo_conduct(int state_id,
+ struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ return IS_MT_RM_RC_READY(cpubuckldo_status);
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if ((st->type == CONSTRAINT_UPDATE_VALID) && st->value) {
+ if ((st->id == MT_RM_CONSTRAINT_ID_ALL) ||
+ (st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) {
+ struct constraint_status *con = (struct constraint_status *)st->value;
+
+ if ((st->act & MT_LPM_SMC_ACT_CLR) > 0U) {
+ SPM_RC_BITS_CLR(cpubuckldo_status, con->is_valid);
+ } else {
+ SPM_RC_BITS_SET(cpubuckldo_status, con->is_valid);
+ }
+ }
+ }
+}
+
+int spm_update_rc_cpu_buck_ldo(int state_id, int type, const void *val)
+{
+ if (type == PLAT_RC_STATUS) {
+ update_rc_status(val);
+ }
+ return MT_RM_STATUS_OK;
+}
+
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
+{
+ return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
+}
+
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ unsigned int ext_op = 0U;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : (0U)));
+#endif
+ if (cpubuckldo_status & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_SET_WDT),
+ CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_cpu_bcuk_ldo_conduct);
+ }
+
+ cpubuckldo_enter_cnt++;
+
+ return 0;
+}
+
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ unsigned int ext_op = 0U;
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+ if (cpubuckldo_status & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
+ } else {
+ mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+ }
+
+ return 0;
+}
+
+int spm_get_status_rc_cpu_buck_ldo(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type != PLAT_RC_STATUS) {
+ return ret;
+ }
+
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ if ((st->id == MT_RM_CONSTRAINT_ID_ALL) ||
+ (st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) {
+ struct constraint_status *dest;
+
+ dest = (struct constraint_status *)st->value;
+ do {
+ if (dest == NULL) {
+ break;
+ }
+ if (st->type == CONSTRAINT_GET_VALID) {
+ dest->is_valid = cpubuckldo_status;
+ } else if (st->type == CONSTRAINT_COND_BLOCK) {
+ dest->is_cond_block = 0;
+ } else if (st->type == CONSTRAINT_GET_ENTER_CNT) {
+ if (st->id == MT_RM_CONSTRAINT_ID_ALL) {
+ dest->enter_cnt += cpubuckldo_enter_cnt;
+ } else {
+ dest->enter_cnt = cpubuckldo_enter_cnt;
+ }
+ } else {
+ break;
+ }
+ if (st->id != MT_RM_CONSTRAINT_ID_ALL) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ } while (0);
+ }
+ return ret;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
new file mode 100644
index 0000000..d1a2435
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_DRAM_ALLOW (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
+
+#define CONSTRAINT_DRAM_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_DRAM_PCM_FLAG1 (0)
+
+#define CONSTRAINT_DRAM_RESOURCE_REQ (MT_SPM_SYSPLL | MT_SPM_INFRA | MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_dram = {
+ .table_cg = {
+ 0xFF5DD002, /* MTCMOS1 */
+ 0x0000003C, /* MTCMOS2 */
+ 0x27AF8000, /* INFRA0 */
+ 0x20010876, /* INFRA1 */
+ 0x86000640, /* INFRA2 */
+ 0x00000000, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x01002A00, /* PERI0 */
+ 0x00080000, /* VPPSYS0_0 */
+ 0x38803000, /* VPPSYS0_1 */
+ 0x00081450, /* VPPSYS1_0 */
+ 0x00003000, /* VPPSYS1_1 */
+ 0x00000000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x000001F8, /* VDOSYS1_0 */
+ 0x000001E0, /* VDOSYS1_1 */
+ 0x00FB0007, /* VDOSYS1_2 */
+ },
+ .table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_dram_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_DRAM,
+ .is_valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_CHECK |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_XSOC_BBLPM |
+ MT_SPM_RC_VALID_TRACE_TIME),
+ .is_cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_dram_res,
+ .residency = 0ULL,
+};
+
+static unsigned short ext_status_dram;
+
+int spm_dram_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_DRAM_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
+{
+ return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK)) &&
+ IS_MT_RM_RC_READY(status.is_valid) &&
+ (IS_PLAT_SUSPEND_ID(state_id) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_MEM) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+ const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
+ const struct mt_spm_cond_tables *tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
+
+ if (tlb == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_dram_res : NULL);
+ return MT_RM_STATUS_OK;
+}
+
+static void update_rc_clkbuf_status(const void *val)
+{
+ unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
+
+ if (is_flight != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_ufs_status(const void *val)
+{
+ unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
+
+ if (is_ufs_h8 != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st;
+
+ st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+ struct mt_spm_cond_tables * const tlb = &cond_dram;
+
+ spm_rc_condition_modifier(st->id, st->act, st->value,
+ MT_RM_CONSTRAINT_ID_DRAM, tlb);
+ } else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+ (st->type == CONSTRAINT_RESIDNECY)) {
+ spm_rc_constraint_status_set(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ (struct constraint_status * const)st->value,
+ (struct constraint_status * const)&status);
+ } else {
+ INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+ }
+}
+
+int spm_update_rc_dram(int state_id, int type, const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ switch (type) {
+ case PLAT_RC_UPDATE_CONDITION:
+ res = update_rc_condition(val);
+ break;
+ case PLAT_RC_CLKBUF_STATUS:
+ update_rc_clkbuf_status(val);
+ break;
+ case PLAT_RC_UFS_STATUS:
+ update_rc_ufs_status(val);
+ break;
+ case PLAT_RC_STATUS:
+ update_rc_status(val);
+ break;
+ default:
+ INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+ break;
+ }
+
+ return res;
+}
+
+unsigned int spm_allow_rc_dram(int state_id)
+{
+ return CONSTRAINT_DRAM_ALLOW;
+}
+
+int spm_run_rc_dram(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+ ext_status_dram = status.is_valid;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+ (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#else
+ (void)allows;
+#endif
+
+ if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_HW_S1_DETECT),
+ CONSTRAINT_DRAM_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_dram(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+ (void)allows;
+#endif
+
+ if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+ NULL);
+ } else {
+ struct wake_status *waken = NULL;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+ ext_op |= MT_SPM_EX_OP_TRACE_LP;
+ }
+ mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+ status.enter_cnt++;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+ status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+ }
+ }
+
+ return 0;
+}
+
+int spm_get_status_rc_dram(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type == PLAT_RC_STATUS) {
+ int res = 0;
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ res = spm_rc_constraint_status_get(st->id, st->type,
+ st->act, MT_RM_CONSTRAINT_ID_DRAM,
+ (struct constraint_status * const)&status,
+ (struct constraint_status * const)st->value);
+ if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ }
+ return ret;
+}
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_internal.h b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_internal.h
new file mode 100644
index 0000000..7763152
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_internal.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_INTERNAL_H
+#define MT_SPM_RC_INTERNAL_H
+
+#ifdef MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT
+#define SPM_FLAG_SRAM_SLEEP_CTRL (SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+#define SPM_SRAM_SLEEP_RC_RES_RESTRICT (0)
+#else
+#define SPM_FLAG_SRAM_SLEEP_CTRL (0)
+#define SPM_SRAM_SLEEP_RC_RES_RESTRICT (0)
+#endif
+
+#define SPM_RC_UPDATE_COND_ID_MASK (0xffff)
+#define SPM_RC_UPDATE_COND_RC_ID_MASK (0xffff)
+#define SPM_RC_UPDATE_COND_RC_ID_SHIFT (16)
+
+#define SPM_RC_UPDATE_COND_RC_ID_GET(val) \
+ ((val >> SPM_RC_UPDATE_COND_RC_ID_SHIFT) & SPM_RC_UPDATE_COND_RC_ID_MASK)
+
+#define SPM_RC_UPDATE_COND_ID_GET(val) (val & SPM_RC_UPDATE_COND_ID_MASK)
+
+/* cpu buck/ldo constraint function */
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_update_rc_cpu_buck_ldo(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_get_status_rc_cpu_buck_ldo(unsigned int type, void *priv);
+
+/* spm resource dram constraint function */
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
+int spm_update_rc_dram(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_dram(int state_id);
+int spm_run_rc_dram(unsigned int cpu, int state_id);
+int spm_reset_rc_dram(unsigned int cpu, int state_id);
+int spm_get_status_rc_dram(unsigned int type, void *priv);
+
+/* spm resource syspll constraint function */
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
+int spm_update_rc_syspll(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_syspll(int state_id);
+int spm_run_rc_syspll(unsigned int cpu, int state_id);
+int spm_reset_rc_syspll(unsigned int cpu, int state_id);
+int spm_get_status_rc_syspll(unsigned int type, void *priv);
+
+/* spm resource bus26m constraint function */
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
+int spm_update_rc_bus26m(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_bus26m(int state_id);
+int spm_run_rc_bus26m(unsigned int cpu, int state_id);
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
+int spm_get_status_rc_bus26m(unsigned int type, void *priv);
+
+#endif
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
new file mode 100644
index 0000000..700f500
--- /dev/null
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/spm/mt_spm_resource_req.h>
+#include <lib/pm/mtk_pm.h>
+#include <lpm/mt_lp_api.h>
+#include <lpm/mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include "mt_spm_rc_api.h"
+#include "mt_spm_rc_internal.h"
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+
+#define CONSTRAINT_SYSPLL_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_ENABLE_6315_CTRL | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_USE_SRCCLKENO2)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG1 (0)
+
+/* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
+#if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
+#else
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
+#endif
+
+static unsigned int syspll_ext_opand2;
+static unsigned short ext_status_syspll;
+
+static struct mt_spm_cond_tables cond_syspll = {
+ .table_cg = {
+ 0xFF5DD002, /* MTCMOS1 */
+ 0x0000003C, /* MTCMOS2 */
+ 0x27AF8000, /* INFRA0 */
+ 0x20010876, /* INFRA1 */
+ 0x86000640, /* INFRA2 */
+ 0x30008020, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x01002A0B, /* PERI0 */
+ 0x00090000, /* VPPSYS0_0 */
+ 0x38FF3E69, /* VPPSYS0_1 */
+ 0xF0081450, /* VPPSYS1_0 */
+ 0x00003000, /* VPPSYS1_1 */
+ 0x00000000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x000001FF, /* VDOSYS1_0 */
+ 0x008001E0, /* VDOSYS1_1 */
+ 0x00FB0007, /* VDOSYS1_2 */
+ },
+ .table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_syspll_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_SYSPLL,
+ .is_valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_CHECK |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_XSOC_BBLPM |
+ MT_SPM_RC_VALID_TRACE_TIME),
+ .is_cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_syspll_res,
+ .residency = 0ULL,
+};
+
+int spm_syspll_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+ unsigned int res_req = CONSTRAINT_SYSPLL_RESOURCE_REQ;
+
+ if ((spm_lp == NULL) || (resource_req == NULL)) {
+ return -1;
+ }
+
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
+
+ *resource_req |= res_req;
+ return 0;
+}
+
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
+{
+ return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
+ IS_MT_RM_RC_READY(status.is_valid) &&
+ (IS_PLAT_SUSPEND_ID(state_id) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
+ (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
+}
+
+static int update_rc_condition(const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ const struct mt_spm_cond_tables * const tlb =
+ (const struct mt_spm_cond_tables * const)val;
+ const struct mt_spm_cond_tables *tlb_check =
+ (const struct mt_spm_cond_tables *)&cond_syspll;
+
+ if (tlb == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
+ &cond_syspll_res : NULL);
+ return res;
+}
+
+static void update_rc_clkbuf_status(const void *val)
+{
+ unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
+
+ if (is_flight != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_FLIGHTMODE,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_ufs_status(const void *val)
+{
+ unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
+
+ if (is_ufs_h8 != 0U) {
+ spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ } else {
+ spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_SPM_RC_VALID_UFS_H8,
+ (struct constraint_status * const)&status);
+ }
+}
+
+static void update_rc_usb_peri(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ } else {
+ SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
+ }
+}
+
+static void update_rc_usb_infra(const void *val)
+{
+ int *flag = (int *)val;
+
+ if (flag == NULL) {
+ return;
+ }
+
+ if (*flag != 0) {
+ SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ } else {
+ SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
+ }
+}
+
+static void update_rc_status(const void *val)
+{
+ const struct rc_common_state *st;
+
+ st = (const struct rc_common_state *)val;
+
+ if (st == NULL) {
+ return;
+ }
+
+ if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
+ struct mt_spm_cond_tables * const tlb = &cond_syspll;
+
+ spm_rc_condition_modifier(st->id, st->act, st->value,
+ MT_RM_CONSTRAINT_ID_SYSPLL, tlb);
+ } else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
+ (st->type == CONSTRAINT_RESIDNECY)) {
+ spm_rc_constraint_status_set(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ (struct constraint_status * const)st->value,
+ (struct constraint_status * const)&status);
+ } else {
+ INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
+ }
+}
+
+int spm_update_rc_syspll(int state_id, int type, const void *val)
+{
+ int res = MT_RM_STATUS_OK;
+
+ switch (type) {
+ case PLAT_RC_UPDATE_CONDITION:
+ res = update_rc_condition(val);
+ break;
+ case PLAT_RC_CLKBUF_STATUS:
+ update_rc_clkbuf_status(val);
+ break;
+ case PLAT_RC_UFS_STATUS:
+ update_rc_ufs_status(val);
+ break;
+ case PLAT_RC_IS_USB_PERI:
+ update_rc_usb_peri(val);
+ break;
+ case PLAT_RC_IS_USB_INFRA:
+ update_rc_usb_infra(val);
+ break;
+ case PLAT_RC_STATUS:
+ update_rc_status(val);
+ break;
+ default:
+ INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
+ break;
+ }
+ return res;
+}
+
+unsigned int spm_allow_rc_syspll(int state_id)
+{
+ return CONSTRAINT_SYSPLL_ALLOW;
+}
+
+int spm_run_rc_syspll(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+ ext_status_syspll = status.is_valid;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
+#else
+ (void)allows;
+#endif
+ if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (syspll_ext_opand2 | MT_SPM_EX_OP_CLR_26M_RECORD |
+ MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE),
+ CONSTRAINT_SYSPLL_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_syspll(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+ (void)allows;
+#endif
+ if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
+ ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
+ }
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (syspll_ext_opand2 | MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+ NULL);
+ } else {
+ struct wake_status *waken = NULL;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
+ ext_op |= MT_SPM_EX_OP_TRACE_LP;
+ }
+
+ mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
+ status.enter_cnt++;
+
+ if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
+ status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
+ }
+ }
+
+ return 0;
+}
+
+int spm_get_status_rc_syspll(unsigned int type, void *priv)
+{
+ int ret = MT_RM_STATUS_OK;
+
+ if (type == PLAT_RC_STATUS) {
+ int res = 0;
+ struct rc_common_state *st = (struct rc_common_state *)priv;
+
+ if (st == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ res = spm_rc_constraint_status_get(st->id, st->type, st->act,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ (struct constraint_status * const)&status,
+ (struct constraint_status * const)st->value);
+ if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
+ ret = MT_RM_STATUS_STOP;
+ }
+ }
+ return ret;
+}