tree e9b9258472bc3d0f87862d062b0ed468eb3c1f09
parent e9c4a64da573c9281740a49997fdaf3318aeb466
author Vikram Kanigiri <vikram.kanigiri@arm.com> 1441890756 +0100
committer Achin Gupta <achin.gupta@arm.com> 1442264980 +0100

Tegra: Perform cache maintenance on video carveout memory

Currently, the non-overlapping video memory carveout region is cleared after
disabling the MMU at EL3. If at any exception level the carveout region is being
marked as cacheable, this zeroing of memory will not have an affect on the
cached lines. Hence, we first invalidate the dirty lines and update the memory
and invalidate again so that both caches and memory is zeroed out.

Change-Id: If3b2d139ab7227f6799c0911d59e079849dc86aa