Merge "qemu/qemu_sbsa: increase SHARED_RAM_SIZE" into integration
diff --git a/.editorconfig b/.editorconfig
index f523ca1..12f786d 100644
--- a/.editorconfig
+++ b/.editorconfig
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -38,10 +38,10 @@
insert_final_newline = true
# [LCS] Chapter 2: Breaking long lines and strings
-# "The limit on the length of lines is 80 columns"
+# "The limit on the length of lines is 100 columns"
# This is a "soft" requirement for Arm-TF, and should not be the sole
# reason for changes.
-max_line_length = 80
+max_line_length = 100
# [LCS] Chapter 1: Indentation
# "Tabs are 8 characters"
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index ab2d3f9..f500938 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -529,8 +529,10 @@
Xilinx platform port
^^^^^^^^^^^^^^^^^^^^
-:M: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
-:G: `sivadur`_
+:M: Michal Simek <michal.simek@xilinx.com>
+:G: `michalsimek`_
+:M: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
+:G: `venkatesh`_
:F: docs/plat/xilinx-zynqmp.rst
:F: plat/xilinx/
@@ -614,6 +616,7 @@
.. _ldts: https://github.com/ldts
.. _marex: https://github.com/marex
.. _masahir0y: https://github.com/masahir0y
+.. _michalsimek: https://github.com/michalsimek
.. _mmind: https://github.com/mmind
.. _mtk09422: https://github.com/mtk09422
.. _niej: https://github.com/niej
@@ -624,13 +627,13 @@
.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm
.. _sgorecha: https://github.com/sgorecha
.. _shawnguo2: https://github.com/shawnguo2
-.. _sivadur: https://github.com/sivadur
.. _smaeul: https://github.com/smaeul
.. _soby-mathew: https://github.com/soby-mathew
.. _thloh85-intel: https://github.com/thloh85-intel
.. _thomas-arm: https://github.com/thomas-arm
.. _TonyXie06: https://github.com/TonyXie06
.. _vwadekar: https://github.com/vwadekar
+.. _venkatesh: https://github.com/vabbarap
.. _Yann-lms: https://github.com/Yann-lms
.. _manish-pandey-arm: https://github.com/manish-pandey-arm
.. _mardyk01: https://github.com/mardyk01
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index c0fda78..e901e0c 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -363,10 +363,11 @@
Cortex-A57 based platform must make its own decision on whether to use
the optimization. This flag is disabled by default.
-- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
+- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last
level cache(LLC) is present in the system, and that the DataSource field
on the master CHI interface indicates when data is returned from the LLC.
This is used to control how the LL_CACHE* PMU events count.
+ Default value is 0 (Disabled).
--------------
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 33e1134..6dcdacf 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -243,6 +243,13 @@
#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
+#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
+#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
+#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
+#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
+#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
+#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
+
/* ID_AA64MMFR2_EL1 definitions */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
@@ -266,9 +273,17 @@
#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
-#define MTE_UNIMPLEMENTED ULL(0)
-#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */
-#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */
+/* Memory Tagging Extension is not implemented */
+#define MTE_UNIMPLEMENTED U(0)
+/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
+#define MTE_IMPLEMENTED_EL0 U(1)
+/* FEAT_MTE2: Full MTE is implemented */
+#define MTE_IMPLEMENTED_ELX U(2)
+/*
+ * FEAT_MTE3: MTE is implemented with support for
+ * asymmetric Tag Check Fault handling
+ */
+#define MTE_IMPLEMENTED_ASY U(3)
#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
@@ -286,6 +301,7 @@
#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
(UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
+
#define SCTLR_AARCH32_EL1_RES1 \
((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
(U(1) << 4) | (U(1) << 3))
@@ -300,9 +316,12 @@
#define SCTLR_SA_BIT (ULL(1) << 3)
#define SCTLR_SA0_BIT (ULL(1) << 4)
#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
+#define SCTLR_nAA_BIT (ULL(1) << 6)
#define SCTLR_ITD_BIT (ULL(1) << 7)
#define SCTLR_SED_BIT (ULL(1) << 8)
#define SCTLR_UMA_BIT (ULL(1) << 9)
+#define SCTLR_EnRCTX_BIT (ULL(1) << 10)
+#define SCTLR_EOS_BIT (ULL(1) << 11)
#define SCTLR_I_BIT (ULL(1) << 12)
#define SCTLR_EnDB_BIT (ULL(1) << 13)
#define SCTLR_DZE_BIT (ULL(1) << 14)
@@ -310,21 +329,65 @@
#define SCTLR_NTWI_BIT (ULL(1) << 16)
#define SCTLR_NTWE_BIT (ULL(1) << 18)
#define SCTLR_WXN_BIT (ULL(1) << 19)
-#define SCTLR_UWXN_BIT (ULL(1) << 20)
+#define SCTLR_TSCXT_BIT (ULL(1) << 20)
#define SCTLR_IESB_BIT (ULL(1) << 21)
+#define SCTLR_EIS_BIT (ULL(1) << 22)
+#define SCTLR_SPAN_BIT (ULL(1) << 23)
#define SCTLR_E0E_BIT (ULL(1) << 24)
#define SCTLR_EE_BIT (ULL(1) << 25)
#define SCTLR_UCI_BIT (ULL(1) << 26)
#define SCTLR_EnDA_BIT (ULL(1) << 27)
+#define SCTLR_nTLSMD_BIT (ULL(1) << 28)
+#define SCTLR_LSMAOE_BIT (ULL(1) << 29)
#define SCTLR_EnIB_BIT (ULL(1) << 30)
#define SCTLR_EnIA_BIT (ULL(1) << 31)
#define SCTLR_BT0_BIT (ULL(1) << 35)
#define SCTLR_BT1_BIT (ULL(1) << 36)
#define SCTLR_BT_BIT (ULL(1) << 36)
+#define SCTLR_ITFSB_BIT (ULL(1) << 37)
+#define SCTLR_TCF0_SHIFT U(38)
+#define SCTLR_TCF0_MASK ULL(3)
+
+/* Tag Check Faults in EL0 have no effect on the PE */
+#define SCTLR_TCF0_NO_EFFECT U(0)
+/* Tag Check Faults in EL0 cause a synchronous exception */
+#define SCTLR_TCF0_SYNC U(1)
+/* Tag Check Faults in EL0 are asynchronously accumulated */
+#define SCTLR_TCF0_ASYNC U(2)
+/*
+ * Tag Check Faults in EL0 cause a synchronous exception on reads,
+ * and are asynchronously accumulated on writes
+ */
+#define SCTLR_TCF0_SYNCR_ASYNCW U(3)
+
+#define SCTLR_TCF_SHIFT U(40)
+#define SCTLR_TCF_MASK ULL(3)
+
+/* Tag Check Faults in EL1 have no effect on the PE */
+#define SCTLR_TCF_NO_EFFECT U(0)
+/* Tag Check Faults in EL1 cause a synchronous exception */
+#define SCTLR_TCF_SYNC U(1)
+/* Tag Check Faults in EL1 are asynchronously accumulated */
+#define SCTLR_TCF_ASYNC U(2)
+/*
+ * Tag Check Faults in EL1 cause a synchronous exception on reads,
+ * and are asynchronously accumulated on writes
+ */
+#define SCTLR_TCF_SYNCR_ASYNCW U(3)
+
+#define SCTLR_ATA0_BIT (ULL(1) << 42)
+#define SCTLR_ATA_BIT (ULL(1) << 43)
#define SCTLR_DSSBS_BIT (ULL(1) << 44)
+#define SCTLR_TWEDEn_BIT (ULL(1) << 45)
+#define SCTLR_TWEDEL_SHIFT U(46)
+#define SCTLR_TWEDEL_MASK ULL(0xf)
+#define SCTLR_EnASR_BIT (ULL(1) << 54)
+#define SCTLR_EnAS0_BIT (ULL(1) << 55)
+#define SCTLR_EnALS_BIT (ULL(1) << 56)
+#define SCTLR_EPAN_BIT (ULL(1) << 57)
#define SCTLR_RESET_VAL SCTLR_EL3_RES1
-/* CPACR_El1 definitions */
+/* CPACR_EL1 definitions */
#define CPACR_EL1_FPEN(x) ((x) << 20)
#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
#define CPACR_EL1_FP_TRAP_ALL UL(0x2)
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index 9998b93..b50befa 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -64,12 +64,4 @@
#define CPUPOR_EL3 S3_6_C15_C8_2
#define CPUPMR_EL3 S3_6_C15_C8_3
-/******************************************************************************
- * CPU Configuration register definitions.
- *****************************************************************************/
-#define CPUCFR_EL1 S3_0_C15_C0_0
-
-/* SCU bit of CPU Configuration Register, EL1 */
-#define SCU_SHIFT U(2)
-
#endif /* NEOVERSE_N1_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
new file mode 100644
index 0000000..7cbd8c1
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_N2_H
+#define NEOVERSE_N2_H
+
+/* Neoverse N2 ID register for revision r0p0 */
+#define NEOVERSE_N2_MIDR U(0x410FD490)
+
+/*******************************************************************************
+ * CPU Power control register
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
+#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
+#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
+
+#endif /* NEOVERSE_N2_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n_common.h b/include/lib/cpus/aarch64/neoverse_n_common.h
new file mode 100644
index 0000000..7cb91cd
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_n_common.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_N_COMMON_H
+#define NEOVERSE_N_COMMON_H
+
+/******************************************************************************
+ * Neoverse Nx CPU Configuration register definitions
+ *****************************************************************************/
+#define CPUCFR_EL1 S3_0_C15_C0_0
+
+/* SCU bit of CPU Configuration Register, EL1 */
+#define SCU_SHIFT U(2)
+
+#endif /* NEOVERSE_N_COMMON_H */
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 03ee472..96891be 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -1,15 +1,15 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
-#include <neoverse_n1.h>
#include <cpuamu.h>
#include <cpu_macros.S>
#include <context.h>
+#include <neoverse_n1.h>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
@@ -22,19 +22,6 @@
#endif
.global neoverse_n1_errata_ic_trap_handler
- .global is_scu_present_in_dsu
-
-/*
- * Check DSU is configured with SCU and L3 unit
- * 1-> SCU present
- * 0-> SCU not present
- */
-func is_scu_present_in_dsu
- mrs x0, CPUCFR_EL1
- ubfx x0, x0, #SCU_SHIFT, #1
- eor x0, x0, #1
- ret
-endfunc is_scu_present_in_dsu
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Erratum 1043202.
@@ -515,7 +502,7 @@
msr CPUAMCNTENSET_EL0, x0
#endif
-#if NEOVERSE_N1_EXTERNAL_LLC
+#if NEOVERSE_Nx_EXTERNAL_LLC
/* Some system may have External LLC, core needs to be made aware */
mrs x0, NEOVERSE_N1_CPUECTLR_EL1
orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
new file mode 100644
index 0000000..8d646cb
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+#include <neoverse_n2.h>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Neoverse N2.
+ * -------------------------------------------------
+ */
+func neoverse_n2_reset_func
+ /* Check if the PE implements SSBS */
+ mrs x0, id_aa64pfr1_el1
+ tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
+ b.eq 1f
+
+ /* Disable speculative loads */
+ msr SSBS, xzr
+1:
+ /* Force all cacheable atomic instructions to be near */
+ mrs x0, NEOVERSE_N2_CPUACTLR2_EL1
+ orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
+ msr NEOVERSE_N2_CPUACTLR2_EL1, x0
+
+#if ENABLE_AMU
+ /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
+ mrs x0, cptr_el3
+ orr x0, x0, #TAM_BIT
+ msr cptr_el3, x0
+
+ /* Make sure accesses from EL0/EL1 are not trapped to EL2 */
+ mrs x0, cptr_el2
+ orr x0, x0, #TAM_BIT
+ msr cptr_el2, x0
+
+ /* No need to enable the counters as this would be done at el3 exit */
+#endif
+
+#if NEOVERSE_Nx_EXTERNAL_LLC
+ /* Some systems may have External LLC, core needs to be made aware */
+ mrs x0, NEOVERSE_N2_CPUECTLR_EL1
+ orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
+ msr NEOVERSE_N2_CPUECTLR_EL1, x0
+#endif
+
+ isb
+ ret
+endfunc neoverse_n2_reset_func
+
+func neoverse_n2_core_pwr_dwn
+ /* ---------------------------------------------
+ * Enable CPU power down bit in power control register
+ * No need to do cache maintenance here.
+ * ---------------------------------------------
+ */
+ mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
+ orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
+ msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc neoverse_n2_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Neoverse N2 cores. Must follow AAPCS.
+ */
+func neoverse_n2_errata_report
+ /* No errata reported for Neoverse N2 cores */
+ ret
+endfunc neoverse_n2_errata_report
+#endif
+
+ /* ---------------------------------------------
+ * This function provides Neoverse N2 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ASCII and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.neoverse_n2_regs, "aS"
+neoverse_n2_regs: /* The ASCII list of register names to be reported */
+ .asciz "cpupwrctlr_el1", ""
+
+func neoverse_n2_cpu_reg_dump
+ adr x6, neoverse_n2_regs
+ mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1
+ ret
+endfunc neoverse_n2_cpu_reg_dump
+
+declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \
+ neoverse_n2_reset_func, \
+ neoverse_n2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_n_common.S b/lib/cpus/aarch64/neoverse_n_common.S
new file mode 100644
index 0000000..b816342
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_n_common.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <neoverse_n_common.h>
+
+ .global is_scu_present_in_dsu
+
+/*
+ * Check if the SCU L3 Unit is present on the DSU
+ * 1-> SCU present
+ * 0-> SCU not present
+ *
+ * This function is implemented as weak on dsu_helpers.S and must be
+ * overwritten for Neoverse Nx cores.
+ */
+
+func is_scu_present_in_dsu
+ mrs x0, CPUCFR_EL1
+ ubfx x0, x0, #SCU_SHIFT, #1
+ eor x0, x0, #1
+ ret
+endfunc is_scu_present_in_dsu
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 4126105..084e6e7 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -25,9 +25,9 @@
WORKAROUND_CVE_2018_3639 ?=1
DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
-# Flag to indicate internal or external Last level cache
+# Flags to indicate internal or external Last level cache
# By default internal
-NEOVERSE_N1_EXTERNAL_LLC ?=0
+NEOVERSE_Nx_EXTERNAL_LLC ?=0
# Process A57_ENABLE_NONCACHEABLE_LOAD_FWD flag
$(eval $(call assert_boolean,A57_ENABLE_NONCACHEABLE_LOAD_FWD))
@@ -56,8 +56,8 @@
$(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639))
$(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639))
-$(eval $(call assert_boolean,NEOVERSE_N1_EXTERNAL_LLC))
-$(eval $(call add_define,NEOVERSE_N1_EXTERNAL_LLC))
+$(eval $(call assert_boolean,NEOVERSE_Nx_EXTERNAL_LLC))
+$(eval $(call add_define,NEOVERSE_Nx_EXTERNAL_LLC))
ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
ifeq (${WORKAROUND_CVE_2018_3639},0)
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index b460731..72d463b 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -144,30 +144,33 @@
scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
#endif /* !CTX_INCLUDE_PAUTH_REGS */
+#if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
+ /* Get Memory Tagging Extension support level */
+ unsigned int mte = get_armv8_5_mte_support();
+#endif
/*
* Enable MTE support. Support is enabled unilaterally for the normal
* world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
* set.
*/
#if CTX_INCLUDE_MTE_REGS
- assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX);
+ assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
scr_el3 |= SCR_ATA_BIT;
#else
- unsigned int mte = get_armv8_5_mte_support();
- if (mte == MTE_IMPLEMENTED_EL0) {
- /*
- * Can enable MTE across both worlds as no MTE registers are
- * used
- */
- scr_el3 |= SCR_ATA_BIT;
- } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) {
- /*
- * Can only enable MTE in Non-Secure world without register
- * saving
- */
+ /*
+ * When MTE is only implemented at EL0, it can be enabled
+ * across both worlds as no MTE registers are used.
+ */
+ if ((mte == MTE_IMPLEMENTED_EL0) ||
+ /*
+ * When MTE is implemented at all ELs, it can be only enabled
+ * in Non-Secure world without register saving.
+ */
+ (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) &&
+ (security_state == NON_SECURE))) {
scr_el3 |= SCR_ATA_BIT;
}
-#endif
+#endif /* CTX_INCLUDE_MTE_REGS */
#ifdef IMAGE_BL31
/*
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 4b751fb..3ac1c01 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -59,7 +59,9 @@
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/cortex_a77.S \
lib/cpus/aarch64/cortex_a78.S \
+ lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_a78_ae.S \
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 4da0d76..0a6fa56 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -118,7 +118,9 @@
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/cortex_a77.S \
lib/cpus/aarch64/cortex_a78.S \
+ lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_a78_ae.S \
diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk
index 4b621e3..f20397a 100644
--- a/plat/arm/board/n1sdp/platform.mk
+++ b/plat/arm/board/n1sdp/platform.mk
@@ -69,7 +69,7 @@
USE_COHERENT_MEM := 0
# Enable the flag since N1SDP has a system level cache
-NEOVERSE_N1_EXTERNAL_LLC := 1
+NEOVERSE_Nx_EXTERNAL_LLC := 1
include plat/arm/common/arm_common.mk
include plat/arm/css/common/css_common.mk
include plat/arm/board/common/board_common.mk
diff --git a/plat/marvell/version.mk b/plat/marvell/version.mk
index e072e12..bb22255 100644
--- a/plat/marvell/version.mk
+++ b/plat/marvell/version.mk
@@ -1 +1 @@
-SUBVERSION = devel-18.12.0
+SUBVERSION = devel-18.12.2
diff --git a/plat/rockchip/common/rockchip_stack_protector.c b/plat/rockchip/common/rockchip_stack_protector.c
new file mode 100644
index 0000000..1898977
--- /dev/null
+++ b/plat/rockchip/common/rockchip_stack_protector.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <arch_helpers.h>
+#include <plat/common/platform.h>
+
+#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL)
+
+u_register_t plat_get_stack_protector_canary(void)
+{
+ /*
+ * Ideally, a random number should be returned instead of the
+ * combination of a timer's value and a compile-time constant.
+ * As the virt platform does not have any random number generator,
+ * this is better than nothing but not necessarily really secure.
+ */
+ return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
+}
+
diff --git a/plat/rockchip/px30/platform.mk b/plat/rockchip/px30/platform.mk
index 87cf187..b1bb807 100644
--- a/plat/rockchip/px30/platform.mk
+++ b/plat/rockchip/px30/platform.mk
@@ -36,6 +36,10 @@
lib/xlat_tables/aarch64/xlat_tables.c \
plat/common/plat_psci_common.c
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c
+endif
+
BL31_SOURCES += ${RK_GIC_SOURCES} \
common/desc_image_load.c \
drivers/arm/cci/cci.c \
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index 0219422..5a307e4 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -35,6 +35,10 @@
plat/common/aarch64/crash_console_helpers.S \
plat/common/plat_psci_common.c
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c
+endif
+
BL31_SOURCES += ${RK_GIC_SOURCES} \
drivers/arm/cci/cci.c \
drivers/ti/uart/aarch64/16550_console.S \
diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk
index cb0cb89..e787293 100644
--- a/plat/rockchip/rk3368/platform.mk
+++ b/plat/rockchip/rk3368/platform.mk
@@ -33,6 +33,10 @@
plat/common/aarch64/crash_console_helpers.S \
plat/common/plat_psci_common.c
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c
+endif
+
BL31_SOURCES += ${RK_GIC_SOURCES} \
drivers/arm/cci/cci.c \
drivers/ti/uart/aarch64/16550_console.S \
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index a658fb2..aba67c2 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -38,6 +38,10 @@
plat/common/aarch64/crash_console_helpers.S \
plat/common/plat_psci_common.c
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c
+endif
+
BL31_SOURCES += ${RK_GIC_SOURCES} \
drivers/arm/cci/cci.c \
drivers/ti/uart/aarch64/16550_console.S \
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 44f20f6..1cd168f 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -59,13 +59,14 @@
-Iplat/xilinx/zynqmp/include/ \
-Iplat/xilinx/zynqmp/pm_service/ \
+# Include GICv2 driver files
+include drivers/arm/gic/v2/gicv2.mk
+
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
- drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
+ ${GICV2_SOURCES} \
drivers/cadence/uart/aarch64/cdns_console.S \
plat/arm/common/arm_cci.c \
plat/arm/common/arm_common.c \
@@ -95,6 +96,8 @@
plat/xilinx/zynqmp/pm_service/pm_api_clock.c \
plat/xilinx/zynqmp/pm_service/pm_client.c
+BL31_CPPFLAGS += -fno-jump-tables
+
ifneq (${RESET_TO_BL31},1)
$(error "Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1.")
endif
diff --git a/services/std_svc/spm_mm/spm_mm_setup.c b/services/std_svc/spm_mm/spm_mm_setup.c
index 468e5b3..32562c3 100644
--- a/services/std_svc/spm_mm/spm_mm_setup.c
+++ b/services/std_svc/spm_mm/spm_mm_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -142,6 +142,8 @@
SCTLR_DZE_BIT |
/* Enable SP Alignment check for EL0 */
SCTLR_SA0_BIT |
+ /* Don't change PSTATE.PAN on taking an exception to EL1 */
+ SCTLR_SPAN_BIT |
/* Allow cacheable data and instr. accesses to normal memory. */
SCTLR_C_BIT | SCTLR_I_BIT |
/* Enable MMU. */