FVP: Add support for passing platform's topology to DTS

This patch adds support for passing FVP platform's topology
configuration to DTS files for compilation, which allows to
build DTBs with correct number of clusters and CPUs.
This removes non-existing clusters/CPUs from the compiled
device tree blob and fixes reported Linux errors when trying
to power on absent CPUs/PEs.
If DTS file is passed using FVP_HW_CONFIG_DTS build option from
the platform's makefile, FVP_CLUSTER_COUNT, FVP_MAX_CPUS_PER_CLUSTER
and FVP_MAX_PE_PER_CPU parameters are used, otherwise CI script will
use the default values from the corresponding DTS file.

Change-Id: Idcb45dc6ad5e3eaea18573aff1a01c9344404ab3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
index 6e63b43..bda4b8d 100644
--- a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
+++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
@@ -4,185 +4,15 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-/dts-v1/;
-
-#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
-
-&CPU_MAP {
-	/delete-node/ cluster0;
-
-	cluster0 {
-		core0 {
-			thread0 {
-				cpu = <&CPU0>;
-			};
-			thread1 {
-				cpu = <&CPU1>;
-			};
-		};
-		core1 {
-			thread0 {
-				cpu = <&CPU2>;
-			};
-			thread1 {
-				cpu = <&CPU3>;
-			};
-		};
-		core2 {
-			thread0 {
-				cpu = <&CPU4>;
-			};
-			thread1 {
-				cpu = <&CPU5>;
-			};
-		};
-		core3 {
-			thread0 {
-				cpu = <&CPU6>;
-			};
-			thread1 {
-				cpu = <&CPU7>;
-			};
-		};
-		core4 {
-			thread0 {
-				cpu = <&CPU8>;
-			};
-			thread1 {
-				cpu = <&CPU9>;
-			};
-		};
-		core5 {
-			thread0 {
-				cpu = <&CPU10>;
-			};
-			thread1 {
-				cpu = <&CPU11>;
-			};
-		};
-		core6 {
-			thread0 {
-				cpu = <&CPU12>;
-			};
-			thread1 {
-				cpu = <&CPU13>;
-			};
-		};
-		core7 {
-			thread0 {
-				cpu = <&CPU14>;
-			};
-			thread1 {
-				cpu = <&CPU15>;
-			};
-		};
-	};
-};
-
-/ {
-	cpus {
-		CPU0:cpu@0 {
-			reg = <0x0 0x0>;
-		};
-
-		CPU1:cpu@1 {
-			reg = <0x0 0x1>;
-		};
-
-		CPU2:cpu@2 {
-			reg = <0x0 0x100>;
-		};
-
-		CPU3:cpu@3 {
-			reg = <0x0 0x101>;
-		};
-
-		CPU4:cpu@100 {
-			reg = <0x0 0x200>;
-		};
+/* DynamIQ configuration: 1 cluster with up to 8 CPUs with 2 threads per each */
 
-		CPU5:cpu@101 {
-			reg = <0x0 0x201>;
-		};
+/* Set default value if not passed from platform's makefile */
+#ifdef	FVP_MAX_PE_PER_CPU
+#define	PE_PER_CPU		FVP_MAX_PE_PER_CPU
+#else
+#define	PE_PER_CPU		2
+#endif
 
-		CPU6:cpu@102 {
-			reg = <0x0 0x300>;
-		};
-
-		CPU7:cpu@103 {
-			reg = <0x0 0x301>;
-		};
-
-		CPU8:cpu@200 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x400>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU9:cpu@201 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x401>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU10:cpu@202 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x500>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU11:cpu@203 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x501>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU12:cpu@300 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x600>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU13:cpu@301 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x601>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU14:cpu@302 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x700>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
+/dts-v1/;
 
-		CPU15:cpu@303 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x701>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-	};
-};
+#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"