fix(stm32mp13-fdts): cosmetic fixes in PLL nodes
- remove spaces in DT properties.
- rename pll3_vco_417_8Mhz into pll3_vco_417Mhz
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Iec3b9ef70dd3c70873263f4959bf6c03d26cbe7d
diff --git a/fdts/stm32mp135f-dk.dts b/fdts/stm32mp135f-dk.dts
index 0f06b67..1204692 100644
--- a/fdts/stm32mp135f-dk.dts
+++ b/fdts/stm32mp135f-dk.dts
@@ -223,20 +223,20 @@
};
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
- src = < CLK_PLL12_HSE >;
- divmn = < 2 65 >;
- frac = < 0x1400 >;
+ src = <CLK_PLL12_HSE>;
+ divmn = <2 65>;
+ frac = <0x1400>;
};
- pll3_vco_417_8Mhz: pll3-vco-417_8Mhz {
- src = < CLK_PLL3_HSE >;
- divmn = < 1 33 >;
- frac = < 0x1a04 >;
+ pll3_vco_417Mhz: pll3-vco-417Mhz {
+ src = <CLK_PLL3_HSE>;
+ divmn = <1 33>;
+ frac = <0x1a04>;
};
pll4_vco_600Mhz: pll4-vco-600Mhz {
- src = < CLK_PLL4_HSE >;
- divmn = < 1 49 >;
+ src = <CLK_PLL4_HSE>;
+ divmn = <1 49>;
};
};
@@ -258,11 +258,11 @@
compatible = "st,stm32mp1-pll";
reg = <1>;
- st,pll = < &pll2_cfg1 >;
+ st,pll = <&pll2_cfg1>;
pll2_cfg1: pll2_cfg1 {
- st,pll_vco = < &pll2_vco_1066Mhz >;
- st,pll_div_pqr = < 1 1 0 >;
+ st,pll_vco = <&pll2_vco_1066Mhz>;
+ st,pll_div_pqr = <1 1 0>;
};
};
@@ -271,11 +271,11 @@
compatible = "st,stm32mp1-pll";
reg = <2>;
- st,pll = < &pll3_cfg1 >;
+ st,pll = <&pll3_cfg1>;
pll3_cfg1: pll3_cfg1 {
- st,pll_vco = < &pll3_vco_417_8Mhz >;
- st,pll_div_pqr = < 1 16 1 >;
+ st,pll_vco = <&pll3_vco_417Mhz>;
+ st,pll_div_pqr = <1 16 1>;
};
};
@@ -284,11 +284,11 @@
compatible = "st,stm32mp1-pll";
reg = <3>;
- st,pll = < &pll4_cfg1 >;
+ st,pll = <&pll4_cfg1>;
pll4_cfg1: pll4_cfg1 {
- st,pll_vco = < &pll4_vco_600Mhz >;
- st,pll_div_pqr = < 11 59 5 >;
+ st,pll_vco = <&pll4_vco_600Mhz>;
+ st,pll_div_pqr = <11 59 5>;
};
};
};