diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
index 74677f6..076fafb 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
@@ -57,14 +57,22 @@
    uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
    uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
    uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
+/* rev.0.10 */
+   uint32_t pdr_ctl;
+/* rev.0.11 */
+   uint32_t byp_ctl;
 
 /* rev.0.08 */
    if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
      pdqsr_ctl  = 1;
      lcdl_ctl   = 1;
+     pdr_ctl    = 1;  /* rev.0.10 */
+     byp_ctl    = 1;  /* rev.0.11 */
     }else {
      pdqsr_ctl  = 0;
      lcdl_ctl   = 0;
+     pdr_ctl    = 0;  /* rev.0.10 */
+     byp_ctl    = 0;  /* rev.0.11 */
    }
 
    /*  Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
@@ -198,6 +206,7 @@
    WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
    WriteReg_32(DBSC_E3_DBCMD,0x01840001);
    WriteReg_32(DBSC_E3_DBCMD,0x08840000);
+   NOTICE("BL2: [COLD_BOOT]\n");	/* rev.0.11 */
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
@@ -266,7 +275,11 @@
    while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
 
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
+   if (byp_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C720);
+   } else {
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
+   }
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
    while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
 
@@ -394,10 +407,6 @@
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
 
-   /*  rev.0.03 add Comment */
-   /****************************************************************************
-    *  Initial_Step4( WLADJ training )
-    ***************************************************************************/
    for ( i = 0; i<4; i++){
       WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
       RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
@@ -426,6 +435,10 @@
       } /*  RegVal_R6 */
    } /*  for i */
 
+   /*  rev.0.10 move Comment */
+   /****************************************************************************
+    *  Initial_Step4( WLADJ training )
+    ***************************************************************************/
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
    WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
 
@@ -441,6 +454,18 @@
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
 
+   }
+
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
    }
 
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
@@ -448,9 +473,8 @@
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
 
-   /*  rev.0.03 add Comment */
    /****************************************************************************
-    *  Initial_Step5678( RdWrbitRdWreye )
+    *  Initial_Step5(Read Data Bit Deskew)
     ***************************************************************************/
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
    WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
@@ -472,11 +496,29 @@
    WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
 }
 
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+   }
+
+   /****************************************************************************
+    *  Initial_Step6(Write Data Bit Deskew)
+    ***************************************************************************/
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
 
+   /****************************************************************************
+    *  Initial_Step7(Read Data Eye Training)
+    ***************************************************************************/
 if (pdqsr_ctl == 1){
    WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
@@ -488,6 +530,18 @@
    WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
 }
 
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+   }
+
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
@@ -504,6 +558,21 @@
    WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
 }
 
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+   }
+
+   /****************************************************************************
+    *  Initial_Step8(Write Data Eye Training)
+    ***************************************************************************/
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
@@ -528,10 +597,6 @@
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
 
-   /*  rev.0.03 add Comment */
-   /****************************************************************************
-    *  Initial_Step5-2_7-2( Rd bit Rd eye )
-    ***************************************************************************/
    for ( i = 0; i < 4; i++){
       WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
       RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
@@ -561,6 +626,10 @@
       } /*  RegVal_R12 < RegVal_R6 */
    } /*  for i */
 
+   /*  rev.0.10 move Comment */
+   /****************************************************************************
+    *  Initial_Step5-2_7-2( Rd bit Rd eye )
+    ***************************************************************************/
 /* rev.0.08 */
    if (pdqsr_ctl == 1){}else{
 
@@ -573,6 +642,18 @@
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
 
+   }
+
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
    }
 
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
@@ -658,7 +739,11 @@
 
 
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
+   if (byp_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C720);
+   } else {
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
+   }
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
    while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
 
@@ -696,6 +781,17 @@
 
    }
 
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+   }
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
@@ -766,14 +862,22 @@
    uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
    uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
    uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
+   /* rev.0.10 */
+   uint32_t pdr_ctl;
+   /* rev.0.11 */
+   uint32_t byp_ctl;
 
 /* rev.0.08 */
    if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
      pdqsr_ctl  = 1;
      lcdl_ctl   = 1;
+     pdr_ctl    = 1;  /* rev.0.10 */
+     byp_ctl    = 1;  /* rev.0.11 */
     }else {
      pdqsr_ctl  = 0;
      lcdl_ctl   = 0;
+     pdr_ctl    = 0;  /* rev.0.10 */
+     byp_ctl    = 0;  /* rev.0.11 */
    }
 
 
@@ -908,7 +1012,11 @@
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008); /*  DDR_PLLCR */
    WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003); /*  DDR_PGCR1 */
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
+   if (byp_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C720);
+   } else {
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
+   }
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020); /*  DDR_DXCCR */
    WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
    WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A); /*  DDR_ACIOCR0 */
@@ -1207,6 +1315,18 @@
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
 
+   }
+
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
    }
 
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
@@ -1235,6 +1355,18 @@
    WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
 }
 
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl==1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+   }
+
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
@@ -1251,6 +1383,18 @@
    WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
 }
 
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+   }
+
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
@@ -1267,6 +1411,18 @@
    WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
 }
 
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+   }
+
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
@@ -1331,6 +1487,18 @@
 
    }
 
+   /* PDR always off */	/* rev.0.10 */
+   if (pdr_ctl==1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
+   }
+
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
@@ -1415,7 +1583,11 @@
 
 
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
-   WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
+   if (byp_ctl==1) {
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C720);
+   } else {
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
+   }
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
    while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
@@ -1442,6 +1614,18 @@
    WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
 
+   }
+
+   /* PDR dynamic */	/* rev.0.10 */
+   if (pdr_ctl == 1) {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
    }
 
 
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
index 47fe07b..2e9a5bf 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
@@ -9,7 +9,7 @@
 
 #include <stdint.h>
 
-#define RCAR_E3_DDR_VERSION    "rev.0.09"
+#define RCAR_E3_DDR_VERSION    "rev.0.11"
 
 #ifdef ddr_qos_init_setting
    #define REFRESH_RATE  3900               /*  Average periodic refresh interval[ns]. Support 3900,7800 */