rockchip: support the suspend/resume for rk3399
1.Fixes the suspend/resume some bugs.
2.Add the power domain for saving power consumption.
3.Add cpu clusters suspend for rk3399 SoCs
Change-Id: Id602779016b41d6281f4ba40a20229d909b28e46
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
index bf2d441..d11a2f6 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.c
+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
@@ -69,6 +69,15 @@
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(GRF_BASE, GRF_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(SERVICE_NOC_0_BASE, NOC_0_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(SERVICE_NOC_1_BASE, NOC_1_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(SERVICE_NOC_2_BASE, NOC_2_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(SERVICE_NOC_3_BASE, NOC_3_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+
{ 0 }
};
@@ -272,8 +281,7 @@
for (i = 0; i < CRU_CLKSEL_COUNT; i++)
slp_data.cru_clksel_con[i] =
- mmio_read_32(CRU_BASE +
- CRU_CLKSEL_OFFSET + i * REG_SIZE);
+ mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(i));
for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++)
slp_data.pmucru_clksel_con[i] =
@@ -289,6 +297,43 @@
_pll_suspend(ALPLL_ID);
}
+void clk_gate_con_save(void)
+{
+ uint32_t i = 0;
+
+ for (i = 0; i < PMUCRU_GATE_COUNT; i++)
+ slp_data.pmucru_gate_con[i] =
+ mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i));
+
+ for (i = 0; i < CRU_GATE_COUNT; i++)
+ slp_data.cru_gate_con[i] =
+ mmio_read_32(CRU_BASE + CRU_GATE_CON(i));
+}
+
+void clk_gate_con_disable(void)
+{
+ uint32_t i;
+
+ for (i = 0; i < PMUCRU_GATE_COUNT; i++)
+ mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK);
+
+ for (i = 0; i < CRU_GATE_COUNT; i++)
+ mmio_write_32(CRU_BASE + CRU_GATE_CON(i), REG_SOC_WMSK);
+}
+
+void clk_gate_con_restore(void)
+{
+ uint32_t i;
+
+ for (i = 0; i < PMUCRU_GATE_COUNT; i++)
+ mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i),
+ REG_SOC_WMSK | slp_data.pmucru_gate_con[i]);
+
+ for (i = 0; i < CRU_GATE_COUNT; i++)
+ mmio_write_32(CRU_BASE + CRU_GATE_CON(i),
+ REG_SOC_WMSK | slp_data.cru_gate_con[i]);
+}
+
static void set_plls_nobypass(uint32_t pll_id)
{
if (pll_id == PPLL_ID)
@@ -304,7 +349,7 @@
int i;
for (i = 0; i < CRU_CLKSEL_COUNT; i++)
- mmio_write_32((CRU_BASE + CRU_CLKSEL_OFFSET + i * REG_SIZE),
+ mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)),
REG_SOC_WMSK | slp_data.cru_clksel_con[i]);
for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++)
mmio_write_32((PMUCRU_BASE +
@@ -351,7 +396,7 @@
* so we do not hope the core to excute valid codes.
*/
while (1)
- ;
+ ;
}
void plat_rockchip_soc_init(void)
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.h b/plat/rockchip/rk3399/drivers/soc/soc.h
index 4c6f000..26c0df6 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.h
+++ b/plat/rockchip/rk3399/drivers/soc/soc.h
@@ -34,12 +34,8 @@
#define GLB_SRST_FST_CFG_VAL 0xfdb9
#define GLB_SRST_SND_CFG_VAL 0xeca8
-#define PMUCRU_PPLL_CON_OFFSET 0x000
-#define PMUCRU_PPLL_CON_BASE_ADDR (PMUCRU_BASE + PMUCRU_PPLL_CON_OFFSET)
-#define PMUCRU_PPLL_CON_CONUT 0x06
-
-#define PMUCRU_PPLL_CON(num) (PMUCRU_PPLL_CON_BASE_ADDR + num * 4)
-#define CRU_PLL_CON(pll_id, num) (CRU_BASE + pll_id * 0x20 + num * 4)
+#define PMUCRU_PPLL_CON(n) ((n) * 4)
+#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
#define PLL_MODE_MSK 0x03
#define PLL_MODE_SHIFT 0x08
#define PLL_BYPASS_MSK 0x01
@@ -52,28 +48,30 @@
#define NO_PLL_BYPASS (0x00)
#define NO_PLL_PWRDN (0x00)
-#define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\
+#define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\
PLL_MODE_MSK, PLL_MODE_SHIFT)
-#define PLL_BYPASS_MODE BITS_WITH_WMASK(PLL_BYPASS,\
- PLL_BYPASS_MSK,\
- PLL_BYPASS_SHIFT)
-#define PLL_NO_BYPASS_MODE BITS_WITH_WMASK(NO_PLL_BYPASS,\
- PLL_BYPASS_MSK,\
- PLL_BYPASS_SHIFT)
-#define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\
+
+#define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\
PLL_MODE_MSK, PLL_MODE_SHIFT)
+#define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT)
+#define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT)
+
#define PLL_CON_COUNT 0x06
#define CRU_CLKSEL_COUNT 0x108
-#define CRU_CLKSEL_OFFSET 0x300
+#define CRU_CLKSEL_CON(n) (0x80 + (n) * 4)
#define PMUCRU_CLKSEL_CONUT 0x06
#define PMUCRU_CLKSEL_OFFSET 0x080
#define REG_SIZE 0x04
#define REG_SOC_WMSK 0xffff0000
-
#define CLK_GATE_MASK 0x01
+#define PMUCRU_GATE_COUNT 0x03
+#define CRU_GATE_COUNT 0x23
+#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4)
+#define CRU_GATE_CON(n) (0x300 + (n) * 4)
+
enum plls_id {
ALPLL_ID = 0,
ABPLL_ID,
@@ -86,6 +84,9 @@
END_PLL_ID,
};
+#define CLST_L_CPUS_MSK (0xf)
+#define CLST_B_CPUS_MSK (0x3)
+
enum pll_work_mode {
SLOW_MODE = 0x00,
NORMAL_MODE = 0x01,
@@ -102,10 +103,13 @@
uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT];
uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT];
uint32_t cru_clksel_con[CRU_CLKSEL_COUNT];
+ uint32_t cru_gate_con[CRU_GATE_COUNT];
+ uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
};
#define CYCL_24M_CNT_US(us) (24 * us)
#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000))
+#define CYCL_32K_CNT_MS(ms) (ms * 32)
/**************************************************
* secure timer
@@ -261,5 +265,7 @@
void __dead2 soc_global_soft_reset(void);
void plls_resume(void);
void plls_suspend(void);
-
+void clk_gate_con_save(void);
+void clk_gate_con_disable(void);
+void clk_gate_con_restore(void);
#endif /* __SOC_H__ */