tree c08a9348cf5016af8fc31d188f70bfba6e7abff4
parent de8daeca8468c95e9ec5e04935ecc17e3e252a11
author Soby Mathew <soby.mathew@arm.com> 1409651253 +0100
committer Soby Mathew <soby.mathew@arm.com> 1414604336 +0000

Add support for level specific cache maintenance operations

This patch adds level specific cache maintenance functions
to cache_helpers.S. The new functions 'dcsw_op_levelx',
where '1 <= x <= 3', allow to perform cache maintenance by
set/way for that particular level of cache.  With this patch,
functions to support cache maintenance upto level 3 have
been implemented since it is the highest cache level for
most ARM SoCs.

These functions are now utilized in CPU specific power down
sequences to implement them as mandated by processor specific
technical reference manual.

Change-Id: Icd90ce6b51cff5a12863bcda01b93601417fd45c