Merge "fix(intel): add in JTAG ID for Linux FCS" into integration
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index f61c479..ac4bf12 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -185,6 +185,21 @@
#define SDM 0x000A000A
#define CORE_SIGHT_DEBUG 0x000B000B
+/* JTAG ID value for Agilex5 */
+#define A590_JTAG_ID 0x9000
+#define A594_JTAG_ID 0x40009000
+#define A5C0_JTAG_ID 0xC000
+#define A5C4_JTAG_ID 0x4000C000
+#define A5D0_JTAG_ID 0xD000
+#define A5D4_JTAG_ID 0x4000D000
+#define A5F0_JTAG_ID 0xC000
+#define A5F4_JTAG_ID 0x4000F000
+#define A510_JTAG_ID 0x1000
+#define A514_JTAG_ID 0x40001000
+#define A530_JTAG_ID 0x3000
+#define A534_JTAG_ID 0x40003000
+#define JTAG_ID_MASK 0xC000F000
+
/* Field Masking */
#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)
diff --git a/plat/intel/soc/agilex5/platform.mk b/plat/intel/soc/agilex5/platform.mk
index 172b554..a831c39 100644
--- a/plat/intel/soc/agilex5/platform.mk
+++ b/plat/intel/soc/agilex5/platform.mk
@@ -99,6 +99,7 @@
plat/intel/soc/common/sip/socfpga_sip_ecc.c \
plat/intel/soc/common/sip/socfpga_sip_fcs.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
+ plat/intel/soc/common/soc/socfpga_system_manager.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c
# Configs for A76 and A55
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index fcee101..82f9fd3 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -247,6 +247,7 @@
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
void intel_smmu_hps_remapper_init(uint64_t *mem);
+int intel_smmu_hps_remapper_config(uint32_t remapper_bypass);
#endif
int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index d2eceb9..31474c4 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -140,6 +140,7 @@
#define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE 0xC200008B
#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C
#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E
+#define INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG 0xC2000201
/* SEU ERR */
#define INTEL_SIP_SMC_SEU_ERR_STATUS 0xC2000099
diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h
index 1327b81..346cfe1 100644
--- a/plat/intel/soc/common/include/socfpga_system_manager.h
+++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,4 +33,8 @@
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ (SOCFPGA_SYSMGR_##_reg))
+/* Function Prototype */
+uint32_t intel_hps_get_jtag_id(void);
+bool is_agilex5_A5F0(void);
+
#endif /* SOCFPGA_SYSTEMMANAGER_H */
diff --git a/plat/intel/soc/common/soc/socfpga_system_manager.c b/plat/intel/soc/common/soc/socfpga_system_manager.c
new file mode 100644
index 0000000..4223b2b
--- /dev/null
+++ b/plat/intel/soc/common/soc/socfpga_system_manager.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+#include "socfpga_system_manager.h"
+
+uint32_t intel_hps_get_jtag_id(void)
+{
+ uint32_t jtag_id = 0x00;
+
+ jtag_id = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_4)));
+
+ INFO("%s: JTAG ID: 0x%x\n", __func__, jtag_id);
+
+ return jtag_id;
+}
+
+/* Check for Agilex5 SM4 */
+bool is_agilex5_A5F0(void)
+{
+ return ((intel_hps_get_jtag_id() & JTAG_ID_MASK) == A5F0_JTAG_ID);
+}
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 5dfbc14..3c223c1 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -28,6 +28,9 @@
static uint32_t send_id, rcv_id;
static uint32_t bytes_per_block, blocks_submitted;
static bool bridge_disable;
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+static uint32_t g_remapper_bypass;
+#endif
/* RSU static variables */
static uint32_t rsu_dcmf_ver[4] = {0};
@@ -758,7 +761,7 @@
/* Read out Bit 1 value */
uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02);
- if (remap == 0x00) {
+ if ((remap == 0x00) && (g_remapper_bypass == 0x00)) {
/* Update DRAM Base address for SDM SMMU */
mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE);
mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE);
@@ -766,6 +769,19 @@
} else {
*mem = *mem - DRAM_BASE;
}
+}
+
+int intel_smmu_hps_remapper_config(uint32_t remapper_bypass)
+{
+ /* Read out the JTAG-ID from boot scratch register */
+ if (is_agilex5_A5F0() != 0) {
+ if (remapper_bypass == 0x01) {
+ g_remapper_bypass = remapper_bypass;
+ mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0);
+ mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0);
+ }
+ }
+ return INTEL_SIP_SMC_STATUS_OK;
}
#endif
@@ -1291,6 +1307,12 @@
status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
x5, x6, true, &send_id);
SMC_RET1(handle, status);
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG:
+ status = intel_smmu_hps_remapper_config(x1);
+ SMC_RET1(handle, status);
+#endif
case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384:
status = intel_fcs_get_rom_patch_sha384(x1, &retval64,