plat: xilinx: versal: Dont set IOU switch clock
The IOU switch clock will be set by PLM during boot so there is no need to
set here and hence this patch removes it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I1512708411eb07a07c1a8fbd66575efee975431a
diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c
index 29528da..825421e 100644
--- a/plat/xilinx/versal/aarch64/versal_common.c
+++ b/plat/xilinx/versal/aarch64/versal_common.c
@@ -46,10 +46,6 @@
versal_print_platform_name();
- mmio_write_32(VERSAL_CRL_IOU_SWITCH_CTRL,
- VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT |
- (0x20 << VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT));
-
/* Global timer init - Program time stamp reference clk */
val = mmio_read_32(VERSAL_CRL_TIMESTAMP_REF_CTRL);
val |= VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index c08928a..a1479a1 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -35,13 +35,10 @@
/* CRL */
#define VERSAL_CRL 0xFF5E0000
-#define VERSAL_CRL_IOU_SWITCH_CTRL (VERSAL_CRL + 0x114)
#define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C)
#define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348)
#define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25)
-#define VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT (1 << 25)
-#define VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
/* IOU SCNTRS */
#define VERSAL_IOU_SCNTRS 0xFF140000