diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h
index 24a9c6c..8e86df4 100644
--- a/include/lib/cpus/aarch32/cortex_a53.h
+++ b/include/lib/cpus/aarch32/cortex_a53.h
@@ -40,11 +40,11 @@
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A53_ACTLR			p15, 0, c15
+#define CORTEX_A53_CPUACTLR			p15, 0, c15
 
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT	44
-#define CORTEX_A53_ACTLR_ENDCCASCI		(1 << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT)
-#define CORTEX_A53_ACTLR_DTAH			(1 << 24)
+#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT	44
+#define CORTEX_A53_CPUACTLR_ENDCCASCI		(1 << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT)
+#define CORTEX_A53_CPUACTLR_DTAH		(1 << 24)
 
 /*******************************************************************************
  * L2 Auxiliary Control register specific definitions.
@@ -67,4 +67,16 @@
  ******************************************************************************/
 #define CORTEX_A53_L2MERRSR			p15, 3, c15
 
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A53_ACTLR			CORTEX_A53_CPUACTLR
+
+#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT	CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT
+#define CORTEX_A53_ACTLR_ENDCCASCI		CORTEX_A53_CPUACTLR_ENDCCASCI
+#define CORTEX_A53_ACTLR_DTAH			CORTEX_A53_CPUACTLR_DTAH
+#endif /* !ERROR_DEPRECATED */
+
 #endif /* __CORTEX_A53_H__ */
diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h
index 9afcfd8..d3ae5b9 100644
--- a/include/lib/cpus/aarch32/cortex_a57.h
+++ b/include/lib/cpus/aarch32/cortex_a57.h
@@ -41,17 +41,17 @@
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A57_ACTLR			p15, 0, c15
+#define CORTEX_A57_CPUACTLR				p15, 0, c15
 
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB	(ULL(1) << 59)
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE	(ULL(1) << 54)
-#define CORTEX_A57_ACTLR_DIS_OVERREAD		(ULL(1) << 52)
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA		(ULL(1) << 49)
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI		(ULL(1) << 44)
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH	(ULL(1) << 38)
-#define CORTEX_A57_ACTLR_DIS_STREAMING		(ULL(3) << 27)
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING	(ULL(3) << 25)
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR	(ULL(1) << 4)
+#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB		(ULL(1) << 59)
+#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE		(ULL(1) << 54)
+#define CORTEX_A57_CPUACTLR_DIS_OVERREAD		(ULL(1) << 52)
+#define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA		(ULL(1) << 49)
+#define CORTEX_A57_CPUACTLR_DCC_AS_DCCI			(ULL(1) << 44)
+#define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH		(ULL(1) << 38)
+#define CORTEX_A57_CPUACTLR_DIS_STREAMING		(ULL(3) << 27)
+#define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING		(ULL(3) << 25)
+#define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR	(ULL(1) << 4)
 
 /*******************************************************************************
  * L2 Control register specific definitions.
@@ -77,4 +77,22 @@
  ******************************************************************************/
 #define CORTEX_A57_L2MERRSR			p15, 3, c15
 
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A57_ACTLR			CORTEX_A57_CPUACTLR
+
+#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB	CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
+#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE	CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
+#define CORTEX_A57_ACTLR_DIS_OVERREAD		CORTEX_A57_CPUACTLR_DIS_OVERREAD
+#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA		CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
+#define CORTEX_A57_ACTLR_DCC_AS_DCCI		CORTEX_A57_CPUACTLR_DCC_AS_DCCI
+#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH	CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
+#define CORTEX_A57_ACTLR_DIS_STREAMING		CORTEX_A57_CPUACTLR_DIS_STREAMING
+#define CORTEX_A57_ACTLR_DIS_L1_STREAMING	CORTEX_A57_CPUACTLR_DIS_L1_STREAMING
+#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR	CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
+#endif /* !ERROR_DEPRECATED */
+
 #endif /* __CORTEX_A57_H__ */
diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h
index ed406ef..306253d 100644
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -29,11 +29,11 @@
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A72_ACTLR				p15, 0, c15
+#define CORTEX_A72_CPUACTLR				p15, 0, c15
 
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			(ULL(1) << 49)
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI			(ULL(1) << 44)
+#define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
+#define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA		(ULL(1) << 49)
+#define CORTEX_A72_CPUACTLR_DCC_AS_DCCI			(ULL(1) << 44)
 
 /*******************************************************************************
  * L2 Control register specific definitions.
@@ -52,4 +52,16 @@
  ******************************************************************************/
 #define CORTEX_A72_L2MERRSR				p15, 3, c15
 
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A72_ACTLR				CORTEX_A72_CPUACTLR
+
+#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
+#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA
+#define CORTEX_A72_ACTLR_DCC_AS_DCCI			CORTEX_A72_CPUACTLR_DCC_AS_DCCI
+#endif /* !ERROR_DEPRECATED */
+
 #endif /* __CORTEX_A72_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 6627dcf..22c6800 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -22,53 +22,70 @@
 /*******************************************************************************
  * CPU Extended Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A53_ECTLR_EL1		S3_1_C15_C2_1
+#define CORTEX_A53_ECTLR_EL1				S3_1_C15_C2_1
 
-#define CORTEX_A53_ECTLR_SMP_BIT	(U(1) << 6)
+#define CORTEX_A53_ECTLR_SMP_BIT			(U(1) << 6)
 
-#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT	U(0)
-#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK	(U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
+#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT		U(0)
+#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK		(U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
 
-#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT	U(3)
-#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK	(U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
+#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT		U(3)
+#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK		(U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
 
 /*******************************************************************************
  * CPU Memory Error Syndrome register specific definitions.
  ******************************************************************************/
-#define CORTEX_A53_MERRSR_EL1			S3_1_C15_C2_2
+#define CORTEX_A53_MERRSR_EL1				S3_1_C15_C2_2
 
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A53_ACTLR_EL1			S3_1_C15_C2_0
+#define CORTEX_A53_CPUACTLR_EL1				S3_1_C15_C2_0
 
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT	U(44)
-#define CORTEX_A53_ACTLR_ENDCCASCI		(U(1) << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT)
-#define CORTEX_A53_ACTLR_RADIS_SHIFT		U(27)
-#define CORTEX_A53_ACTLR_RADIS			(U(3) << CORTEX_A53_ACTLR_RADIS_SHIFT)
-#define CORTEX_A53_ACTLR_L1RADIS_SHIFT		U(25)
-#define CORTEX_A53_ACTLR_L1RADIS		(U(3) << CORTEX_A53_ACTLR_L1RADIS_SHIFT)
-#define CORTEX_A53_ACTLR_DTAH_SHIFT		U(24)
-#define CORTEX_A53_ACTLR_DTAH			(U(1) << CORTEX_A53_ACTLR_DTAH_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT		U(44)
+#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI		(U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT		U(27)
+#define CORTEX_A53_CPUACTLR_EL1_RADIS			(U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT		U(25)
+#define CORTEX_A53_CPUACTLR_EL1_L1RADIS			(U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT		U(24)
+#define CORTEX_A53_CPUACTLR_EL1_DTAH			(U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
 
 /*******************************************************************************
  * L2 Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A53_L2ACTLR_EL1			S3_1_C15_C0_0
+#define CORTEX_A53_L2ACTLR_EL1				S3_1_C15_C0_0
 
-#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN	(U(1) << 14)
-#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH	(U(1) << 3)
+#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN		(U(1) << 14)
+#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH		(U(1) << 3)
 /*******************************************************************************
  * L2 Extended Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A53_L2ECTLR_EL1			S3_1_C11_C0_3
+#define CORTEX_A53_L2ECTLR_EL1				S3_1_C11_C0_3
 
-#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT	U(0)
-#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK	(U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
+#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT		U(0)
+#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK		(U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
 
 /*******************************************************************************
  * L2 Memory Error Syndrome register specific definitions.
  ******************************************************************************/
-#define CORTEX_A53_L2MERRSR_EL1			S3_1_C15_C2_3
+#define CORTEX_A53_L2MERRSR_EL1				S3_1_C15_C2_3
+
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions
+ * so as not to break platforms that continue using them.
+ */
+#define CORTEX_A53_ACTLR_EL1			CORTEX_A53_CPUACTLR_EL1
+
+#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT	CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT
+#define CORTEX_A53_ACTLR_ENDCCASCI		CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
+#define CORTEX_A53_ACTLR_RADIS_SHIFT		CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT
+#define CORTEX_A53_ACTLR_RADIS			CORTEX_A53_CPUACTLR_EL1_RADIS
+#define CORTEX_A53_ACTLR_L1RADIS_SHIFT		CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT
+#define CORTEX_A53_ACTLR_L1RADIS		CORTEX_A53_CPUACTLR_EL1_L1RADIS
+#define CORTEX_A53_ACTLR_DTAH_SHIFT		CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT
+#define CORTEX_A53_ACTLR_DTAH			CORTEX_A53_CPUACTLR_EL1_DTAH
+#endif /* !ERROR_DEPRECATED */
 
 #endif /* __CORTEX_A53_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index e9788ff..070108d 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -41,17 +41,17 @@
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A57_ACTLR_EL1			S3_1_C15_C2_0
+#define CORTEX_A57_CPUACTLR_EL1				S3_1_C15_C2_0
 
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB	(ULL(1) << 59)
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE	(ULL(1) << 54)
-#define CORTEX_A57_ACTLR_DIS_OVERREAD		(ULL(1) << 52)
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA		(ULL(1) << 49)
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI		(ULL(1) << 44)
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH	(ULL(1) << 38)
-#define CORTEX_A57_ACTLR_DIS_STREAMING		(ULL(3) << 27)
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING	(ULL(3) << 25)
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR	(ULL(1) << 4)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB	(ULL(1) << 59)
+#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE	(ULL(1) << 54)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD		(ULL(1) << 52)
+#define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA		(ULL(1) << 49)
+#define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI		(ULL(1) << 44)
+#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH	(ULL(1) << 38)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING		(ULL(3) << 27)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING	(ULL(3) << 25)
+#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR	(ULL(1) << 4)
 
 /*******************************************************************************
  * L2 Control register specific definitions.
@@ -79,4 +79,22 @@
  ******************************************************************************/
 #define CORTEX_A57_L2MERRSR_EL1			S3_1_C15_C2_3
 
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A57_ACTLR_EL1			CORTEX_A57_CPUACTLR_EL1
+
+#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB	CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
+#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE	CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
+#define CORTEX_A57_ACTLR_DIS_OVERREAD		CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
+#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA		CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
+#define CORTEX_A57_ACTLR_DCC_AS_DCCI		CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
+#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH	CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
+#define CORTEX_A57_ACTLR_DIS_STREAMING		CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING
+#define CORTEX_A57_ACTLR_DIS_L1_STREAMING	CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING
+#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR	CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
+#endif /* !ERROR_DEPRECATED */
+
 #endif /* __CORTEX_A57_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index a30abe8..aed714c 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -29,11 +29,11 @@
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A72_ACTLR_EL1				S3_1_C15_C2_0
+#define CORTEX_A72_CPUACTLR_EL1					S3_1_C15_C2_0
 
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			(ULL(1) << 49)
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI			(ULL(1) << 44)
+#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
+#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA			(ULL(1) << 49)
+#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI			(ULL(1) << 44)
 
 /*******************************************************************************
  * L2 Control register specific definitions.
@@ -52,4 +52,16 @@
  ******************************************************************************/
 #define CORTEX_A72_L2MERRSR_EL1				S3_1_C15_C2_3
 
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A72_ACTLR				CORTEX_A72_CPUACTLR_EL1
+
+#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
+#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA
+#define CORTEX_A72_ACTLR_DCC_AS_DCCI			CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI
+#endif /* !ERROR_DEPRECATED */
+
 #endif /* __CORTEX_A72_H__ */