commit 4198e751f45bfb24d9768312fff6666e156b6b4a
author Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Mon Jul 12 19:14:11 2021 +0900
committer Marek Vasut <marek.vasut+renesas@gmail.com> Sun Sep 12 01:13:48 2021 +0200
tree 4e7b94aa659ab0a279eb278b5f5d55264cbde221
parent c2dfd8e09304d782723fa063e9b1a611d3019ebb

feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR

Modified the operation register to clearing the state bit of
the SYSCISR register from SYSCISR to SYSCISCR.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I9a0820b6414425fa2f4197f60852137827414a4d

drivers/renesas/common/pwrc/pwrc.c

diff --git a/drivers/renesas/common/pwrc/pwrc.c b/drivers/renesas/common/pwrc/pwrc.c
index d29a026..4ebf049 100644
--- a/drivers/renesas/common/pwrc/pwrc.c
+++ b/drivers/renesas/common/pwrc/pwrc.c
@@ -230,7 +230,7 @@
 
 	while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0)
 		;
-	mmio_write_32(RCAR_SYSCISR, sysc_reg_bit);
+	mmio_write_32(RCAR_SYSCISCR, sysc_reg_bit);
 
 	if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) ||
 	    lsi_product == PRR_PRODUCT_H3 ||