stm32mp1: save boot information in backup registers
This will be used by BL33 to get boot device and instance.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 6128c5e..125d2cc 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -19,6 +19,7 @@
#include <stm32mp1_clk.h>
#include <stm32mp1_dt.h>
#include <stm32mp1_private.h>
+#include <stm32mp1_context.h>
#include <stm32mp1_pwr.h>
#include <stm32mp1_rcc.h>
#include <string.h>
@@ -37,6 +38,9 @@
void bl2_el3_plat_arch_setup(void)
{
+ boot_api_context_t *boot_context =
+ (boot_api_context_t *)stm32mp1_get_boot_ctx_address();
+
/*
* Disable the backup domain write protection.
* The protection is enable at each reset by hardware
@@ -90,5 +94,11 @@
panic();
}
+ if (stm32_save_boot_interface(boot_context->boot_interface_selected,
+ boot_context->boot_interface_instance) !=
+ 0) {
+ ERROR("Cannot save boot interface\n");
+ }
+
stm32mp1_io_setup();
}
diff --git a/plat/st/stm32mp1/include/stm32mp1_context.h b/plat/st/stm32mp1/include/stm32mp1_context.h
new file mode 100644
index 0000000..fd08afc
--- /dev/null
+++ b/plat/st/stm32mp1/include/stm32mp1_context.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __STM32MP1_CONTEXT_H__
+#define __STM32MP1_CONTEXT_H__
+
+#include <stdint.h>
+
+int stm32_save_boot_interface(uint32_t interface, uint32_t instance);
+
+#endif /* __STM32MP1_CONTEXT_H__ */
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 46b7fbd..9c97f72 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -43,6 +43,7 @@
drivers/st/clk/stm32mp1_clkfunc.c \
drivers/st/gpio/stm32_gpio.c \
drivers/st/reset/stm32mp1_reset.c \
+ plat/st/stm32mp1/stm32mp1_context.c \
plat/st/stm32mp1/stm32mp1_dt.c \
plat/st/stm32mp1/stm32mp1_helper.S
diff --git a/plat/st/stm32mp1/stm32mp1_context.c b/plat/st/stm32mp1/stm32mp1_context.c
new file mode 100644
index 0000000..245fd17
--- /dev/null
+++ b/plat/st/stm32mp1/stm32mp1_context.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <errno.h>
+#include <mmio.h>
+#include <platform_def.h>
+#include <stm32mp1_clk.h>
+#include <stm32mp1_context.h>
+
+#define TAMP_BOOT_ITF_BACKUP_REG_ID U(20)
+#define TAMP_BOOT_ITF_MASK U(0x0000FF00)
+#define TAMP_BOOT_ITF_SHIFT 8
+
+int stm32_save_boot_interface(uint32_t interface, uint32_t instance)
+{
+ uint32_t tamp_clk_off = 0;
+ uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_ITF_BACKUP_REG_ID);
+
+ if (!stm32mp1_clk_is_enabled(RTCAPB)) {
+ tamp_clk_off = 1;
+ if (stm32mp1_clk_enable(RTCAPB) != 0) {
+ return -EINVAL;
+ }
+ }
+
+ mmio_clrsetbits_32(bkpr_itf_idx,
+ TAMP_BOOT_ITF_MASK,
+ ((interface << 4) | (instance & 0xFU)) <<
+ TAMP_BOOT_ITF_SHIFT);
+
+ if (tamp_clk_off != 0U) {
+ if (stm32mp1_clk_disable(RTCAPB) != 0) {
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 0b46bc5..5ff509c 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -158,6 +158,19 @@
#define STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/
/*******************************************************************************
+ * STM32MP1 TAMP
+ ******************************************************************************/
+#define TAMP_BASE U(0x5C00A000)
+#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
+
+#if !(defined(__LINKER__) || defined(__ASSEMBLY__))
+static inline uint32_t tamp_bkpr(uint32_t idx)
+{
+ return TAMP_BKP_REGISTER_BASE + (idx << 2);
+}
+#endif
+
+/*******************************************************************************
* STM32MP1 DDRCTRL
******************************************************************************/
#define DDRCTRL_BASE U(0x5A003000)