Merge "debugfs: add 9p device interface" into integration
diff --git a/Makefile b/Makefile
index 7cee8e0..073c2ed 100644
--- a/Makefile
+++ b/Makefile
@@ -257,7 +257,6 @@
# Additional warnings
# Level 1
WARNING1 := -Wextra
-WARNING1 += -Wmissing-declarations
WARNING1 += -Wmissing-format-attribute
WARNING1 += -Wmissing-prototypes
WARNING1 += -Wold-style-definition
@@ -271,7 +270,6 @@
WARNING3 += -Wcast-qual
WARNING3 += -Wconversion
WARNING3 += -Wpacked
-WARNING3 += -Wpadded
WARNING3 += -Wpointer-arith
WARNING3 += -Wredundant-decls
WARNING3 += -Wswitch-default
@@ -722,7 +720,6 @@
$(eval $(call assert_boolean,ENABLE_PSCI_STAT))
$(eval $(call assert_boolean,ENABLE_RUNTIME_INSTRUMENTATION))
$(eval $(call assert_boolean,ENABLE_SPE_FOR_LOWER_ELS))
-$(eval $(call assert_boolean,ENABLE_SPM))
$(eval $(call assert_boolean,ENABLE_SVE_FOR_NS))
$(eval $(call assert_boolean,ERROR_DEPRECATED))
$(eval $(call assert_boolean,FAULT_INJECTION_SUPPORT))
@@ -788,7 +785,6 @@
$(eval $(call add_define,ENABLE_PSCI_STAT))
$(eval $(call add_define,ENABLE_RUNTIME_INSTRUMENTATION))
$(eval $(call add_define,ENABLE_SPE_FOR_LOWER_ELS))
-$(eval $(call add_define,ENABLE_SPM))
$(eval $(call add_define,ENABLE_SVE_FOR_NS))
$(eval $(call add_define,ERROR_DEPRECATED))
$(eval $(call add_define,FAULT_INJECTION_SUPPORT))
diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index 855add3..00f2718 100644
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -30,7 +30,8 @@
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=bl1_exceptions
+ _exception_vectors=bl1_exceptions \
+ _pie_fixup_size=0
/* --------------------------------------------------------------------
* Perform BL1 setup
diff --git a/bl2/aarch64/bl2_el3_entrypoint.S b/bl2/aarch64/bl2_el3_entrypoint.S
index 6fe2dd9..f97121e 100644
--- a/bl2/aarch64/bl2_el3_entrypoint.S
+++ b/bl2/aarch64/bl2_el3_entrypoint.S
@@ -26,7 +26,8 @@
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=bl2_el3_exceptions
+ _exception_vectors=bl2_el3_exceptions \
+ _pie_fixup_size=0
/* ---------------------------------------------
* Restore parameters of boot rom
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 1ad26e4..665a05e 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -9,7 +9,7 @@
#include <arch.h>
#include <common/bl_common.h>
#include <el3_common_macros.S>
-#include <lib/pmf/pmf_asm_macros.S>
+#include <lib/pmf/aarch64/pmf_asm_macros.S>
#include <lib/runtime_instr.h>
#include <lib/xlat_tables/xlat_mmu_helpers.h>
@@ -32,17 +32,6 @@
mov x22, x2
mov x23, x3
- /* --------------------------------------------------------------------
- * If PIE is enabled, fixup the Global descriptor Table and dynamic
- * relocations
- * --------------------------------------------------------------------
- */
-#if ENABLE_PIE
- mov_imm x0, BL31_BASE
- mov_imm x1, BL31_LIMIT
- bl fixup_gdt_reloc
-#endif /* ENABLE_PIE */
-
#if !RESET_TO_BL31
/* ---------------------------------------------------------------------
* For !RESET_TO_BL31 systems, only the primary CPU ever reaches
@@ -59,7 +48,8 @@
_secondary_cold_boot=0 \
_init_memory=0 \
_init_c_runtime=1 \
- _exception_vectors=runtime_exceptions
+ _exception_vectors=runtime_exceptions \
+ _pie_fixup_size=BL31_LIMIT - BL31_BASE
#else
/* ---------------------------------------------------------------------
@@ -74,7 +64,8 @@
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=runtime_exceptions
+ _exception_vectors=runtime_exceptions \
+ _pie_fixup_size=BL31_LIMIT - BL31_BASE
/* ---------------------------------------------------------------------
* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
@@ -174,7 +165,8 @@
_secondary_cold_boot=0 \
_init_memory=0 \
_init_c_runtime=0 \
- _exception_vectors=runtime_exceptions
+ _exception_vectors=runtime_exceptions \
+ _pie_fixup_size=0
/*
* We're about to enable MMU and participate in PSCI state coordination.
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index 3cc4d56..1d28d5e 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -102,9 +102,11 @@
/* Setup exception class and syndrome arguments for platform handler */
mov x0, #ERROR_EA_SYNC
mrs x1, esr_el3
- adr x30, el3_exit
- b delegate_sync_ea
+ bl delegate_sync_ea
+ /* el3_exit assumes SP_EL0 on entry */
+ msr spsel, #MODE_SP_EL0
+ b el3_exit
2:
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
@@ -146,8 +148,11 @@
/* Setup exception class and syndrome arguments for platform handler */
mov x0, #ERROR_EA_ASYNC
mrs x1, esr_el3
- adr x30, el3_exit
- b delegate_async_ea
+ bl delegate_async_ea
+
+ /* el3_exit assumes SP_EL0 on entry */
+ msr spsel, #MODE_SP_EL0
+ b el3_exit
endfunc enter_lower_el_async_ea
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 708ee32..a598e59 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -142,7 +142,7 @@
ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
"cpu_ops not defined for this platform.")
-#if ENABLE_SPM
+#if SPM_MM
#ifndef SPM_SHIM_EXCEPTIONS_VMA
#define SPM_SHIM_EXCEPTIONS_VMA RAM
#endif
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 85d471c..58909e8 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -5,22 +5,17 @@
#
################################################################################
-# Include SPM Makefile
+# Include Makefile for the SPM-MM implementation
################################################################################
-ifeq (${ENABLE_SPM},1)
- ifeq (${SPM_MM},1)
- ifeq (${EL3_EXCEPTION_HANDLING},0)
- $(error EL3_EXCEPTION_HANDLING must be 1 for SPM support)
- endif
- $(info Including makefile of SPM based on MM)
- include services/std_svc/spm_mm/spm.mk
+ifeq (${SPM_MM},1)
+ ifeq (${EL3_EXCEPTION_HANDLING},0)
+ $(error EL3_EXCEPTION_HANDLING must be 1 for SPM-MM support)
else
- $(info Including SPM makefile)
- include services/std_svc/spm/spm.mk
+ $(info Including SPM Management Mode (MM) makefile)
+ include services/std_svc/spm_mm/spm_mm.mk
endif
endif
-
include lib/psci/psci_lib.mk
BL31_SOURCES += bl31/bl31_main.c \
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S
index 0a68475..f3a1e44 100644
--- a/bl32/sp_min/aarch32/entrypoint.S
+++ b/bl32/sp_min/aarch32/entrypoint.S
@@ -10,6 +10,9 @@
#include <common/runtime_svc.h>
#include <context.h>
#include <el3_common_macros.S>
+#include <lib/el3_runtime/cpu_data.h>
+#include <lib/pmf/aarch32/pmf_asm_macros.S>
+#include <lib/runtime_instr.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <smccc_helpers.h>
#include <smccc_macros.S>
@@ -164,6 +167,20 @@
/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
str lr, [sp, #SMC_CTX_LR_MON]
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ /*
+ * Read the timestamp value and store it on top of the C runtime stack.
+ * The value will be saved to the per-cpu data once the C stack is
+ * available, as a valid stack is needed to call _cpu_data()
+ */
+ strd r0, r1, [sp, #SMC_CTX_GPREG_R0]
+ ldcopr16 r0, r1, CNTPCT_64
+ ldr lr, [sp, #SMC_CTX_SP_MON]
+ strd r0, r1, [lr, #-8]!
+ str lr, [sp, #SMC_CTX_SP_MON]
+ ldrd r0, r1, [sp, #SMC_CTX_GPREG_R0]
+#endif
+
smccc_save_gp_mode_regs
clrex_on_monitor_entry
@@ -175,6 +192,23 @@
mov r2, sp /* handle */
ldr sp, [r2, #SMC_CTX_SP_MON]
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ /* Save handle to a callee saved register */
+ mov r6, r2
+
+ /*
+ * Restore the timestamp value and store it in per-cpu data. The value
+ * will be extracted from per-cpu data by the C level SMC handler and
+ * saved to the PMF timestamp region.
+ */
+ ldrd r4, r5, [sp], #8
+ bl _cpu_data
+ strd r4, r5, [r0, #CPU_DATA_PMF_TS0_OFFSET]
+
+ /* Restore handle */
+ mov r2, r6
+#endif
+
ldr r0, [r2, #SMC_CTX_SCR]
and r3, r0, #SCR_NS_BIT /* flags */
@@ -239,6 +273,16 @@
* The Warm boot entrypoint for SP_MIN.
*/
func sp_min_warm_entrypoint
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ /*
+ * This timestamp update happens with cache off. The next
+ * timestamp collection will need to do cache maintenance prior
+ * to timestamp update.
+ */
+ pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR
+ ldcopr16 r2, r3, CNTPCT_64
+ strd r2, r3, [r0]
+#endif
/*
* On the warm boot path, most of the EL3 initialisations performed by
* 'el3_entrypoint_common' must be skipped:
@@ -295,6 +339,30 @@
bl smc_get_next_ctx
/* r0 points to `smc_ctx_t` */
/* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
+
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ /* Save smc_ctx_t */
+ mov r5, r0
+
+ pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI
+ mov r4, r0
+
+ /*
+ * Invalidate before updating timestamp to ensure previous timestamp
+ * updates on the same cache line with caches disabled are properly
+ * seen by the same core. Without the cache invalidate, the core might
+ * write into a stale cache line.
+ */
+ mov r1, #PMF_TS_SIZE
+ bl inv_dcache_range
+
+ ldcopr16 r0, r1, CNTPCT_64
+ strd r0, r1, [r4]
+
+ /* Restore smc_ctx_t */
+ mov r0, r5
+#endif
+
b sp_min_exit
endfunc sp_min_warm_entrypoint
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S
index 4559903..6997a7f 100644
--- a/bl32/sp_min/sp_min.ld.S
+++ b/bl32/sp_min/sp_min.ld.S
@@ -55,6 +55,14 @@
KEEP(*(rt_svc_descs))
__RT_SVC_DESCS_END__ = .;
+#if ENABLE_PMF
+ /* Ensure 4-byte alignment for descriptors and ensure inclusion */
+ . = ALIGN(4);
+ __PMF_SVC_DESCS_START__ = .;
+ KEEP(*(pmf_svc_descs))
+ __PMF_SVC_DESCS_END__ = .;
+#endif /* ENABLE_PMF */
+
/*
* Ensure 4-byte alignment for cpu_ops so that its fields are also
* aligned. Also ensure cpu_ops inclusion.
diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c
index f39e33b..f050160 100644
--- a/bl32/sp_min/sp_min_main.c
+++ b/bl32/sp_min/sp_min_main.c
@@ -19,7 +19,9 @@
#include <context.h>
#include <drivers/console.h>
#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/pmf/pmf.h>
#include <lib/psci/psci.h>
+#include <lib/runtime_instr.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
#include <platform_sp_min.h>
@@ -28,6 +30,11 @@
#include "sp_min_private.h"
+#if ENABLE_RUNTIME_INSTRUMENTATION
+PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID,
+ RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE)
+#endif
+
/* Pointers to per-core cpu contexts */
static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT];
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 68f84ea..d9d7f84 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -17,10 +17,18 @@
:G: `sandrine-bailleux-arm`_
:M: Alexei Fedorov <alexei.fedorov@arm.com>
:G: `AlexeiFedorov`_
-:M: Paul Beesley <paul.beesley@arm.com>
-:G: `pbeesley-arm`_
:M: György Szing <gyorgy.szing@arm.com>
:G: `gyuri-szing`_
+:M: Manish Pandey <manish.pandey2@arm.com>
+:G: `manish-pandey-arm`_
+:M: Mark Dykes <mark.dykes@arm.com>
+:G: `mardyk01`_
+:M: Olivier Deprez <olivier.deprez@arm.com>
+:G: `odeprez`_
+:M: Bipin Ravi <bipin.ravi@arm.com>
+:G: `bipinravi-arm`_
+:M: Joanna Farley <joanna.farley@arm.com>
+:G: `joannafarley-arm`_
Allwinner ARMv8 platform port
-----------------------------
@@ -300,7 +308,6 @@
.. _mtk09422: https://github.com/mtk09422
.. _niej: https://github.com/niej
.. _npoushin: https://github.com/npoushin
-.. _pbeesley-arm: https://github.com/pbeesley-arm
.. _qoriq-open-source: https://github.com/qoriq-open-source
.. _remi-triplefault: https://github.com/repk
.. _rockchip-linux: https://github.com/rockchip-linux
@@ -314,3 +321,8 @@
.. _TonyXie06: https://github.com/TonyXie06
.. _vwadekar: https://github.com/vwadekar
.. _Yann-lms: https://github.com/Yann-lms
+.. _manish-pandey-arm: https://github.com/manish-pandey-arm
+.. _mardyk01: https://github.com/mardyk01
+.. _odeprez: https://github.com/odeprez
+.. _bipinravi-arm: https://github.com/bipinravi-arm
+.. _joannafarley-arm: https://github.com/joannafarley-arm
diff --git a/docs/components/secure-partition-manager-design.rst b/docs/components/secure-partition-manager-design.rst
index de0792d..9aba954 100644
--- a/docs/components/secure-partition-manager-design.rst
+++ b/docs/components/secure-partition-manager-design.rst
@@ -160,7 +160,7 @@
Partition.
- ``plat_get_secure_partition_boot_info()`` returns a
- ``secure_partition_boot_info_t`` struct that is populated by the platform
+ ``spm_mm_boot_info_t`` struct that is populated by the platform
with information about the memory map of the Secure Partition.
For an example of all the changes in context, you may refer to commit
@@ -308,8 +308,8 @@
Miscellaneous interfaces
------------------------
-``SPM_VERSION_AARCH32``
-^^^^^^^^^^^^^^^^^^^^^^^
+``SPM_MM_VERSION_AARCH32``
+^^^^^^^^^^^^^^^^^^^^^^^^^^
- Description
@@ -369,7 +369,7 @@
The SPM is responsible for initialising the architectural execution context to
enable initialisation of a service in S-EL0. The responsibilities of the SPM are
listed below. At the end of initialisation, the partition issues a
-``SP_EVENT_COMPLETE_AARCH64`` call (described later) to signal readiness for
+``MM_SP_EVENT_COMPLETE_AARCH64`` call (described later) to signal readiness for
handling requests for services implemented by the Secure Partition. The
initialisation event is executed as a Fast Call.
@@ -488,12 +488,12 @@
The SPM receives requests for Secure Partition services through a synchronous
invocation (i.e. a SMC from the Non-secure world). These requests are delegated
to the partition by programming a return from the last
-``SP_EVENT_COMPLETE_AARCH64`` call received from the partition. The last call
+``MM_SP_EVENT_COMPLETE_AARCH64`` call received from the partition. The last call
was made to signal either completion of Secure Partition initialisation or
completion of a partition service request.
-``SP_EVENT_COMPLETE_AARCH64``
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+``MM_SP_EVENT_COMPLETE_AARCH64``
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
- Description
@@ -569,7 +569,7 @@
- Caller responsibilities
- A Secure Partition must only call ``SP_EVENT_COMPLETE_AARCH64`` to signal
+ A Secure Partition must only call ``MM_SP_EVENT_COMPLETE_AARCH64`` to signal
completion of a request that was delegated to it by the SPM.
- Callee responsibilities
@@ -613,18 +613,19 @@
In this case, the Secure Partition needs a way to change the access permissions
of its memory regions. The SPM provides this feature through the
-``SP_MEMORY_ATTRIBUTES_SET_AARCH64`` SVC interface. This interface is available
-to the Secure Partition during a specific time window: from the first entry into
-the Secure Partition up to the first ``SP_EVENT_COMPLETE`` call that signals the
-Secure Partition has finished its initialisation. Once the initialisation is
-complete, the SPM does not allow changes to the memory attributes.
+``MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64`` SVC interface. This interface is
+available to the Secure Partition during a specific time window: from the first
+entry into the Secure Partition up to the first ``SP_EVENT_COMPLETE`` call that
+signals the Secure Partition has finished its initialisation. Once the
+initialisation is complete, the SPM does not allow changes to the memory
+attributes.
This section describes the standard SVC interface that is implemented by the SPM
to determine and change permission attributes of memory regions that belong to a
Secure Partition.
-``SP_MEMORY_ATTRIBUTES_GET_AARCH64``
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+``MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64``
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
- Description
@@ -673,7 +674,7 @@
- ``NOT_SUPPORTED`` : The SPM does not support retrieval of attributes of
any memory page that is accessible by the Secure Partition, or the
function was called from the Non-secure world. Also returned if it is
- used after ``SP_EVENT_COMPLETE_AARCH64``.
+ used after ``MM_SP_EVENT_COMPLETE_AARCH64``.
See `Error Codes`_ for integer values that are associated with each return
code.
@@ -696,8 +697,8 @@
The SPM must not return the memory access controls for a page of memory that
is not accessible from a Secure Partition.
-``SP_MEMORY_ATTRIBUTES_SET_AARCH64``
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+``MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64``
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
- Description
@@ -762,7 +763,7 @@
- ``NOT_SUPPORTED``: The SPM does not permit change of attributes of any
memory region that is accessible by the Secure Partition. Function was
called from the Non-secure world. Also returned if it is used after
- ``SP_EVENT_COMPLETE_AARCH64``.
+ ``MM_SP_EVENT_COMPLETE_AARCH64``.
See `Error Codes`_ for integer values that are associated with each return
code.
@@ -776,8 +777,8 @@
currently supported.
This function is only available at boot time. This interface is revoked after
- the Secure Partition sends the first ``SP_EVENT_COMPLETE_AARCH64`` to signal
- that it is initialised and ready to receive run-time requests.
+ the Secure Partition sends the first ``MM_SP_EVENT_COMPLETE_AARCH64`` to
+ signal that it is initialised and ready to receive run-time requests.
- Caller responsibilities
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 051586b..87429f2 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -196,7 +196,7 @@
builds, but this behaviour can be overridden in each platform's Makefile or
in the build command line.
- - ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
+- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
support in GCC for TF-A. This option is currently only supported for
AArch64. Default is 0.
@@ -235,10 +235,6 @@
The default is 1 but is automatically disabled when the target architecture
is AArch32.
-- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
- Refer to :ref:`Secure Partition Manager` for more details about
- this feature. Default is 0.
-
- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
(SVE) for the Non-secure world only. SVE is an optional architectural feature
for AArch64. Note that when SVE is enabled for the Non-secure world, access
@@ -354,6 +350,21 @@
compliant and is retained only for compatibility. The default value of this
flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
+- ``KEY_SIZE``: This build flag enables the user to select the key size for
+ the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
+ depend on the chosen algorithm and the cryptographic module.
+
+ +-----------+------------------------------------+
+ | KEY_ALG | Possible key sizes |
+ +===========+====================================+
+ | rsa | 1024 , 2048 (default), 3072, 4096* |
+ +-----------+------------------------------------+
+ | ecdsa | unavailable |
+ +-----------+------------------------------------+
+
+ * Only 2048 bits size is available with CryptoCell 712 SBROM release 1.
+ Only 3072 bits size is available with CryptoCell 712 SBROM release 2.
+
- ``HASH_ALG``: This build flag enables the user to select the secure hash
algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
The default value of this flag is ``sha256``.
@@ -492,6 +503,9 @@
firmware images have been loaded in memory, and the MMU and caches are
turned off. Refer to the "Debugging options" section for more details.
+- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
+ Partition Manager (SPM) implementation. The default value is ``0``.
+
- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
secure interrupts (caught through the FIQ line). Platforms can enable
this directive if they need to handle such interruption. When enabled,
diff --git a/docs/plat/nvidia-tegra.rst b/docs/plat/nvidia-tegra.rst
index bc9e35b..02ff38b 100644
--- a/docs/plat/nvidia-tegra.rst
+++ b/docs/plat/nvidia-tegra.rst
@@ -1,6 +1,17 @@
NVIDIA Tegra
============
+- .. rubric:: T194
+ :name: t194
+
+T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
+configuration. The Carmel cores support the ARM Architecture version 8.2,
+executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel
+processors are organized as four dual-core clusters, where each cluster has
+a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects
+these processor complexes and allows heterogeneous multi-processing with all
+eight cores if required.
+
- .. rubric:: T186
:name: t186
@@ -78,9 +89,10 @@
These are the supported Trusted OS' by Tegra platforms.
-Tegra132: TLK
-Tegra210: TLK and Trusty
-Tegra186: Trusty
+- Tegra132: TLK
+- Tegra210: TLK and Trusty
+- Tegra186: Trusty
+- Tegra194: Trusty
Scatter files
-------------
@@ -98,7 +110,7 @@
.. code:: shell
CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
- TARGET_SOC=<target-soc e.g. t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd>
+ TARGET_SOC=<target-soc e.g. t194|t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd>
bl31
Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>``
diff --git a/docs/process/security-hardening.rst b/docs/process/security-hardening.rst
index 4967871..a18a792 100644
--- a/docs/process/security-hardening.rst
+++ b/docs/process/security-hardening.rst
@@ -30,9 +30,8 @@
- W=1
- Adds ``Wextra``, ``Wmissing-declarations``, ``Wmissing-format-attribute``,
- ``Wmissing-prototypes``, ``Wold-style-definition`` and
- ``Wunused-const-variable``.
+ Adds ``Wextra``, ``Wmissing-format-attribute``, ``Wmissing-prototypes``,
+ ``Wold-style-definition`` and ``Wunused-const-variable``.
- W=2
@@ -42,7 +41,7 @@
- W=3
Adds ``Wbad-function-cast``, ``Wcast-qual``, ``Wconversion``, ``Wpacked``,
- ``Wpadded``, ``Wpointer-arith``, ``Wredundant-decls`` and
+ ``Wpointer-arith``, ``Wredundant-decls`` and
``Wswitch-default``.
Refer to the GCC or Clang documentation for more information on the individual
diff --git a/drivers/allwinner/axp/axp803.c b/drivers/allwinner/axp/axp803.c
new file mode 100644
index 0000000..53b11c1
--- /dev/null
+++ b/drivers/allwinner/axp/axp803.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/allwinner/axp.h>
+
+const uint8_t axp_chip_id = AXP803_CHIP_ID;
+const char *const axp_compatible = "x-powers,axp803";
+
+const struct axp_regulator axp_regulators[] = {
+ {"dcdc1", 1600, 3400, 100, NA, 0x20, 0x10, 0},
+ {"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4},
+ {"dcdc6", 600, 1520, 10, 50, 0x25, 0x10, 5},
+ {"dldo1", 700, 3300, 100, NA, 0x15, 0x12, 3},
+ {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4},
+ {"dldo3", 700, 3300, 100, NA, 0x17, 0x12, 5},
+ {"dldo4", 700, 3300, 100, NA, 0x18, 0x12, 6},
+ {"fldo1", 700, 1450, 50, NA, 0x1c, 0x13, 2},
+ {}
+};
diff --git a/drivers/allwinner/axp/axp805.c b/drivers/allwinner/axp/axp805.c
new file mode 100644
index 0000000..8d029c0
--- /dev/null
+++ b/drivers/allwinner/axp/axp805.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/allwinner/axp.h>
+
+const uint8_t axp_chip_id = AXP805_CHIP_ID;
+const char *const axp_compatible = "x-powers,axp805";
+
+/*
+ * The "dcdcd" split changes the step size by a factor of 5, not 2;
+ * disallow values above the split to maintain accuracy.
+ */
+const struct axp_regulator axp_regulators[] = {
+ {"dcdca", 600, 1520, 10, 50, 0x12, 0x10, 0},
+ {"dcdcb", 1000, 2550, 50, NA, 0x13, 0x10, 1},
+ {"dcdcc", 600, 1520, 10, 50, 0x14, 0x10, 2},
+ {"dcdcd", 600, 1500, 20, NA, 0x15, 0x10, 3},
+ {"dcdce", 1100, 3400, 100, NA, 0x16, 0x10, 4},
+ {"aldo1", 700, 3300, 100, NA, 0x17, 0x10, 5},
+ {"aldo2", 700, 3300, 100, NA, 0x18, 0x10, 6},
+ {"aldo3", 700, 3300, 100, NA, 0x19, 0x10, 7},
+ {"bldo1", 700, 1900, 100, NA, 0x20, 0x11, 0},
+ {"bldo2", 700, 1900, 100, NA, 0x21, 0x11, 1},
+ {"bldo3", 700, 1900, 100, NA, 0x22, 0x11, 2},
+ {"bldo4", 700, 1900, 100, NA, 0x23, 0x11, 3},
+ {"cldo1", 700, 3300, 100, NA, 0x24, 0x11, 4},
+ {"cldo2", 700, 4200, 100, 27, 0x25, 0x11, 5},
+ {"cldo3", 700, 3300, 100, NA, 0x26, 0x11, 6},
+ {}
+};
diff --git a/drivers/allwinner/axp/common.c b/drivers/allwinner/axp/common.c
new file mode 100644
index 0000000..13437fe
--- /dev/null
+++ b/drivers/allwinner/axp/common.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <libfdt.h>
+
+#include <common/debug.h>
+#include <drivers/allwinner/axp.h>
+
+int axp_check_id(void)
+{
+ int ret;
+
+ ret = axp_read(0x03);
+ if (ret < 0)
+ return ret;
+
+ ret &= 0xcf;
+ if (ret != axp_chip_id) {
+ ERROR("PMIC: Found unknown PMIC %02x\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask)
+{
+ uint8_t val;
+ int ret;
+
+ ret = axp_read(reg);
+ if (ret < 0)
+ return ret;
+
+ val = (ret & ~clr_mask) | set_mask;
+
+ return axp_write(reg, val);
+}
+
+void axp_power_off(void)
+{
+ /* Set "power disable control" bit */
+ axp_setbits(0x32, BIT(7));
+}
+
+/*
+ * Retrieve the voltage from a given regulator DTB node.
+ * Both the regulator-{min,max}-microvolt properties must be present and
+ * have the same value. Return that value in millivolts.
+ */
+static int fdt_get_regulator_millivolt(const void *fdt, int node)
+{
+ const fdt32_t *prop;
+ uint32_t min_volt;
+
+ prop = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL);
+ if (prop == NULL)
+ return -EINVAL;
+ min_volt = fdt32_to_cpu(*prop);
+
+ prop = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL);
+ if (prop == NULL)
+ return -EINVAL;
+
+ if (fdt32_to_cpu(*prop) != min_volt)
+ return -EINVAL;
+
+ return min_volt / 1000;
+}
+
+static int setup_regulator(const void *fdt, int node,
+ const struct axp_regulator *reg)
+{
+ uint8_t val;
+ int mvolt;
+
+ mvolt = fdt_get_regulator_millivolt(fdt, node);
+ if (mvolt < reg->min_volt || mvolt > reg->max_volt)
+ return -EINVAL;
+
+ val = (mvolt / reg->step) - (reg->min_volt / reg->step);
+ if (val > reg->split)
+ val = ((val - reg->split) / 2) + reg->split;
+
+ axp_write(reg->volt_reg, val);
+ axp_setbits(reg->switch_reg, BIT(reg->switch_bit));
+
+ INFO("PMIC: %s voltage: %d.%03dV\n", reg->dt_name,
+ mvolt / 1000, mvolt % 1000);
+
+ return 0;
+}
+
+static bool should_enable_regulator(const void *fdt, int node)
+{
+ if (fdt_getprop(fdt, node, "phandle", NULL) != NULL)
+ return true;
+ if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL)
+ return true;
+ return false;
+}
+
+void axp_setup_regulators(const void *fdt)
+{
+ int node;
+ bool sw = false;
+
+ if (fdt == NULL)
+ return;
+
+ /* locate the PMIC DT node, bail out if not found */
+ node = fdt_node_offset_by_compatible(fdt, -1, axp_compatible);
+ if (node < 0) {
+ WARN("PMIC: No PMIC DT node, skipping setup\n");
+ return;
+ }
+
+ /* This applies to AXP803 only. */
+ if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) {
+ axp_clrbits(0x8f, BIT(4));
+ axp_setbits(0x30, BIT(2));
+ INFO("PMIC: Enabling DRIVEVBUS\n");
+ }
+
+ /* descend into the "regulators" subnode */
+ node = fdt_subnode_offset(fdt, node, "regulators");
+ if (node < 0) {
+ WARN("PMIC: No regulators DT node, skipping setup\n");
+ return;
+ }
+
+ /* iterate over all regulators to find used ones */
+ fdt_for_each_subnode(node, fdt, node) {
+ const struct axp_regulator *reg;
+ const char *name;
+ int length;
+
+ /* We only care if it's always on or referenced. */
+ if (!should_enable_regulator(fdt, node))
+ continue;
+
+ name = fdt_get_name(fdt, node, &length);
+
+ /* Enable the switch last to avoid overheating. */
+ if (!strncmp(name, "dc1sw", length) ||
+ !strncmp(name, "sw", length)) {
+ sw = true;
+ continue;
+ }
+
+ for (reg = axp_regulators; reg->dt_name; reg++) {
+ if (!strncmp(name, reg->dt_name, length)) {
+ setup_regulator(fdt, node, reg);
+ break;
+ }
+ }
+ }
+
+ /*
+ * On the AXP803, if DLDO2 is enabled after DC1SW, the PMIC overheats
+ * and shuts down. So always enable DC1SW as the very last regulator.
+ */
+ if (sw) {
+ INFO("PMIC: Enabling DC SW\n");
+ if (axp_chip_id == AXP803_CHIP_ID)
+ axp_setbits(0x12, BIT(7));
+ if (axp_chip_id == AXP805_CHIP_ID)
+ axp_setbits(0x11, BIT(7));
+ }
+}
diff --git a/drivers/auth/cryptocell/712/cryptocell_crypto.c b/drivers/auth/cryptocell/712/cryptocell_crypto.c
index 395c550..25eb6bc 100644
--- a/drivers/auth/cryptocell/712/cryptocell_crypto.c
+++ b/drivers/auth/cryptocell/712/cryptocell_crypto.c
@@ -225,7 +225,7 @@
/* Verify the signature */
error = CCSbVerifySignature((uintptr_t)PLAT_CRYPTOCELL_BASE,
(uint32_t *)data_ptr, &pk, &signature,
- data_len, RSA_PSS_2048);
+ data_len, RSA_PSS);
if (error != CC_OK)
return CRYPTO_ERR_SIGNATURE;
diff --git a/drivers/auth/cryptocell/cryptocell_crypto.mk b/drivers/auth/cryptocell/cryptocell_crypto.mk
index d42a2e7..2fc4ddb 100644
--- a/drivers/auth/cryptocell/cryptocell_crypto.mk
+++ b/drivers/auth/cryptocell/cryptocell_crypto.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -12,6 +12,8 @@
# Needs to be set to drive mbed TLS configuration correctly
$(eval $(call add_define,TF_MBEDTLS_KEY_ALG_ID))
+$(eval $(call add_define,KEY_SIZE))
+
# CCSBROM_LIB_PATH must be set to the Cryptocell SBROM library path
ifeq (${CCSBROM_LIB_PATH},)
$(error Error: CCSBROM_LIB_PATH not set)
diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c
index 2e8c412..f6a40a5 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.c
+++ b/drivers/marvell/comphy/phy-comphy-3700.c
@@ -195,6 +195,45 @@
ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode);
}
+/*
+ * This is something like the inverse of the previous function: for given
+ * lane it returns COMPHY_*_MODE.
+ *
+ * It is useful when powering the phy off.
+ *
+ * This function returns COMPHY_USB3_MODE even if the phy was configured
+ * with COMPHY_USB3D_MODE or COMPHY_USB3H_MODE. (The usb3 phy initialization
+ * code does not differentiate between these modes.)
+ * Also it returns COMPHY_SGMII_MODE even if the phy was configures with
+ * COMPHY_HS_SGMII_MODE. (The sgmii phy initialization code does differentiate
+ * between these modes, but it is irrelevant when powering the phy off.)
+ */
+static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index)
+{
+ uint32_t reg;
+
+ reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG);
+ switch (comphy_index) {
+ case COMPHY_LANE0:
+ if ((reg & COMPHY_SELECTOR_USB3_GBE1_SEL_BIT) != 0)
+ return COMPHY_USB3_MODE;
+ else
+ return COMPHY_SGMII_MODE;
+ case COMPHY_LANE1:
+ if ((reg & COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT) != 0)
+ return COMPHY_PCIE_MODE;
+ else
+ return COMPHY_SGMII_MODE;
+ case COMPHY_LANE2:
+ if ((reg & COMPHY_SELECTOR_USB3_PHY_SEL_BIT) != 0)
+ return COMPHY_USB3_MODE;
+ else
+ return COMPHY_SATA_MODE;
+ }
+
+ return COMPHY_UNUSED;
+}
+
/* It is only used for SATA and USB3 on comphy lane2. */
static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data,
uint16_t mask, int mode)
@@ -547,6 +586,23 @@
return ret;
}
+static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index)
+{
+ int ret = 0;
+ uint32_t mask, data, offset;
+
+ debug_enter();
+
+ data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT;
+ mask = 0;
+ offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
+ reg_set(offset, data, mask);
+
+ debug_exit();
+
+ return ret;
+}
+
static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
uint32_t comphy_mode)
{
@@ -721,11 +777,11 @@
udelay(PLL_SET_DELAY_US);
if (comphy_index == COMPHY_LANE2) {
- data = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET;
+ data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET;
mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET,
data);
- addr = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET;
+ addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET;
ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
COMPHY_PLL_TIMEOUT, REG_32BIT);
} else {
@@ -908,7 +964,20 @@
debug_enter();
+ if (!mode) {
+ /*
+ * The user did not specify which mode should be powered off.
+ * In this case we can identify this by reading the phy selector
+ * register.
+ */
+ mode = mvebu_a3700_comphy_get_mode(comphy_index);
+ }
+
switch (mode) {
+ case(COMPHY_SGMII_MODE):
+ case(COMPHY_HS_SGMII_MODE):
+ err = mvebu_a3700_comphy_sgmii_power_off(comphy_index);
+ break;
case (COMPHY_USB3_MODE):
case (COMPHY_USB3H_MODE):
err = mvebu_a3700_comphy_usb3_power_off();
diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts
index 91212e8..fc8783d 100644
--- a/fdts/a5ds.dts
+++ b/fdts/a5ds.dts
@@ -22,29 +22,30 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "psci";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
- enable-method = "psci";
reg = <0>;
+ next-level-cache = <&L2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a5";
- enable-method = "psci";
reg = <1>;
+ next-level-cache = <&L2>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a5";
- enable-method = "psci";
reg = <2>;
+ next-level-cache = <&L2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a5";
- enable-method = "psci";
reg = <3>;
+ next-level-cache = <&L2>;
};
};
@@ -53,6 +54,16 @@
reg = <0x80000000 0x7F000000>;
};
+ L2: cache-controller@1C010000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x1C010000 0x1000>;
+ interrupts = <0 84 4>;
+ cache-level = <2>;
+ cache-unified;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <1 1 1>;
+ };
+
refclk100mhz: refclk100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 3ff2912..1fcd0f9 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -140,6 +140,8 @@
#define ID_AA64PFR0_GIC_MASK ULL(0xf)
#define ID_AA64PFR0_SVE_SHIFT U(32)
#define ID_AA64PFR0_SVE_MASK ULL(0xf)
+#define ID_AA64PFR0_SEL2_SHIFT U(36)
+#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
#define ID_AA64PFR0_MPAM_SHIFT U(40)
#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
#define ID_AA64PFR0_DIT_SHIFT U(48)
@@ -285,6 +287,7 @@
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
#define SCR_ATA_BIT (U(1) << 26)
#define SCR_FIEN_BIT (U(1) << 21)
+#define SCR_EEL2_BIT (U(1) << 18)
#define SCR_API_BIT (U(1) << 17)
#define SCR_APK_BIT (U(1) << 16)
#define SCR_TWE_BIT (U(1) << 13)
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 378e827..b14b7b6 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -232,11 +232,18 @@
*
* _exception_vectors:
* Address of the exception vectors to program in the VBAR_EL3 register.
+ *
+ * _pie_fixup_size:
+ * Size of memory region to fixup Global Descriptor Table (GDT).
+ *
+ * A non-zero value is expected when firmware needs GDT to be fixed-up.
+ *
* -----------------------------------------------------------------------------
*/
.macro el3_entrypoint_common \
_init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
- _init_memory, _init_c_runtime, _exception_vectors
+ _init_memory, _init_c_runtime, _exception_vectors, \
+ _pie_fixup_size
.if \_init_sctlr
/* -------------------------------------------------------------
@@ -283,6 +290,26 @@
do_cold_boot:
.endif /* _warm_boot_mailbox */
+ .if \_pie_fixup_size
+#if ENABLE_PIE
+ /*
+ * ------------------------------------------------------------
+ * If PIE is enabled fixup the Global descriptor Table only
+ * once during primary core cold boot path.
+ *
+ * Compile time base address, required for fixup, is calculated
+ * using "pie_fixup" label present within first page.
+ * ------------------------------------------------------------
+ */
+ pie_fixup:
+ ldr x0, =pie_fixup
+ and x0, x0, #~(PAGE_SIZE - 1)
+ mov_imm x1, \_pie_fixup_size
+ add x1, x1, x0
+ bl fixup_gdt_reloc
+#endif /* ENABLE_PIE */
+ .endif /* _pie_fixup_size */
+
/* ---------------------------------------------------------------------
* Set the exception vectors.
* ---------------------------------------------------------------------
diff --git a/include/drivers/allwinner/axp.h b/include/drivers/allwinner/axp.h
new file mode 100644
index 0000000..9c0035f
--- /dev/null
+++ b/include/drivers/allwinner/axp.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AXP_H
+#define AXP_H
+
+#include <stdint.h>
+
+#define NA 0xff
+
+enum {
+ AXP803_CHIP_ID = 0x41,
+ AXP805_CHIP_ID = 0x40,
+};
+
+struct axp_regulator {
+ const char *dt_name;
+ uint16_t min_volt;
+ uint16_t max_volt;
+ uint16_t step;
+ unsigned char split;
+ unsigned char volt_reg;
+ unsigned char switch_reg;
+ unsigned char switch_bit;
+};
+
+extern const uint8_t axp_chip_id;
+extern const char *const axp_compatible;
+extern const struct axp_regulator axp_regulators[];
+
+/*
+ * Since the PMIC can be connected to multiple bus types,
+ * low-level read/write functions must be provided by the platform
+ */
+int axp_read(uint8_t reg);
+int axp_write(uint8_t reg, uint8_t val);
+int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask);
+#define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0)
+#define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask)
+
+int axp_check_id(void);
+void axp_power_off(void);
+void axp_setup_regulators(const void *fdt);
+
+#endif /* AXP_H */
diff --git a/include/drivers/arm/cryptocell/712/rsa.h b/include/drivers/arm/cryptocell/712/rsa.h
index cd9925b..825214d 100644
--- a/include/drivers/arm/cryptocell/712/rsa.h
+++ b/include/drivers/arm/cryptocell/712/rsa.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,19 +21,21 @@
/************************ Defines ******************************/
-/* the modulus size ion bits */
+/* the modulus size in bits */
+#if (KEY_SIZE == 2048)
#define RSA_MOD_SIZE_IN_BITS 2048UL
+#elif (KEY_SIZE == 3072)
+#define RSA_MOD_SIZE_IN_BITS 3072UL
+#else
+#error Unsupported CryptoCell key size requested
+#endif
+
#define RSA_MOD_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_MOD_SIZE_IN_BITS))
#define RSA_MOD_SIZE_IN_WORDS (CALC_FULL_32BIT_WORDS(RSA_MOD_SIZE_IN_BITS))
#define RSA_MOD_SIZE_IN_256BITS (RSA_MOD_SIZE_IN_WORDS/8)
#define RSA_EXP_SIZE_IN_BITS 17UL
#define RSA_EXP_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_EXP_SIZE_IN_BITS))
-/* size of buffer for Barrett modulus tag NP, used in PKA algorithms */
-#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS 132
-#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS))
-#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS (CALC_FULL_32BIT_WORDS(RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS))
-
/*
* @brief The RSA_CalcNp calculates Np value and saves it into Np_ptr:
*
diff --git a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h
index 68b9ef8..ed1f283 100644
--- a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h
+++ b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,7 +24,14 @@
/***********************/
/*RSA definitions*/
+#if (KEY_SIZE == 2048)
#define SB_RSA_MOD_SIZE_IN_WORDS 64
+#elif (KEY_SIZE == 3072)
+#define SB_RSA_MOD_SIZE_IN_WORDS 96
+#else
+#error Unsupported CryptoCell key size requested
+#endif
+
#define SB_RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS 5
@@ -43,9 +50,12 @@
/********* Supported algorithms definitions ***********/
/*! RSA supported algorithms */
+/* Note: this applies to either 2k or 3k based on CryptoCell SBROM library
+ * version - it means 2k in version 1 and 3k in version 2 (yes, really).
+ */
typedef enum {
- RSA_PSS_2048 = 0x01, /*!< RSA PSS 2048 after hash SHA 256 */
- RSA_PKCS15_2048 = 0x02, /*!< RSA PKX15 */
+ RSA_PSS = 0x01, /*!< RSA PSS after hash SHA 256 */
+ RSA_PKCS15 = 0x02, /*!< RSA PKX15 */
RSA_Last = 0x7FFFFFFF
} CCSbRsaAlg_t;
diff --git a/include/lib/libc/stdint.h b/include/lib/libc/stdint.h
index 80b3e96..818870e 100644
--- a/include/lib/libc/stdint.h
+++ b/include/lib/libc/stdint.h
@@ -72,7 +72,7 @@
#define PTRDIFF_MIN LONG_MIN
#define PTRDIFF_MAX LONG_MAX
-#define SIZE_MAX UINT64_MAX
+#define SIZE_MAX ULONG_MAX
#define INT8_C(x) x
#define INT16_C(x) x
diff --git a/include/lib/pmf/aarch32/pmf_asm_macros.S b/include/lib/pmf/aarch32/pmf_asm_macros.S
new file mode 100644
index 0000000..1dbb408
--- /dev/null
+++ b/include/lib/pmf/aarch32/pmf_asm_macros.S
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMF_ASM_MACROS_S
+#define PMF_ASM_MACROS_S
+
+#define PMF_TS_SIZE 8
+
+ /*
+ * This macro calculates the address of the per-cpu timestamp
+ * for the given service name and local timestamp id.
+ * Clobbers: r0 - r4
+ */
+ .macro pmf_calc_timestamp_addr _name, _tid
+ mov r4, lr
+ bl plat_my_core_pos
+ mov lr, r4
+ ldr r1, =__PERCPU_TIMESTAMP_SIZE__
+ mov r2, #(\_tid * PMF_TS_SIZE)
+ mla r0, r0, r1, r2
+ ldr r1, =pmf_ts_mem_\_name
+ add r0, r0, r1
+ .endm
+
+#endif /* PMF_ASM_MACROS_S */
diff --git a/include/lib/pmf/pmf_asm_macros.S b/include/lib/pmf/aarch64/pmf_asm_macros.S
similarity index 100%
rename from include/lib/pmf/pmf_asm_macros.S
rename to include/lib/pmf/aarch64/pmf_asm_macros.S
diff --git a/include/lib/sprt/sprt_common.h b/include/lib/sprt/sprt_common.h
deleted file mode 100644
index 27d5027..0000000
--- a/include/lib/sprt/sprt_common.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SPRT_COMMON_H
-#define SPRT_COMMON_H
-
-#define SPRT_MAX_MSG_ARGS 6
-
-/*
- * Message types supported.
- */
-#define SPRT_MSG_TYPE_SERVICE_HANDLE_OPEN 1
-#define SPRT_MSG_TYPE_SERVICE_HANDLE_CLOSE 2
-/* TODO: Add other types of SPRT messages. */
-#define SPRT_MSG_TYPE_SERVICE_TUN_REQUEST 10
-
-/*
- * Struct that defines the layout of the fields corresponding to a request in
- * shared memory.
- */
-struct __attribute__((__packed__)) sprt_queue_entry_message {
- uint32_t type; /* Type of message (result of an SPCI call). */
- uint16_t client_id; /* SPCI client ID */
- uint16_t service_handle;/* SPCI service handle */
- uint32_t session_id; /* Optional SPCI session ID */
- uint32_t token; /* SPCI request token */
- uint64_t args[SPRT_MAX_MSG_ARGS];
-};
-
-#define SPRT_QUEUE_ENTRY_MSG_SIZE (sizeof(struct sprt_queue_entry_message))
-
-#define SPRT_QUEUE_NUM_BLOCKING 0
-#define SPRT_QUEUE_NUM_NON_BLOCKING 1
-
-#endif /* SPRT_COMMON_H */
diff --git a/include/lib/sprt/sprt_host.h b/include/lib/sprt/sprt_host.h
deleted file mode 100644
index f888141..0000000
--- a/include/lib/sprt/sprt_host.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef SPRT_HOST_H
-#define SPRT_HOST_H
-
-#include <stddef.h>
-
-#include "sprt_common.h"
-
-/*
- * Initialize the specified buffer to be used by SPM.
- */
-void sprt_initialize_queues(void *buffer_base, size_t buffer_size);
-
-/*
- * Push a message to the queue number `queue_num` in a buffer that has been
- * initialized by `sprt_initialize_queues`.
- */
-int sprt_push_message(void *buffer_base,
- const struct sprt_queue_entry_message *message,
- int queue_num);
-
-#endif /* SPRT_HOST_H */
diff --git a/include/lib/utils.h b/include/lib/utils.h
index cdb125c..17ee936 100644
--- a/include/lib/utils.h
+++ b/include/lib/utils.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -79,13 +79,11 @@
* which is constant and does not depend on the execute address of the binary.
*/
#define DEFINE_LOAD_SYM_ADDR(_name) \
-static inline u_register_t load_addr_## _name(void) \
-{ \
- u_register_t v; \
- /* Create a void reference to silence compiler */ \
- (void) _name; \
- __asm__ volatile ("ldr %0, =" #_name : "=r" (v)); \
- return v; \
+static inline u_register_t load_addr_## _name(void) \
+{ \
+ u_register_t v; \
+ __asm__ volatile ("ldr %0, =" #_name : "=r" (v) : "X" (#_name));\
+ return v; \
}
/* Helper to invoke the function defined by DEFINE_LOAD_SYM_ADDR() */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 941190f..72e2e8e 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -457,7 +457,7 @@
* Trusted DRAM (if available) or the DRAM region secured by the TrustZone
* controller.
*/
-# if ENABLE_SPM
+# if SPM_MM
# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
@@ -500,9 +500,9 @@
* SPD and no SPM, as they are the only ones that can be used as BL32.
*/
#if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME
-# if defined(SPD_none) && !ENABLE_SPM
+# if defined(SPD_none) && !SPM_MM
# undef BL32_BASE
-# endif /* defined(SPD_none) && !ENABLE_SPM */
+# endif /* defined(SPD_none) && !SPM_MM*/
#endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */
/*******************************************************************************
diff --git a/include/plat/arm/common/arm_spm_def.h b/include/plat/arm/common/arm_spm_def.h
index 16c806b..c43583d 100644
--- a/include/plat/arm/common/arm_spm_def.h
+++ b/include/plat/arm/common/arm_spm_def.h
@@ -10,31 +10,6 @@
#include <lib/xlat_tables/xlat_tables_defs.h>
/*
- * Reserve 4 MiB for binaries of Secure Partitions and Resource Description
- * blobs.
- */
-#define PLAT_SP_PACKAGE_BASE BL32_BASE
-#define PLAT_SP_PACKAGE_SIZE ULL(0x400000)
-
-#define PLAT_MAP_SP_PACKAGE_MEM_RO MAP_REGION_FLAT( \
- PLAT_SP_PACKAGE_BASE, \
- PLAT_SP_PACKAGE_SIZE, \
- MT_MEMORY | MT_RO | MT_SECURE)
-#define PLAT_MAP_SP_PACKAGE_MEM_RW MAP_REGION_FLAT( \
- PLAT_SP_PACKAGE_BASE, \
- PLAT_SP_PACKAGE_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
-/*
- * The rest of the memory reserved for BL32 is free for SPM to use it as memory
- * pool to allocate memory regions requested in the resource description.
- */
-#define PLAT_SPM_HEAP_BASE (PLAT_SP_PACKAGE_BASE + PLAT_SP_PACKAGE_SIZE)
-#define PLAT_SPM_HEAP_SIZE (BL32_LIMIT - BL32_BASE - PLAT_SP_PACKAGE_SIZE)
-
-#if SPM_MM
-
-/*
* If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the
* region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition
* at the base of DRAM.
@@ -121,23 +96,8 @@
/* Total number of memory regions with distinct properties */
#define ARM_SP_IMAGE_NUM_MEM_REGIONS 6
-#endif /* SPM_MM */
-
/* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */
#define PLAT_SPM_COOKIE_0 ULL(0)
#define PLAT_SPM_COOKIE_1 ULL(0)
-/*
- * Max number of elements supported by SPM in this platform. The defines below
- * are used to allocate memory at compile time for different arrays in SPM.
- */
-#define PLAT_SPM_MAX_PARTITIONS U(2)
-
-#define PLAT_SPM_MEM_REGIONS_MAX U(80)
-#define PLAT_SPM_NOTIFICATIONS_MAX U(30)
-#define PLAT_SPM_SERVICES_MAX U(30)
-
-#define PLAT_SPCI_HANDLES_MAX_NUM U(20)
-#define PLAT_SPM_RESPONSES_MAX U(30)
-
#endif /* ARM_SPM_DEF_H */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index c00a041..02feec7 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -38,7 +38,7 @@
* - Region 1 with secure access only;
* - the remaining DRAM regions access from the given Non-Secure masters.
******************************************************************************/
-#if ENABLE_SPM && SPM_MM
+#if SPM_MM
#define ARM_TZC_REGIONS_DEF \
{ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
TZC_REGION_S_RDWR, 0}, \
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index eeae621..9efb2fd 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -22,7 +22,7 @@
struct bl_load_info;
struct bl_params;
struct mmap_region;
-struct secure_partition_boot_info;
+struct spm_mm_boot_info;
struct sp_res_desc;
/*******************************************************************************
@@ -267,7 +267,7 @@
* Secure Partitions functions
******************************************************************************/
const struct mmap_region *plat_get_secure_partition_mmap(void *cookie);
-const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
+const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
void *cookie);
int plat_spm_sp_rd_load(struct sp_res_desc *rd, const void *ptr, size_t size);
int plat_spm_sp_get_next_address(void **sp_base, size_t *sp_size,
diff --git a/include/services/mm_svc.h b/include/services/mm_svc.h
deleted file mode 100644
index c111326..0000000
--- a/include/services/mm_svc.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef MM_SVC_H
-#define MM_SVC_H
-
-#if SPM_MM
-
-#include <lib/utils_def.h>
-
-#define MM_VERSION_MAJOR U(1)
-#define MM_VERSION_MAJOR_SHIFT 16
-#define MM_VERSION_MAJOR_MASK U(0x7FFF)
-#define MM_VERSION_MINOR U(0)
-#define MM_VERSION_MINOR_SHIFT 0
-#define MM_VERSION_MINOR_MASK U(0xFFFF)
-#define MM_VERSION_FORM(major, minor) ((major << MM_VERSION_MAJOR_SHIFT) | (minor))
-#define MM_VERSION_COMPILED MM_VERSION_FORM(MM_VERSION_MAJOR, MM_VERSION_MINOR)
-
-/*
- * SMC IDs defined in [1] for accessing MM services from the Non-secure world.
- * These FIDs occupy the range 0x40 - 0x5f.
- * [1] DEN0060A_ARM_MM_Interface_Specification.pdf
- */
-#define MM_VERSION_AARCH32 U(0x84000040)
-
-#define MM_COMMUNICATE_AARCH64 U(0xC4000041)
-#define MM_COMMUNICATE_AARCH32 U(0x84000041)
-
-#endif /* SPM_MM */
-
-#endif /* MM_SVC_H */
diff --git a/include/services/sp_res_desc.h b/include/services/sp_res_desc.h
deleted file mode 100644
index b8be72e..0000000
--- a/include/services/sp_res_desc.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SPM_RES_DESC_H
-#define SPM_RES_DESC_H
-
-#include <stdint.h>
-
-#include <services/sp_res_desc_def.h>
-
-/*******************************************************************************
- * Attribute Section
- ******************************************************************************/
-
-struct sp_rd_sect_attribute {
- /*
- * Version of the resource description.
- */
- uint16_t version;
-
- /*
- * Type of the Secure Partition:
- * - bit[0]: SP Type
- * - b'0: UP SP
- * - b'1: MP SP
- * If UP SP:
- * - bit[1]: Type of UP SP
- * - b'0: Migratable UP SP
- * - b'1: Pinned UP SP
- */
- uint16_t sp_type;
-
- /*
- * If this is a Pinned UP SP, PE on which the Pinned UP SP will run.
- */
- uint32_t pe_mpidr;
-
- /*
- * Run-Time Exception Level:
- * - 0: SEL0 SP
- * - 1: SEL1 SP
- */
- uint8_t runtime_el;
-
- /*
- * Type of Execution:
- * - 0: Init-time only
- * - 1: Run-time Execution
- */
- uint8_t exec_type;
-
- /*
- * Expected behavior upon failure:
- * - 0: Restartable
- * - 1: One-Shot
- */
- uint8_t panic_policy;
-
- /*
- * Translation Granule to use in the SP translation regime:
- * - 0: 4KB
- * - 1: 16KB
- * - 2: 64KB
- */
- uint8_t xlat_granule;
-
- /*
- * Size of the SP binary in bytes.
- */
- uint32_t binary_size;
-
- /*
- * - If SP is NOT PIE:
- * - VA Address where the SP expects to be loaded.
- * - If SP is PIE:
- * - Ignored.
- */
- uint64_t load_address;
-
- /*
- * Initial execution address. This is a VA as the SP sees it.
- */
- uint64_t entrypoint;
-};
-
-/*******************************************************************************
- * Memory Region Section
- ******************************************************************************/
-
-struct sp_rd_sect_mem_region {
- /*
- * Name of a Memory region, including null terminator. Reserved names:
- * - "Client Shared Memory Region":
- * Memory region where memory shared by clients shall be mapped.
- * - "Queue Memory Region":
- * Memory region shared with SPM for SP queue management.
- */
- char name[RD_MEM_REGION_NAME_LEN];
-
- /*
- * Memory Attributes:
- * - bits[3:0]: Type of memory
- * - 0: Device
- * - 1: Code
- * - 2: Data
- * - 3: BSS
- * - 4: Read-only Data
- * - 5: SPM-to-SP Shared Memory Region
- * - 6: Client Shared Memory Region
- * - 7: Miscellaneous
- * - If memory is { SPM-to-SP shared Memory, Client Shared Memory,
- * Miscellaneous }
- * - bits[4]: Position Independent
- * - b'0: Position Dependent
- * - b'1: Position Independent
- */
- uint32_t attr;
-
- /*
- * Base address of the memory region.
- */
- uint64_t base;
-
- /*
- * Size of the memory region.
- */
- uint64_t size;
-
- /*
- * Pointer to next memory region (or NULL if this is the last one).
- */
- struct sp_rd_sect_mem_region *next;
-};
-
-/*******************************************************************************
- * Notification Section
- ******************************************************************************/
-
-struct sp_rd_sect_notification {
- /*
- * Notification attributes:
- * - bit[31]: Notification Type
- * - b'0: Platform Notification
- * - b'1: Interrupt
- * If Notification Type == Platform Notification
- * - bits[15:0]: Implementation-defined Notification ID
- * If Notification Type == Interrupt
- * - bits[15:0]: IRQ number
- * - bits[23:16]: Interrupt Priority
- * - bit[24]: Trigger Type
- * - b'0: Edge Triggered
- * - b'1: Level Triggered
- * - bit[25]: Trigger Level
- * - b'0: Falling or Low
- * - b'1: Rising or High
- */
- uint32_t attr;
-
- /*
- * Processing Element.
- * If Notification Type == Interrupt && IRQ number is { SGI, LPI }
- * - PE ID to which IRQ will be forwarded
- */
- uint32_t pe;
-
- /*
- * Pointer to next notification (or NULL if this is the last one).
- */
- struct sp_rd_sect_notification *next;
-};
-
-/*******************************************************************************
- * Service Description Section
- ******************************************************************************/
-
-struct sp_rd_sect_service {
- /*
- * Service identifier.
- */
- uint32_t uuid[4];
-
- /*
- * Accessibility Options:
- * - bit[0]: Accessibility by secure-world clients
- * - b'0: Not Accessible
- * - b'1: Accessible
- * - bit[1]: Accessible by EL3
- * - b'0: Not Accessible
- * - b'1: Accessible
- * - bit[2]: Accessible by normal-world clients
- * - b'0: Not Accessible
- * - b'1: Accessible
- */
- uint8_t accessibility;
-
- /*
- * Request type supported:
- * - bit[0]: Blocking request
- * - b'0: Not Enable
- * - b'1: Enable
- * - bit[1]: Non-blocking request
- * - b'0: Not Enable
- * - b'1: Enable
- */
- uint8_t request_type;
-
- /*
- * Maximum number of client connections that the service can support.
- */
- uint16_t connection_quota;
-
- /*
- * If the service requires secure world memory to be shared with its
- * clients:
- * - Maximum amount of secure world memory in bytes to reserve from the
- * secure world memory pool for the service.
- */
- uint32_t secure_mem_size;
-
- /*
- * Interrupt number used to notify the SP for the service.
- * - Should also be enabled in the Notification Section.
- */
- uint32_t interrupt_num;
-
- /*
- * Pointer to next service (or NULL if this is the last one).
- */
- struct sp_rd_sect_service *next;
-};
-
-/*******************************************************************************
- * Complete resource description struct
- ******************************************************************************/
-
-struct sp_res_desc {
-
- /* Attribute Section */
- struct sp_rd_sect_attribute attribute;
-
- /* System Resource Section */
- struct sp_rd_sect_mem_region *mem_region;
-
- struct sp_rd_sect_notification *notification;
-
- /* Service Section */
- struct sp_rd_sect_service *service;
-};
-
-#endif /* SPM_RES_DESC_H */
diff --git a/include/services/sp_res_desc_def.h b/include/services/sp_res_desc_def.h
deleted file mode 100644
index 5a3c50d..0000000
--- a/include/services/sp_res_desc_def.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SPM_RES_DESC_DEFS_H
-#define SPM_RES_DESC_DEFS_H
-
-#include <lib/utils_def.h>
-
-/*******************************************************************************
- * Attribute Section
- ******************************************************************************/
-
-#define RD_ATTR_TYPE_UP_MIGRATABLE U(0)
-#define RD_ATTR_TYPE_UP_PINNED U(2)
-#define RD_ATTR_TYPE_MP U(1)
-
-#define RD_ATTR_RUNTIME_SEL0 U(0)
-#define RD_ATTR_RUNTIME_SEL1 U(1)
-
-#define RD_ATTR_INIT_ONLY U(0)
-#define RD_ATTR_RUNTIME U(1)
-
-#define RD_ATTR_PANIC_RESTART U(0)
-#define RD_ATTR_PANIC_ONESHOT U(1)
-
-#define RD_ATTR_XLAT_GRANULE_4KB U(0)
-#define RD_ATTR_XLAT_GRANULE_16KB U(1)
-#define RD_ATTR_XLAT_GRANULE_64KB U(2)
-
-/*******************************************************************************
- * Memory Region Section
- ******************************************************************************/
-
-#define RD_MEM_REGION_NAME_LEN U(32)
-
-#define RD_MEM_DEVICE U(0)
-#define RD_MEM_NORMAL_CODE U(1)
-#define RD_MEM_NORMAL_DATA U(2)
-#define RD_MEM_NORMAL_BSS U(3)
-#define RD_MEM_NORMAL_RODATA U(4)
-#define RD_MEM_NORMAL_SPM_SP_SHARED_MEM U(5)
-#define RD_MEM_NORMAL_CLIENT_SHARED_MEM U(6)
-#define RD_MEM_NORMAL_MISCELLANEOUS U(7)
-
-#define RD_MEM_MASK U(15)
-
-#define RD_MEM_IS_PIE (U(1) << 4)
-
-/*******************************************************************************
- * Notification Section
- ******************************************************************************/
-
-#define RD_NOTIF_TYPE_PLATFORM (U(0) << 31)
-#define RD_NOTIF_TYPE_INTERRUPT (U(1) << 31)
-
-#define RD_NOTIF_PLAT_ID_MASK U(0xFFFF)
-#define RD_NOTIF_PLAT_ID_SHIFT U(0)
-
-#define RD_NOTIF_PLATFORM(id) \
- (RD_NOTIF_TYPE_PLATFORM \
- | (((id) & RD_NOTIF_PLAT_ID_MASK) << RD_NOTIF_PLAT_ID_SHIFT))
-
-#define RD_NOTIF_IRQ_NUM_MASK U(0xFFFF)
-#define RD_NOTIF_IRQ_NUM_SHIFT U(0)
-#define RD_NOTIF_IRQ_PRIO_MASK U(0xFF)
-#define RD_NOTIF_IRQ_PRIO_SHIFT U(16)
-
-#define RD_NOTIF_IRQ_EDGE_FALLING U(0)
-#define RD_NOTIF_IRQ_EDGE_RISING U(2)
-#define RD_NOTIF_IRQ_LEVEL_LOW U(1)
-#define RD_NOTIF_IRQ_LEVEL_HIGH U(3)
-#define RD_NOTIF_IRQ_TRIGGER_SHIFT U(24)
-
-#define RD_NOTIF_IRQ(num, prio, trig) \
- (RD_NOTIF_TYPE_IRQ \
- | (((num) & RD_NOTIF_IRQ_NUM_MASK) << RD_NOTIF_IRQ_NUM_SHIFT) \
- | (((prio) & RD_NOTIF_IRQ_PRIO_MASK) << RD_NOTIF_IRQ_PRIO_SHIFT) \
- | (((trig) << RD_NOTIF_IRQ_TRIGGER_SHIFT)))
-
-/*******************************************************************************
- * Service Description Section
- ******************************************************************************/
-
-#define RD_SERV_ACCESS_SECURE (U(1) << 0)
-#define RD_SERV_ACCESS_EL3 (U(1) << 1)
-#define RD_SERV_ACCESS_NORMAL (U(1) << 2)
-
-#define RD_SERV_SUPPORT_BLOCKING (U(1) << 0)
-#define RD_SERV_SUPPORT_NON_BLOCKING (U(1) << 0)
-
-#endif /* SPM_RES_DESC_DEFS_H */
diff --git a/include/services/spci_svc.h b/include/services/spci_svc.h
deleted file mode 100644
index 1d02bfa..0000000
--- a/include/services/spci_svc.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SPCI_SVC_H
-#define SPCI_SVC_H
-
-#include <lib/smccc.h>
-#include <lib/utils_def.h>
-
-/* SPCI_VERSION helpers */
-
-#define SPCI_VERSION_MAJOR U(0)
-#define SPCI_VERSION_MAJOR_SHIFT 16
-#define SPCI_VERSION_MAJOR_MASK U(0x7FFF)
-#define SPCI_VERSION_MINOR U(1)
-#define SPCI_VERSION_MINOR_SHIFT 0
-#define SPCI_VERSION_MINOR_MASK U(0xFFFF)
-#define SPCI_VERSION_FORM(major, minor) ((((major) & SPCI_VERSION_MAJOR_MASK) \
- << SPCI_VERSION_MAJOR_SHIFT) | \
- ((minor) & SPCI_VERSION_MINOR_MASK))
-#define SPCI_VERSION_COMPILED SPCI_VERSION_FORM(SPCI_VERSION_MAJOR, \
- SPCI_VERSION_MINOR)
-
-/* Definitions to build the complete SMC ID */
-
-#define SPCI_FID_MISC_FLAG (U(0) << 27)
-#define SPCI_FID_MISC_SHIFT U(20)
-#define SPCI_FID_MISC_MASK U(0x7F)
-
-#define SPCI_FID_TUN_FLAG (U(1) << 27)
-#define SPCI_FID_TUN_SHIFT U(24)
-#define SPCI_FID_TUN_MASK U(0x7)
-
-#define OEN_SPCI_START U(0x30)
-#define OEN_SPCI_END U(0x3F)
-
-#define SPCI_SMC(spci_fid) ((OEN_SPCI_START << FUNCID_OEN_SHIFT) | \
- (U(1) << 31) | (spci_fid))
-#define SPCI_MISC_32(misc_fid) ((SMC_32 << FUNCID_CC_SHIFT) | \
- SPCI_FID_MISC_FLAG | \
- SPCI_SMC((misc_fid) << SPCI_FID_MISC_SHIFT))
-#define SPCI_MISC_64(misc_fid) ((SMC_64 << FUNCID_CC_SHIFT) | \
- SPCI_FID_MISC_FLAG | \
- SPCI_SMC((misc_fid) << SPCI_FID_MISC_SHIFT))
-#define SPCI_TUN_32(tun_fid) ((SMC_32 << FUNCID_CC_SHIFT) | \
- SPCI_FID_TUN_FLAG | \
- SPCI_SMC((tun_fid) << SPCI_FID_TUN_SHIFT))
-#define SPCI_TUN_64(tun_fid) ((SMC_64 << FUNCID_CC_SHIFT) | \
- SPCI_FID_TUN_FLAG | \
- SPCI_SMC((tun_fid) << SPCI_FID_TUN_SHIFT))
-
-/* SPCI miscellaneous functions */
-
-#define SPCI_FID_VERSION U(0x0)
-#define SPCI_FID_SERVICE_HANDLE_OPEN U(0x2)
-#define SPCI_FID_SERVICE_HANDLE_CLOSE U(0x3)
-#define SPCI_FID_SERVICE_MEM_REGISTER U(0x4)
-#define SPCI_FID_SERVICE_MEM_UNREGISTER U(0x5)
-#define SPCI_FID_SERVICE_MEM_PUBLISH U(0x6)
-#define SPCI_FID_SERVICE_REQUEST_BLOCKING U(0x7)
-#define SPCI_FID_SERVICE_REQUEST_START U(0x8)
-#define SPCI_FID_SERVICE_GET_RESPONSE U(0x9)
-#define SPCI_FID_SERVICE_RESET_CLIENT_STATE U(0xA)
-
-/* SPCI tunneling functions */
-
-#define SPCI_FID_SERVICE_TUN_REQUEST_START U(0x0)
-#define SPCI_FID_SERVICE_REQUEST_RESUME U(0x1)
-#define SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING U(0x2)
-
-/* Complete SMC IDs and associated values */
-
-#define SPCI_VERSION SPCI_MISC_32(SPCI_FID_VERSION)
-
-#define SPCI_SERVICE_HANDLE_OPEN SPCI_MISC_32(SPCI_FID_SERVICE_HANDLE_OPEN)
-#define SPCI_SERVICE_HANDLE_OPEN_NOTIFY_BIT U(1)
-
-#define SPCI_SERVICE_HANDLE_CLOSE SPCI_MISC_32(SPCI_FID_SERVICE_HANDLE_CLOSE)
-
-#define SPCI_SERVICE_MEM_REGISTER_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_REGISTER)
-#define SPCI_SERVICE_MEM_REGISTER_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_REGISTER)
-
-#define SPCI_SERVICE_MEM_UNREGISTER_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_UNREGISTER)
-#define SPCI_SERVICE_MEM_UNREGISTER_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_UNREGISTER)
-
-#define SPCI_SERVICE_MEM_PUBLISH_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_PUBLISH)
-#define SPCI_SERVICE_MEM_PUBLISH_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_PUBLISH)
-
-#define SPCI_SERVICE_REQUEST_BLOCKING_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_REQUEST_BLOCKING)
-#define SPCI_SERVICE_REQUEST_BLOCKING_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_REQUEST_BLOCKING)
-
-#define SPCI_SERVICE_REQUEST_START_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_REQUEST_START)
-#define SPCI_SERVICE_REQUEST_START_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_REQUEST_START)
-
-#define SPCI_SERVICE_GET_RESPONSE_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_GET_RESPONSE)
-#define SPCI_SERVICE_GET_RESPONSE_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_GET_RESPONSE)
-
-#define SPCI_SERVICE_RESET_CLIENT_STATE_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_RESET_CLIENT_STATE)
-#define SPCI_SERVICE_RESET_CLIENT_STATE_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_RESET_CLIENT_STATE)
-
-#define SPCI_SERVICE_TUN_REQUEST_START_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_TUN_REQUEST_START)
-#define SPCI_SERVICE_TUN_REQUEST_START_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_TUN_REQUEST_START)
-
-#define SPCI_SERVICE_REQUEST_RESUME_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_REQUEST_RESUME)
-#define SPCI_SERVICE_REQUEST_RESUME_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_REQUEST_RESUME)
-
-#define SPCI_SERVICE_TUN_REQUEST_BLOCKING_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING)
-#define SPCI_SERVICE_TUN_REQUEST_BLOCKING_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING)
-
-/* SPCI error codes. */
-
-#define SPCI_SUCCESS 0
-#define SPCI_NOT_SUPPORTED -1
-#define SPCI_INVALID_PARAMETER -2
-#define SPCI_NO_MEMORY -3
-#define SPCI_BUSY -4
-#define SPCI_QUEUED -5
-#define SPCI_DENIED -6
-#define SPCI_NOT_PRESENT -7
-
-#endif /* SPCI_SVC_H */
diff --git a/include/services/secure_partition.h b/include/services/spm_mm_partition.h
similarity index 70%
rename from include/services/secure_partition.h
rename to include/services/spm_mm_partition.h
index 0510f80..ad5ceef 100644
--- a/include/services/secure_partition.h
+++ b/include/services/spm_mm_partition.h
@@ -4,17 +4,15 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef SECURE_PARTITION_H
-#define SECURE_PARTITION_H
-
-#if SPM_MM
+#ifndef SPM_MM_PARTITION_H
+#define SPM_MM_PARTITION_H
#include <stdint.h>
#include <lib/utils_def.h>
/*
- * Flags used by the secure_partition_mp_info structure to describe the
+ * Flags used by the spm_mm_mp_info structure to describe the
* characteristics of a cpu. Only a single flag is defined at the moment to
* indicate the primary cpu.
*/
@@ -24,13 +22,13 @@
* This structure is used to provide information required to initialise a S-EL0
* partition.
*/
-typedef struct secure_partition_mp_info {
+typedef struct spm_mm_mp_info {
uint64_t mpidr;
uint32_t linear_id;
uint32_t flags;
-} secure_partition_mp_info_t;
+} spm_mm_mp_info_t;
-typedef struct secure_partition_boot_info {
+typedef struct spm_mm_boot_info {
param_header_t h;
uint64_t sp_mem_base;
uint64_t sp_mem_limit;
@@ -46,9 +44,7 @@
uint64_t sp_shared_buf_size;
uint32_t num_sp_mem_regions;
uint32_t num_cpus;
- secure_partition_mp_info_t *mp_info;
-} secure_partition_boot_info_t;
-
-#endif /* SPM_MM */
+ spm_mm_mp_info_t *mp_info;
+} spm_mm_boot_info_t;
-#endif /* SECURE_PARTITION_H */
+#endif /* SPM_MM_PARTITION_H */
diff --git a/include/services/spm_mm_svc.h b/include/services/spm_mm_svc.h
new file mode 100644
index 0000000..3148beb
--- /dev/null
+++ b/include/services/spm_mm_svc.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SPM_MM_SVC_H
+#define SPM_MM_SVC_H
+
+#include <lib/utils_def.h>
+
+/*
+ * The MM_VERSION_XXX definitions are used when responding to the
+ * MM_VERSION_AARCH32 service request. The version returned is different between
+ * this request and the SPM_MM_VERSION_AARCH32 request - both have been retained
+ * for compatibility.
+ */
+#define MM_VERSION_MAJOR U(1)
+#define MM_VERSION_MAJOR_SHIFT 16
+#define MM_VERSION_MAJOR_MASK U(0x7FFF)
+#define MM_VERSION_MINOR U(0)
+#define MM_VERSION_MINOR_SHIFT 0
+#define MM_VERSION_MINOR_MASK U(0xFFFF)
+#define MM_VERSION_FORM(major, minor) ((major << MM_VERSION_MAJOR_SHIFT) | \
+ (minor))
+#define MM_VERSION_COMPILED MM_VERSION_FORM(MM_VERSION_MAJOR, \
+ MM_VERSION_MINOR)
+
+#define SPM_MM_VERSION_MAJOR U(0)
+#define SPM_MM_VERSION_MAJOR_SHIFT 16
+#define SPM_MM_VERSION_MAJOR_MASK U(0x7FFF)
+#define SPM_MM_VERSION_MINOR U(1)
+#define SPM_MM_VERSION_MINOR_SHIFT 0
+#define SPM_MM_VERSION_MINOR_MASK U(0xFFFF)
+#define SPM_MM_VERSION_FORM(major, minor) ((major << \
+ SPM_MM_VERSION_MAJOR_SHIFT) | \
+ (minor))
+#define SPM_MM_VERSION_COMPILED SPM_MM_VERSION_FORM(SPM_MM_VERSION_MAJOR, \
+ SPM_MM_VERSION_MINOR)
+
+/* These macros are used to identify SPM-MM calls using the SMC function ID */
+#define SPM_MM_FID_MASK U(0xffff)
+#define SPM_MM_FID_MIN_VALUE U(0x40)
+#define SPM_MM_FID_MAX_VALUE U(0x7f)
+#define is_spm_mm_fid(_fid) \
+ ((((_fid) & SPM_MM_FID_MASK) >= SPM_MM_FID_MIN_VALUE) && \
+ (((_fid) & SPM_MM_FID_MASK) <= SPM_MM_FID_MAX_VALUE))
+
+/*
+ * SMC IDs defined in [1] for accessing MM services from the Non-secure world.
+ * These FIDs occupy the range 0x40 - 0x5f.
+ * [1] DEN0060A_ARM_MM_Interface_Specification.pdf
+ */
+#define MM_VERSION_AARCH32 U(0x84000040)
+#define MM_COMMUNICATE_AARCH64 U(0xC4000041)
+#define MM_COMMUNICATE_AARCH32 U(0x84000041)
+
+/*
+ * SMC IDs defined for accessing services implemented by the Secure Partition
+ * Manager from the Secure Partition(s). These services enable a partition to
+ * handle delegated events and request privileged operations from the manager.
+ * They occupy the range 0x60-0x7f.
+ */
+#define SPM_MM_VERSION_AARCH32 U(0x84000060)
+#define MM_SP_EVENT_COMPLETE_AARCH64 U(0xC4000061)
+#define MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 U(0xC4000064)
+#define MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 U(0xC4000065)
+
+/*
+ * Macros used by MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64.
+ */
+
+#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS U(0)
+#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW U(1)
+/* Value U(2) is reserved. */
+#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO U(3)
+#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK U(3)
+#define MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT 0
+
+#define MM_SP_MEMORY_ATTRIBUTES_EXEC (U(0) << 2)
+#define MM_SP_MEMORY_ATTRIBUTES_NON_EXEC (U(1) << 2)
+
+
+/* SPM error codes. */
+#define SPM_MM_SUCCESS 0
+#define SPM_MM_NOT_SUPPORTED -1
+#define SPM_MM_INVALID_PARAMETER -2
+#define SPM_MM_DENIED -3
+#define SPM_MM_NO_MEMORY -5
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+int32_t spm_mm_setup(void);
+
+uint64_t spm_mm_smc_handler(uint32_t smc_fid,
+ uint64_t x1,
+ uint64_t x2,
+ uint64_t x3,
+ uint64_t x4,
+ void *cookie,
+ void *handle,
+ uint64_t flags);
+
+/* Helper to enter a secure partition */
+uint64_t spm_mm_sp_call(uint32_t smc_fid,
+ uint64_t x1,
+ uint64_t x2,
+ uint64_t x3);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* SPM_MM_SVC_H */
diff --git a/include/services/spm_svc.h b/include/services/spm_svc.h
deleted file mode 100644
index a3723a0..0000000
--- a/include/services/spm_svc.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SPM_SVC_H
-#define SPM_SVC_H
-
-#if SPM_MM
-
-#include <lib/utils_def.h>
-
-#define SPM_VERSION_MAJOR U(0)
-#define SPM_VERSION_MAJOR_SHIFT 16
-#define SPM_VERSION_MAJOR_MASK U(0x7FFF)
-#define SPM_VERSION_MINOR U(1)
-#define SPM_VERSION_MINOR_SHIFT 0
-#define SPM_VERSION_MINOR_MASK U(0xFFFF)
-#define SPM_VERSION_FORM(major, minor) ((major << SPM_VERSION_MAJOR_SHIFT) | (minor))
-#define SPM_VERSION_COMPILED SPM_VERSION_FORM(SPM_VERSION_MAJOR, SPM_VERSION_MINOR)
-
-/* The macros below are used to identify SPM calls from the SMC function ID */
-#define SPM_FID_MASK U(0xffff)
-#define SPM_FID_MIN_VALUE U(0x40)
-#define SPM_FID_MAX_VALUE U(0x7f)
-#define is_spm_fid(_fid) \
- ((((_fid) & SPM_FID_MASK) >= SPM_FID_MIN_VALUE) && \
- (((_fid) & SPM_FID_MASK) <= SPM_FID_MAX_VALUE))
-
-/*
- * SMC IDs defined for accessing services implemented by the Secure Partition
- * Manager from the Secure Partition(s). These services enable a partition to
- * handle delegated events and request privileged operations from the manager.
- * They occupy the range 0x60-0x7f.
- */
-#define SPM_VERSION_AARCH32 U(0x84000060)
-#define SP_EVENT_COMPLETE_AARCH64 U(0xC4000061)
-#define SP_MEMORY_ATTRIBUTES_GET_AARCH64 U(0xC4000064)
-#define SP_MEMORY_ATTRIBUTES_SET_AARCH64 U(0xC4000065)
-
-/*
- * Macros used by SP_MEMORY_ATTRIBUTES_SET_AARCH64.
- */
-
-#define SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS U(0)
-#define SP_MEMORY_ATTRIBUTES_ACCESS_RW U(1)
-/* Value U(2) is reserved. */
-#define SP_MEMORY_ATTRIBUTES_ACCESS_RO U(3)
-#define SP_MEMORY_ATTRIBUTES_ACCESS_MASK U(3)
-#define SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT 0
-
-#define SP_MEMORY_ATTRIBUTES_EXEC (U(0) << 2)
-#define SP_MEMORY_ATTRIBUTES_NON_EXEC (U(1) << 2)
-
-
-/* SPM error codes. */
-#define SPM_SUCCESS 0
-#define SPM_NOT_SUPPORTED -1
-#define SPM_INVALID_PARAMETER -2
-#define SPM_DENIED -3
-#define SPM_NO_MEMORY -5
-
-#endif /* SPM_MM */
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-int32_t spm_setup(void);
-
-#if SPM_MM
-
-uint64_t spm_smc_handler(uint32_t smc_fid,
- uint64_t x1,
- uint64_t x2,
- uint64_t x3,
- uint64_t x4,
- void *cookie,
- void *handle,
- uint64_t flags);
-
-/* Helper to enter a Secure Partition */
-uint64_t spm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3);
-
-#endif /* SPM_MM */
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* SPM_SVC_H */
diff --git a/include/services/sprt_svc.h b/include/services/sprt_svc.h
deleted file mode 100644
index 2421ea2..0000000
--- a/include/services/sprt_svc.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SPRT_SVC_H
-#define SPRT_SVC_H
-
-#include <lib/smccc.h>
-#include <lib/utils_def.h>
-
-/* SPRT_VERSION helpers */
-
-#define SPRT_VERSION_MAJOR U(0)
-#define SPRT_VERSION_MAJOR_SHIFT 16
-#define SPRT_VERSION_MAJOR_MASK U(0x7FFF)
-#define SPRT_VERSION_MINOR U(1)
-#define SPRT_VERSION_MINOR_SHIFT 0
-#define SPRT_VERSION_MINOR_MASK U(0xFFFF)
-#define SPRT_VERSION_FORM(major, minor) ((((major) & SPRT_VERSION_MAJOR_MASK) \
- << SPRT_VERSION_MAJOR_SHIFT) | \
- ((minor) & SPRT_VERSION_MINOR_MASK))
-#define SPRT_VERSION_COMPILED SPRT_VERSION_FORM(SPRT_VERSION_MAJOR, \
- SPRT_VERSION_MINOR)
-
-/* SPRT function IDs */
-
-#define SPRT_FID_VERSION U(0x0)
-#define SPRT_FID_PUT_RESPONSE U(0x1)
-#define SPRT_FID_YIELD U(0x5)
-#define SPRT_FID_PANIC U(0x7)
-#define SPRT_FID_MEMORY_PERM_ATTR_GET U(0xB)
-#define SPRT_FID_MEMORY_PERM_ATTR_SET U(0xC)
-
-#define SPRT_FID_MASK U(0xFF)
-
-/* Definitions to build the complete SMC ID */
-
-#define OEN_SPRT_START U(0x20)
-#define OEN_SPRT_END U(0x2F)
-
-#define SPRT_SMC_64(sprt_fid) ((OEN_SPRT_START << FUNCID_OEN_SHIFT) | \
- (U(1) << 31) | ((sprt_fid) & SPRT_FID_MASK) | \
- (SMC_64 << FUNCID_CC_SHIFT))
-#define SPRT_SMC_32(sprt_fid) ((OEN_SPRT_START << FUNCID_OEN_SHIFT) | \
- (U(1) << 31) | ((sprt_fid) & SPRT_FID_MASK) | \
- (SMC_32 << FUNCID_CC_SHIFT))
-
-/* Complete SMC IDs */
-
-#define SPRT_VERSION SPRT_SMC_32(SPRT_FID_VERSION)
-#define SPRT_PUT_RESPONSE_AARCH64 SPRT_SMC_64(SPRT_FID_PUT_RESPONSE)
-#define SPRT_YIELD_AARCH64 SPRT_SMC_64(SPRT_FID_YIELD)
-#define SPRT_PANIC_AARCH64 SPRT_SMC_64(SPRT_FID_PANIC)
-#define SPRT_MEMORY_PERM_ATTR_GET_AARCH64 SPRT_SMC_64(SPRT_FID_MEMORY_PERM_ATTR_GET)
-#define SPRT_MEMORY_PERM_ATTR_SET_AARCH64 SPRT_SMC_64(SPRT_FID_MEMORY_PERM_ATTR_SET)
-
-/* Defines used by SPRT_MEMORY_PERM_ATTR_{GET,SET}_AARCH64 */
-
-#define SPRT_MEMORY_PERM_ATTR_RO U(0)
-#define SPRT_MEMORY_PERM_ATTR_RW U(1)
-#define SPRT_MEMORY_PERM_ATTR_RO_EXEC U(2)
-/* U(3) is reserved */
-#define SPRT_MEMORY_PERM_ATTR_MASK U(3)
-#define SPRT_MEMORY_PERM_ATTR_SHIFT 3
-
-/* SPRT error codes. */
-
-#define SPRT_SUCCESS 0
-#define SPRT_NOT_SUPPORTED -1
-#define SPRT_INVALID_PARAMETER -2
-
-#endif /* SPRT_SVC_H */
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 1101425..1bbd610 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -6,6 +6,7 @@
#include <arch.h>
#include <asm_macros.S>
+#include <assert_macros.S>
#include <context.h>
.global el1_sysregs_context_save
@@ -477,6 +478,13 @@
* ------------------------------------------------------------------
*/
func el3_exit
+#if ENABLE_ASSERTIONS
+ /* el3_exit assumes SP_EL0 on entry */
+ mrs x17, spsel
+ cmp x17, #MODE_SP_EL0
+ ASM_ASSERT(eq)
+#endif
+
/* ----------------------------------------------------------
* Save the current SP_EL0 i.e. the EL3 runtime stack which
* will be used for handling the next SMC.
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index d65e02d..b7908ad 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -181,6 +181,16 @@
scr_el3 |= SCR_HCE_BIT;
}
+ /* Enable S-EL2 if the next EL is EL2 and security state is secure */
+ if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) {
+ if (GET_RW(ep->spsr) != MODE_RW_64) {
+ ERROR("S-EL2 can not be used in AArch32.");
+ panic();
+ }
+
+ scr_el3 |= SCR_EEL2_BIT;
+ }
+
/*
* Initialise SCTLR_EL1 to the reset value corresponding to the target
* execution state setting all fields rather than relying of the hw.
diff --git a/lib/sprt/sprt_host.c b/lib/sprt/sprt_host.c
deleted file mode 100644
index c4d436e..0000000
--- a/lib/sprt/sprt_host.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <errno.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#include "sprt_common.h"
-#include "sprt_queue.h"
-
-void sprt_initialize_queues(void *buffer_base, size_t buffer_size)
-{
- /* Initialize queue for blocking messages */
-
- void *blocking_base = buffer_base;
- uint32_t blocking_num = 4U;
- size_t blocking_size = SPRT_QUEUE_HEADER_SIZE +
- SPRT_QUEUE_ENTRY_MSG_SIZE * blocking_num;
-
- sprt_queue_init(blocking_base, blocking_num, SPRT_QUEUE_ENTRY_MSG_SIZE);
-
- /* Initialize queue for non-blocking messages */
-
- void *non_blocking_base = (void *)((uintptr_t)blocking_base + blocking_size);
- size_t non_blocking_size = buffer_size - blocking_size;
- uint32_t non_blocking_num = (non_blocking_size - SPRT_QUEUE_HEADER_SIZE) /
- SPRT_QUEUE_ENTRY_MSG_SIZE;
-
- sprt_queue_init(non_blocking_base, non_blocking_num, SPRT_QUEUE_ENTRY_MSG_SIZE);
-}
-
-int sprt_push_message(void *buffer_base,
- const struct sprt_queue_entry_message *message,
- int queue_num)
-{
- struct sprt_queue *q = buffer_base;
-
- while (queue_num-- > 0) {
- uintptr_t next_addr = (uintptr_t)q + sizeof(struct sprt_queue) +
- q->entry_num * q->entry_size;
- q = (struct sprt_queue *) next_addr;
- }
-
- return sprt_queue_push(q, message);
-}
diff --git a/lib/sprt/sprt_host.mk b/lib/sprt/sprt_host.mk
deleted file mode 100644
index abcfe5e..0000000
--- a/lib/sprt/sprt_host.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2018, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-SPRT_LIB_SOURCES := $(addprefix lib/sprt/, \
- sprt_host.c \
- sprt_queue.c)
-
-SPRT_LIB_INCLUDES := -Iinclude/lib/sprt/
diff --git a/lib/sprt/sprt_queue.c b/lib/sprt/sprt_queue.c
deleted file mode 100644
index 2bd4139..0000000
--- a/lib/sprt/sprt_queue.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <stdint.h>
-#include <string.h>
-
-#include "sprt_queue.h"
-
-void sprt_queue_init(void *queue_base, uint32_t entry_num, uint32_t entry_size)
-{
- assert(queue_base != NULL);
- assert(entry_size > 0U);
- assert(entry_num > 0U);
-
- struct sprt_queue *queue = (struct sprt_queue *)queue_base;
-
- queue->entry_num = entry_num;
- queue->entry_size = entry_size;
- queue->idx_write = 0U;
- queue->idx_read = 0U;
-
- memset(queue->data, 0, entry_num * entry_size);
-}
-
-int sprt_queue_is_empty(void *queue_base)
-{
- assert(queue_base != NULL);
-
- struct sprt_queue *queue = (struct sprt_queue *)queue_base;
-
- return (queue->idx_write == queue->idx_read);
-}
-
-int sprt_queue_is_full(void *queue_base)
-{
- assert(queue_base != NULL);
-
- struct sprt_queue *queue = (struct sprt_queue *)queue_base;
-
- uint32_t idx_next_write = (queue->idx_write + 1) % queue->entry_num;
-
- return (idx_next_write == queue->idx_read);
-}
-
-int sprt_queue_push(void *queue_base, const void *entry)
-{
- assert(entry != NULL);
- assert(queue_base != NULL);
-
- if (sprt_queue_is_full(queue_base) != 0) {
- return -ENOMEM;
- }
-
- struct sprt_queue *queue = (struct sprt_queue *)queue_base;
-
- uint8_t *dst_entry = &queue->data[queue->entry_size * queue->idx_write];
-
- memcpy(dst_entry, entry, queue->entry_size);
-
- /*
- * Make sure that the message data is visible before increasing the
- * counter of available messages.
- */
- __asm__ volatile("dmb st" ::: "memory");
-
- queue->idx_write = (queue->idx_write + 1) % queue->entry_num;
-
- __asm__ volatile("dmb st" ::: "memory");
-
- return 0;
-}
-
-int sprt_queue_pop(void *queue_base, void *entry)
-{
- assert(entry != NULL);
- assert(queue_base != NULL);
-
- if (sprt_queue_is_empty(queue_base) != 0) {
- return -ENOENT;
- }
-
- struct sprt_queue *queue = (struct sprt_queue *)queue_base;
-
- uint8_t *src_entry = &queue->data[queue->entry_size * queue->idx_read];
-
- memcpy(entry, src_entry, queue->entry_size);
-
- /*
- * Make sure that the message data is visible before increasing the
- * counter of read messages.
- */
- __asm__ volatile("dmb st" ::: "memory");
-
- queue->idx_read = (queue->idx_read + 1) % queue->entry_num;
-
- __asm__ volatile("dmb st" ::: "memory");
-
- return 0;
-}
diff --git a/lib/sprt/sprt_queue.h b/lib/sprt/sprt_queue.h
deleted file mode 100644
index 4ea1bc2..0000000
--- a/lib/sprt/sprt_queue.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SPRT_QUEUE_H
-#define SPRT_QUEUE_H
-
-#include <stdint.h>
-
-/* Struct that defines a queue. Not to be used directly. */
-struct __attribute__((__packed__)) sprt_queue {
- uint32_t entry_num; /* Number of entries */
- uint32_t entry_size; /* Size of an entry */
- uint32_t idx_write; /* Index of first empty entry */
- uint32_t idx_read; /* Index of first entry to read */
- uint8_t data[0]; /* Start of data */
-};
-
-#define SPRT_QUEUE_HEADER_SIZE (sizeof(struct sprt_queue))
-
-/*
- * Initializes a memory region to be used as a queue of the given number of
- * entries with the specified size.
- */
-void sprt_queue_init(void *queue_base, uint32_t entry_num, uint32_t entry_size);
-
-/* Returns 1 if the queue is empty, 0 otherwise */
-int sprt_queue_is_empty(void *queue_base);
-
-/* Returns 1 if the queue is full, 0 otherwise */
-int sprt_queue_is_full(void *queue_base);
-
-/*
- * Pushes a new entry intro the queue. Returns 0 on success, -ENOMEM if the
- * queue is full.
- */
-int sprt_queue_push(void *queue_base, const void *entry);
-
-/*
- * Pops an entry from the queue. Returns 0 on success, -ENOENT if the queue is
- * empty.
- */
-int sprt_queue_pop(void *queue_base, void *entry);
-
-#endif /* SPRT_QUEUE_H */
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 797f75c..a1f9db9 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -178,11 +178,8 @@
# SPD choice
SPD := none
-# For including the Secure Partition Manager
-ENABLE_SPM := 0
-
-# Use the SPM based on MM
-SPM_MM := 1
+# Enable the Management Mode (MM)-based Secure Partition Manager implementation
+SPM_MM := 0
# Flag to introduce an infinite loop in BL1 just before it exits into the next
# image. This is meant to help debugging the post-BL2 phase.
diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk
index 6866bd6..5e8885d 100644
--- a/plat/allwinner/common/allwinner-common.mk
+++ b/plat/allwinner/common/allwinner-common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -20,7 +20,8 @@
${AW_PLAT}/common/plat_helpers.S \
${AW_PLAT}/common/sunxi_common.c
-BL31_SOURCES += drivers/arm/gic/common/gic_common.c \
+BL31_SOURCES += drivers/allwinner/axp/common.c \
+ drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_helpers.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/delay_timer/delay_timer.c \
diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h
index 1166879..dcf3dc9 100644
--- a/plat/allwinner/common/include/sunxi_private.h
+++ b/plat/allwinner/common/include/sunxi_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,7 +12,7 @@
void sunxi_cpu_on(u_register_t mpidr);
void sunxi_cpu_off(u_register_t mpidr);
void sunxi_disable_secondary_cpus(u_register_t primary_mpidr);
-void __dead2 sunxi_power_down(void);
+void sunxi_power_down(void);
int sunxi_pmic_setup(uint16_t socid, const void *fdt);
void sunxi_security_setup(void);
@@ -20,7 +20,6 @@
uint16_t sunxi_read_soc_id(void);
void sunxi_set_gpio_out(char port, int pin, bool level_high);
int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb);
-void sunxi_execute_arisc_code(uint32_t *code, size_t size,
- int patch_offset, uint16_t param);
+void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param);
#endif /* SUNXI_PRIVATE_H */
diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
index 3b44aab..1e21a42 100644
--- a/plat/allwinner/common/sunxi_common.c
+++ b/plat/allwinner/common/sunxi_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -150,16 +150,16 @@
/* set both pins to pull-up */
mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U);
- /* assert, then de-assert reset of I2C/RSB controller */
- mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
- mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
-
/* un-gate clock */
if (socid != SUNXI_SOC_H6)
mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit);
else
mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0));
+ /* assert, then de-assert reset of I2C/RSB controller */
+ mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
+ mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
+
return 0;
}
@@ -172,8 +172,7 @@
* in SRAM, put the address of that into the reset vector and release the
* arisc reset line. The SCP will execute that code and pull the line up again.
*/
-void sunxi_execute_arisc_code(uint32_t *code, size_t size,
- int patch_offset, uint16_t param)
+void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param)
{
uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE - 0x4000 + 0x100;
@@ -187,8 +186,7 @@
} while (1);
/* Patch up the code to feed in an input parameter. */
- if (patch_offset >= 0 && patch_offset <= (size - 4))
- code[patch_offset] = (code[patch_offset] & ~0xffff) | param;
+ code[0] = (code[0] & ~0xffff) | param;
clean_dcache_range((uintptr_t)code, size);
/*
diff --git a/plat/allwinner/common/sunxi_cpu_ops.c b/plat/allwinner/common/sunxi_cpu_ops.c
index b4c9fcc..6e29b69 100644
--- a/plat/allwinner/common/sunxi_cpu_ops.c
+++ b/plat/allwinner/common/sunxi_cpu_ops.c
@@ -78,7 +78,7 @@
* patched into the first instruction.
*/
sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off),
- 0, BIT_32(core));
+ BIT_32(core));
}
void sunxi_cpu_on(u_register_t mpidr)
diff --git a/plat/allwinner/common/sunxi_pm.c b/plat/allwinner/common/sunxi_pm.c
index 13e1353..9b074d2 100644
--- a/plat/allwinner/common/sunxi_pm.c
+++ b/plat/allwinner/common/sunxi_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -65,6 +65,11 @@
sunxi_disable_secondary_cpus(read_mpidr());
sunxi_power_down();
+
+ udelay(1000);
+ ERROR("PSCI: Cannot turn off system, halting\n");
+ wfi();
+ panic();
}
static void __dead2 sunxi_system_reset(void)
diff --git a/plat/allwinner/sun50i_a64/platform.mk b/plat/allwinner/sun50i_a64/platform.mk
index b46fbc2..f6d5aa9 100644
--- a/plat/allwinner/sun50i_a64/platform.mk
+++ b/plat/allwinner/sun50i_a64/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -7,4 +7,5 @@
# The differences between the platform are covered by the include files.
include plat/allwinner/common/allwinner-common.mk
-PLAT_BL_COMMON_SOURCES += drivers/allwinner/sunxi_rsb.c
+BL31_SOURCES += drivers/allwinner/axp/axp803.c \
+ drivers/allwinner/sunxi_rsb.c
diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c
index 07a3716..5b7d76a 100644
--- a/plat/allwinner/sun50i_a64/sunxi_power.c
+++ b/plat/allwinner/sun50i_a64/sunxi_power.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -7,14 +7,11 @@
#include <errno.h>
-#include <libfdt.h>
-
#include <platform_def.h>
-#include <arch_helpers.h>
#include <common/debug.h>
+#include <drivers/allwinner/axp.h>
#include <drivers/allwinner/sunxi_rsb.h>
-#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <sunxi_def.h>
@@ -22,6 +19,7 @@
#include <sunxi_private.h>
static enum pmic_type {
+ UNKNOWN,
GENERIC_H5,
GENERIC_A64,
REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */
@@ -38,7 +36,7 @@
* disabled.
* This function only cares about peripherals.
*/
-void sunxi_turn_off_soc(uint16_t socid)
+static void sunxi_turn_off_soc(uint16_t socid)
{
int i;
@@ -113,174 +111,22 @@
return ret;
/* Associate the 8-bit runtime address with the 12-bit bus address. */
- return rsb_assign_runtime_address(AXP803_HW_ADDR,
- AXP803_RT_ADDR);
-}
-
-static int axp_write(uint8_t reg, uint8_t val)
-{
- return rsb_write(AXP803_RT_ADDR, reg, val);
-}
-
-static int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask)
-{
- uint8_t regval;
- int ret;
-
- ret = rsb_read(AXP803_RT_ADDR, reg);
- if (ret < 0)
+ ret = rsb_assign_runtime_address(AXP803_HW_ADDR,
+ AXP803_RT_ADDR);
+ if (ret)
return ret;
- regval = (ret & ~clr_mask) | set_mask;
-
- return rsb_write(AXP803_RT_ADDR, reg, regval);
-}
-
-#define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0)
-#define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask)
-
-static bool should_enable_regulator(const void *fdt, int node)
-{
- if (fdt_getprop(fdt, node, "phandle", NULL) != NULL)
- return true;
- if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL)
- return true;
- return false;
+ return axp_check_id();
}
-/*
- * Retrieve the voltage from a given regulator DTB node.
- * Both the regulator-{min,max}-microvolt properties must be present and
- * have the same value. Return that value in millivolts.
- */
-static int fdt_get_regulator_millivolt(const void *fdt, int node)
+int axp_read(uint8_t reg)
{
- const fdt32_t *prop;
- uint32_t min_volt;
-
- prop = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL);
- if (prop == NULL)
- return -EINVAL;
- min_volt = fdt32_to_cpu(*prop);
-
- prop = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL);
- if (prop == NULL)
- return -EINVAL;
-
- if (fdt32_to_cpu(*prop) != min_volt)
- return -EINVAL;
-
- return min_volt / 1000;
+ return rsb_read(AXP803_RT_ADDR, reg);
}
-#define NO_SPLIT 0xff
-
-static const struct axp_regulator {
- char *dt_name;
- uint16_t min_volt;
- uint16_t max_volt;
- uint16_t step;
- unsigned char split;
- unsigned char volt_reg;
- unsigned char switch_reg;
- unsigned char switch_bit;
-} regulators[] = {
- {"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0x10, 0},
- {"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4},
- {"dcdc6", 600, 1520, 10, 50, 0x25, 0x10, 5},
- {"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3},
- {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4},
- {"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5},
- {"fldo1", 700, 1450, 50, NO_SPLIT, 0x1c, 0x13, 2},
- {}
-};
-
-static int setup_regulator(const void *fdt, int node,
- const struct axp_regulator *reg)
+int axp_write(uint8_t reg, uint8_t val)
{
- int mvolt;
- uint8_t regval;
-
- if (!should_enable_regulator(fdt, node))
- return -ENOENT;
-
- mvolt = fdt_get_regulator_millivolt(fdt, node);
- if (mvolt < reg->min_volt || mvolt > reg->max_volt)
- return -EINVAL;
-
- regval = (mvolt / reg->step) - (reg->min_volt / reg->step);
- if (regval > reg->split)
- regval = ((regval - reg->split) / 2) + reg->split;
-
- axp_write(reg->volt_reg, regval);
- if (reg->switch_reg < 0xff)
- axp_setbits(reg->switch_reg, BIT(reg->switch_bit));
-
- INFO("PMIC: AXP803: %s voltage: %d.%03dV\n", reg->dt_name,
- mvolt / 1000, mvolt % 1000);
-
- return 0;
-}
-
-static void setup_axp803_rails(const void *fdt)
-{
- int node;
- bool dc1sw = false;
-
- /* locate the PMIC DT node, bail out if not found */
- node = fdt_node_offset_by_compatible(fdt, -1, "x-powers,axp803");
- if (node < 0) {
- WARN("BL31: PMIC: Cannot find AXP803 DT node, skipping initial setup.\n");
- return;
- }
-
- if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) {
- axp_clrbits(0x8f, BIT(4));
- axp_setbits(0x30, BIT(2));
- INFO("PMIC: AXP803: Enabling DRIVEVBUS\n");
- }
-
- /* descend into the "regulators" subnode */
- node = fdt_subnode_offset(fdt, node, "regulators");
- if (node < 0) {
- WARN("BL31: PMIC: Cannot find regulators subnode, skipping initial setup.\n");
- return;
- }
-
- /* iterate over all regulators to find used ones */
- for (node = fdt_first_subnode(fdt, node);
- node >= 0;
- node = fdt_next_subnode(fdt, node)) {
- const struct axp_regulator *reg;
- const char *name;
- int length;
-
- /* We only care if it's always on or referenced. */
- if (!should_enable_regulator(fdt, node))
- continue;
-
- name = fdt_get_name(fdt, node, &length);
- for (reg = regulators; reg->dt_name; reg++) {
- if (!strncmp(name, reg->dt_name, length)) {
- setup_regulator(fdt, node, reg);
- break;
- }
- }
-
- if (!strncmp(name, "dc1sw", length)) {
- /* Delay DC1SW enablement to avoid overheating. */
- dc1sw = true;
- continue;
- }
- }
- /*
- * If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts
- * down. So always enable DC1SW as the very last regulator.
- */
- if (dc1sw) {
- INFO("PMIC: AXP803: Enabling DC1SW\n");
- axp_setbits(0x12, BIT(7));
- }
+ return rsb_write(AXP803_RT_ADDR, reg, val);
}
int sunxi_pmic_setup(uint16_t socid, const void *fdt)
@@ -289,11 +135,16 @@
switch (socid) {
case SUNXI_SOC_H5:
+ NOTICE("PMIC: Assuming H5 reference regulator design\n");
+
pmic = REF_DESIGN_H5;
- NOTICE("BL31: PMIC: Defaulting to PortL GPIO according to H5 reference design.\n");
+
break;
case SUNXI_SOC_A64:
pmic = GENERIC_A64;
+
+ INFO("PMIC: Probing AXP803 on RSB\n");
+
ret = sunxi_init_platform_r_twi(socid, true);
if (ret)
return ret;
@@ -303,20 +154,16 @@
return ret;
pmic = AXP803_RSB;
- NOTICE("BL31: PMIC: Detected AXP803 on RSB.\n");
-
- if (fdt)
- setup_axp803_rails(fdt);
+ axp_setup_regulators(fdt);
break;
default:
- NOTICE("BL31: PMIC: No support for Allwinner %x SoC.\n", socid);
return -ENODEV;
}
return 0;
}
-void __dead2 sunxi_power_down(void)
+void sunxi_power_down(void)
{
switch (pmic) {
case GENERIC_H5:
@@ -354,16 +201,10 @@
/* (Re-)init RSB in case the rich OS has disabled it. */
sunxi_init_platform_r_twi(SUNXI_SOC_A64, true);
rsb_init();
-
- /* Set "power disable control" bit */
- axp_setbits(0x32, BIT(7));
+ axp_power_off();
break;
default:
break;
}
- udelay(1000);
- ERROR("PSCI: Cannot turn off system, halting.\n");
- wfi();
- panic();
}
diff --git a/plat/allwinner/sun50i_h6/platform.mk b/plat/allwinner/sun50i_h6/platform.mk
index 5c21ead..4ecc57c 100644
--- a/plat/allwinner/sun50i_h6/platform.mk
+++ b/plat/allwinner/sun50i_h6/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -7,4 +7,5 @@
# The differences between the platform are covered by the include files.
include plat/allwinner/common/allwinner-common.mk
-PLAT_BL_COMMON_SOURCES += drivers/mentor/i2c/mi2cv.c
+BL31_SOURCES += drivers/allwinner/axp/axp805.c \
+ drivers/mentor/i2c/mi2cv.c
diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c
index 5b5bad1..443015b 100644
--- a/plat/allwinner/sun50i_h6/sunxi_power.c
+++ b/plat/allwinner/sun50i_h6/sunxi_power.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -10,6 +10,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
+#include <drivers/allwinner/axp.h>
#include <drivers/delay_timer.h>
#include <drivers/mentor/mi2cv.h>
#include <lib/mmio.h>
@@ -19,53 +20,51 @@
#include <sunxi_private.h>
#define AXP805_ADDR 0x36
-#define AXP805_ID 0x03
-enum pmic_type {
- NO_PMIC,
+static enum pmic_type {
+ UNKNOWN,
AXP805,
-};
+} pmic;
-enum pmic_type pmic;
-
-int axp_i2c_read(uint8_t chip, uint8_t reg, uint8_t *val)
+int axp_read(uint8_t reg)
{
+ uint8_t val;
int ret;
- ret = i2c_write(chip, 0, 0, ®, 1);
- if (ret)
+ ret = i2c_write(AXP805_ADDR, 0, 0, ®, 1);
+ if (ret == 0)
+ ret = i2c_read(AXP805_ADDR, 0, 0, &val, 1);
+ if (ret) {
+ ERROR("PMIC: Cannot read AXP805 register %02x\n", reg);
return ret;
+ }
- return i2c_read(chip, 0, 0, val, 1);
+ return val;
}
-int axp_i2c_write(uint8_t chip, uint8_t reg, uint8_t val)
+int axp_write(uint8_t reg, uint8_t val)
{
- return i2c_write(chip, reg, 1, &val, 1);
+ int ret;
+
+ ret = i2c_write(AXP805_ADDR, reg, 1, &val, 1);
+ if (ret)
+ ERROR("PMIC: Cannot write AXP805 register %02x\n", reg);
+
+ return ret;
}
static int axp805_probe(void)
{
int ret;
- uint8_t val;
- ret = axp_i2c_write(AXP805_ADDR, 0xff, 0x0);
- if (ret) {
- ERROR("PMIC: Cannot put AXP805 to master mode.\n");
- return -EPERM;
- }
-
- ret = axp_i2c_read(AXP805_ADDR, AXP805_ID, &val);
+ /* Switch the AXP805 to master/single-PMIC mode. */
+ ret = axp_write(0xff, 0x0);
+ if (ret)
+ return ret;
- if (!ret && ((val & 0xcf) == 0x40))
- NOTICE("PMIC: AXP805 detected\n");
- else if (ret) {
- ERROR("PMIC: Cannot communicate with AXP805.\n");
- return -EPERM;
- } else {
- ERROR("PMIC: Non-AXP805 chip attached at AXP805's address.\n");
- return -EINVAL;
- }
+ ret = axp_check_id();
+ if (ret)
+ return ret;
return 0;
}
@@ -74,41 +73,36 @@
{
int ret;
+ INFO("PMIC: Probing AXP805 on I2C\n");
+
- sunxi_init_platform_r_twi(SUNXI_SOC_H6, false);
+ ret = sunxi_init_platform_r_twi(SUNXI_SOC_H6, false);
+ if (ret)
+ return ret;
+
/* initialise mi2cv driver */
i2c_init((void *)SUNXI_R_I2C_BASE);
- NOTICE("PMIC: Probing AXP805\n");
- pmic = AXP805;
-
ret = axp805_probe();
if (ret)
- pmic = NO_PMIC;
- else
- pmic = AXP805;
+ return ret;
+
+ pmic = AXP805;
+ axp_setup_regulators(fdt);
return 0;
}
-void __dead2 sunxi_power_down(void)
+void sunxi_power_down(void)
{
- uint8_t val;
-
switch (pmic) {
case AXP805:
/* Re-initialise after rich OS might have used it. */
sunxi_init_platform_r_twi(SUNXI_SOC_H6, false);
/* initialise mi2cv driver */
i2c_init((void *)SUNXI_R_I2C_BASE);
- axp_i2c_read(AXP805_ADDR, 0x32, &val);
- axp_i2c_write(AXP805_ADDR, 0x32, val | 0x80);
+ axp_power_off();
break;
default:
break;
}
-
- udelay(1000);
- ERROR("PSCI: Cannot communicate with PMIC, halting\n");
- wfi();
- panic();
}
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index a948796..c36cd6f 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -18,7 +18,7 @@
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
-#include <services/secure_partition.h>
+#include <services/spm_mm_partition.h>
#include "fvp_private.h"
@@ -96,12 +96,9 @@
ARM_MAP_BL1_RW,
#endif
#endif /* TRUSTED_BOARD_BOOT */
-#if ENABLE_SPM && SPM_MM
+#if SPM_MM
ARM_SP_IMAGE_MMAP,
#endif
-#if ENABLE_SPM && !SPM_MM
- PLAT_MAP_SP_PACKAGE_MEM_RW,
-#endif
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
@@ -127,16 +124,13 @@
MAP_DEVICE0,
MAP_DEVICE1,
ARM_V2M_MAP_MEM_PROTECT,
-#if ENABLE_SPM && SPM_MM
+#if SPM_MM
ARM_SPM_BUF_EL3_MMAP,
#endif
-#if ENABLE_SPM && !SPM_MM
- PLAT_MAP_SP_PACKAGE_MEM_RO,
-#endif
{0}
};
-#if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM
+#if defined(IMAGE_BL31) && SPM_MM
const mmap_region_t plat_arm_secure_partition_mmap[] = {
V2M_MAP_IOFPGA_EL0, /* for the UART */
MAP_REGION_FLAT(DEVICE0_BASE, \
@@ -190,12 +184,12 @@
}
#endif
-#if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM
+#if defined(IMAGE_BL31) && SPM_MM
/*
* Boot information passed to a secure partition during initialisation. Linear
* indices in MP information will be filled at runtime.
*/
-static secure_partition_mp_info_t sp_mp_info[] = {
+static spm_mm_mp_info_t sp_mp_info[] = {
[0] = {0x80000000, 0},
[1] = {0x80000001, 0},
[2] = {0x80000002, 0},
@@ -206,10 +200,10 @@
[7] = {0x80000103, 0},
};
-const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
+const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
.h.type = PARAM_SP_IMAGE_BOOT_INFO,
.h.version = VERSION_1,
- .h.size = sizeof(secure_partition_boot_info_t),
+ .h.size = sizeof(spm_mm_boot_info_t),
.h.attr = 0,
.sp_mem_base = ARM_SP_IMAGE_BASE,
.sp_mem_limit = ARM_SP_IMAGE_LIMIT,
@@ -233,7 +227,7 @@
return plat_arm_secure_partition_mmap;
}
-const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
+const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
void *cookie)
{
return &plat_arm_secure_partition_boot_info;
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 98dd0a9..fa855cf 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -61,7 +61,7 @@
* plat_arm_mmap array defined for each BL stage.
*/
#if defined(IMAGE_BL31)
-# if ENABLE_SPM
+# if SPM_MM
# define PLAT_ARM_MMAP_ENTRIES 9
# define MAX_XLAT_TABLES 9
# define PLAT_SP_IMAGE_MMAP_REGIONS 30
@@ -116,11 +116,7 @@
* calculated using the current BL31 PROGBITS debug size plus the sizes of
* BL2 and BL1-RW
*/
-#if ENABLE_SPM && !SPM_MM
-#define PLAT_ARM_MAX_BL31_SIZE UL(0x60000)
-#else
#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
-#endif
#ifndef __aarch64__
/*
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 3a9972b..55ad1c7 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -281,11 +281,6 @@
ifeq (${RESET_TO_BL31},1)
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
- ifeq (${ENABLE_SPM},1)
- ifeq (${SPM_MM},0)
- BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
- endif
- endif
ifeq (${SPD},trusty)
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
diff --git a/plat/arm/common/aarch64/arm_ehf.c b/plat/arm/common/aarch64/arm_ehf.c
index 4ae992c..69ebd79 100644
--- a/plat/arm/common/aarch64/arm_ehf.c
+++ b/plat/arm/common/aarch64/arm_ehf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,7 +24,7 @@
/* Normal priority SDEI */
EHF_PRI_DESC(ARM_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
#endif
-#if ENABLE_SPM
+#if SPM_MM
EHF_PRI_DESC(ARM_PRI_BITS, PLAT_SP_PRI),
#endif
};
diff --git a/plat/arm/common/execution_state_switch.c b/plat/arm/common/aarch64/execution_state_switch.c
similarity index 96%
rename from plat/arm/common/execution_state_switch.c
rename to plat/arm/common/aarch64/execution_state_switch.c
index 00ac16e..8835fa1 100644
--- a/plat/arm/common/execution_state_switch.c
+++ b/plat/arm/common/aarch64/execution_state_switch.c
@@ -39,8 +39,6 @@
uint32_t cookie_lo,
void *handle)
{
- /* Execution state can be switched only if EL3 is AArch64 */
-#ifdef __aarch64__
bool caller_64, thumb = false, from_el2;
unsigned int el, endianness;
u_register_t spsr, pc, scr, sctlr;
@@ -48,6 +46,11 @@
cpu_context_t *ctx = (cpu_context_t *) handle;
el3_state_t *el3_ctx = get_el3state_ctx(ctx);
+ /* Validate supplied entry point */
+ pc = (u_register_t) (((uint64_t) pc_hi << 32) | pc_lo);
+ if (arm_validate_ns_entrypoint(pc) != 0)
+ goto invalid_param;
+
/* That the SMC originated from NS is already validated by the caller */
/*
@@ -173,7 +176,6 @@
SMC_RET1(handle, STATE_SW_E_PARAM);
exec_denied:
-#endif /* __aarch64__ */
/* State switch denied */
SMC_RET1(handle, STATE_SW_E_DENIED);
}
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index bc0cf9a..03d842a 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -16,7 +16,7 @@
#include <lib/xlat_tables/xlat_tables_compat.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
-#include <services/secure_partition.h>
+#include <services/spm_mm_partition.h>
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak plat_get_ns_image_entrypoint
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index acc3797..9d4f05e 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -215,12 +215,17 @@
BL31_SOURCES += plat/arm/common/arm_bl31_setup.c \
plat/arm/common/arm_pm.c \
plat/arm/common/arm_topology.c \
- plat/arm/common/execution_state_switch.c \
plat/common/plat_psci_common.c
ifeq (${ENABLE_PMF}, 1)
-BL31_SOURCES += plat/arm/common/arm_sip_svc.c \
+ifeq (${ARCH}, aarch64)
+BL31_SOURCES += plat/arm/common/aarch64/execution_state_switch.c\
+ plat/arm/common/arm_sip_svc.c \
lib/pmf/pmf_smc.c
+else
+BL32_SOURCES += plat/arm/common/arm_sip_svc.c \
+ lib/pmf/pmf_smc.c
+endif
endif
ifeq (${EL3_EXCEPTION_HANDLING},1)
@@ -243,16 +248,6 @@
lib/extensions/pauth/pauth_helpers.S
endif
-# SPM uses libfdt in Arm platforms
-ifeq (${SPM_MM},0)
-ifeq (${ENABLE_SPM},1)
-BL31_SOURCES += common/fdt_wrappers.c \
- plat/common/plat_spm_rd.c \
- plat/common/plat_spm_sp.c \
- ${LIBFDT_SRCS}
-endif
-endif
-
ifneq (${TRUSTED_BOARD_BOOT},0)
# Include common TBB sources
diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c
index aafb190..e6c5a73 100644
--- a/plat/arm/common/arm_dyn_cfg.c
+++ b/plat/arm/common/arm_dyn_cfg.c
@@ -243,7 +243,8 @@
#ifdef BL31_BASE
/* Ensure the configs don't overlap with BL31 */
- if ((image_base > BL31_BASE) || ((image_base + image_size) > BL31_BASE))
+ if ((image_base >= BL31_BASE) &&
+ (image_base <= BL31_LIMIT))
continue;
#endif
/* Ensure the configs are loaded in a valid address */
@@ -254,7 +255,8 @@
* If BL32 is present, ensure that the configs don't
* overlap with it.
*/
- if (image_base >= BL32_BASE && image_base <= BL32_LIMIT)
+ if ((image_base >= BL32_BASE) &&
+ (image_base <= BL32_LIMIT))
continue;
#endif
}
@@ -263,7 +265,10 @@
cfg_mem_params->image_info.image_base = (uintptr_t)image_base;
cfg_mem_params->image_info.image_max_size = image_size;
- /* Remove the IMAGE_ATTRIB_SKIP_LOADING attribute from HW_CONFIG node */
+ /*
+ * Remove the IMAGE_ATTRIB_SKIP_LOADING attribute from
+ * HW_CONFIG or FW_CONFIG nodes
+ */
cfg_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
}
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c
index cfc5359..4a3a22e 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/arm/common/arm_gicv3.c
@@ -44,12 +44,11 @@
/*
* We save and restore the GICv3 context on system suspend. Allocate the
- * data in the designated EL3 Secure carve-out memory. The `volatile`
- * is used to prevent the compiler from removing the gicv3 contexts even
- * though the DEFINE_LOAD_SYM_ADDR creates a dummy reference to it.
+ * data in the designated EL3 Secure carve-out memory. The `used` attribute
+ * is used to prevent the compiler from removing the gicv3 contexts.
*/
-static volatile gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram");
-static volatile gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram");
+static gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram") __used;
+static gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram") __used;
/* Define accessor function to get reference to the GICv3 context */
DEFINE_LOAD_SYM_ADDR(rdist_ctx)
diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c
index 3d308a3..a61f5f8 100644
--- a/plat/arm/common/arm_sip_svc.c
+++ b/plat/arm/common/arm_sip_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -50,23 +50,22 @@
switch (smc_fid) {
case ARM_SIP_SVC_EXE_STATE_SWITCH: {
- u_register_t pc;
-
+ /* Execution state can be switched only if EL3 is AArch64 */
+#ifdef __aarch64__
/* Allow calls from non-secure only */
if (!is_caller_non_secure(flags))
SMC_RET1(handle, STATE_SW_E_DENIED);
- /* Validate supplied entry point */
- pc = (u_register_t) ((x1 << 32) | (uint32_t) x2);
- if (arm_validate_ns_entrypoint(pc) != 0)
- SMC_RET1(handle, STATE_SW_E_PARAM);
-
/*
* Pointers used in execution state switch are all 32 bits wide
*/
return (uintptr_t) arm_execution_state_switch(smc_fid,
(uint32_t) x1, (uint32_t) x2, (uint32_t) x3,
(uint32_t) x4, handle);
+#else
+ /* State switch denied */
+ SMC_RET1(handle, STATE_SW_E_DENIED);
+#endif /* __aarch64__ */
}
case ARM_SIP_SVC_CALL_COUNT:
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index a9cc852..e214573 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,7 +28,7 @@
* plat_arm_mmap array defined for each BL stage.
*/
#if defined(IMAGE_BL31)
-# if ENABLE_SPM
+# if SPM_MM
# define PLAT_ARM_MMAP_ENTRIES 9
# define MAX_XLAT_TABLES 7
# define PLAT_SP_IMAGE_MMAP_REGIONS 7
@@ -101,7 +101,7 @@
#elif defined(IMAGE_BL2U)
# define PLATFORM_STACK_SIZE 0x400
#elif defined(IMAGE_BL31)
-# if ENABLE_SPM
+# if SPM_MM
# define PLATFORM_STACK_SIZE 0x500
# else
# define PLATFORM_STACK_SIZE 0x400
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index b736b0b..7160111 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -10,8 +10,6 @@
RAS_EXTENSION := 0
-ENABLE_SPM := 0
-
SDEI_SUPPORT := 0
EL3_EXCEPTION_HANDLING := 0
diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c
index 3e207ec..b611eaf 100644
--- a/plat/arm/css/sgi/sgi_plat.c
+++ b/plat/arm/css/sgi/sgi_plat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,7 +15,7 @@
#include <plat/common/platform.h>
#include <drivers/arm/sbsa.h>
#include <sgi_base_platform_def.h>
-#include <services/secure_partition.h>
+#include <services/spm_mm_partition.h>
#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
V2M_FLASH0_SIZE, \
@@ -46,7 +46,7 @@
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
-#if ENABLE_SPM
+#if SPM_MM
ARM_SP_IMAGE_MMAP,
#endif
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
@@ -61,13 +61,13 @@
V2M_MAP_IOFPGA,
CSS_SGI_MAP_DEVICE,
SOC_CSS_MAP_DEVICE,
-#if ENABLE_SPM
+#if SPM_MM
ARM_SPM_BUF_EL3_MMAP,
#endif
{0}
};
-#if ENABLE_SPM && defined(IMAGE_BL31)
+#if SPM_MM && defined(IMAGE_BL31)
const mmap_region_t plat_arm_secure_partition_mmap[] = {
PLAT_ARM_SECURE_MAP_DEVICE,
ARM_SP_IMAGE_MMAP,
@@ -77,17 +77,17 @@
ARM_SPM_BUF_EL0_MMAP,
{0}
};
-#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
+#endif /* SPM_MM && defined(IMAGE_BL31) */
#endif
ARM_CASSERT_MMAP
-#if ENABLE_SPM && defined(IMAGE_BL31)
+#if SPM_MM && defined(IMAGE_BL31)
/*
* Boot information passed to a secure partition during initialisation. Linear
* indices in MP information will be filled at runtime.
*/
-static secure_partition_mp_info_t sp_mp_info[] = {
+static spm_mm_mp_info_t sp_mp_info[] = {
[0] = {0x81000000, 0},
[1] = {0x81000100, 0},
[2] = {0x81000200, 0},
@@ -98,10 +98,10 @@
[7] = {0x81010300, 0},
};
-const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
+const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
.h.type = PARAM_SP_IMAGE_BOOT_INFO,
.h.version = VERSION_1,
- .h.size = sizeof(secure_partition_boot_info_t),
+ .h.size = sizeof(spm_mm_boot_info_t),
.h.attr = 0,
.sp_mem_base = ARM_SP_IMAGE_BASE,
.sp_mem_limit = ARM_SP_IMAGE_LIMIT,
@@ -125,12 +125,12 @@
return plat_arm_secure_partition_mmap;
}
-const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
+const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
void *cookie)
{
return &plat_arm_secure_partition_boot_info;
}
-#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
+#endif /* SPM_MM && defined(IMAGE_BL31) */
#if TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
diff --git a/plat/arm/css/sgi/sgi_ras.c b/plat/arm/css/sgi/sgi_ras.c
index 0001ffd..f56544e 100644
--- a/plat/arm/css/sgi/sgi_ras.c
+++ b/plat/arm/css/sgi/sgi_ras.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,9 +12,8 @@
#include <lib/extensions/ras.h>
#include <plat/arm/common/arm_spm_def.h>
#include <plat/common/platform.h>
-#include <services/mm_svc.h>
#include <services/sdei.h>
-#include <services/spm_svc.h>
+#include <services/spm_mm_svc.h>
#include <sgi_ras.h>
@@ -142,11 +141,11 @@
sizeof(ras_map->ras_ev_num));
header->message_len = 4;
- spm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
- plat_my_core_pos());
+ spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
+ plat_my_core_pos());
/*
- * Do an EOI of the RAS interuupt. This allows the
+ * Do an EOI of the RAS interrupt. This allows the
* sdei event to be dispatched at the SDEI event's
* priority.
*/
diff --git a/plat/common/plat_spm_rd.c b/plat/common/plat_spm_rd.c
deleted file mode 100644
index ebd3e6d..0000000
--- a/plat/common/plat_spm_rd.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <string.h>
-
-#include <libfdt.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <common/fdt_wrappers.h>
-#include <lib/object_pool.h>
-#include <plat/common/platform.h>
-#include <services/sp_res_desc.h>
-
-/*******************************************************************************
- * Resource pool
- ******************************************************************************/
-static struct sp_rd_sect_mem_region rd_mem_regions[PLAT_SPM_MEM_REGIONS_MAX];
-static OBJECT_POOL_ARRAY(rd_mem_regions_pool, rd_mem_regions);
-
-static struct sp_rd_sect_notification rd_notifs[PLAT_SPM_NOTIFICATIONS_MAX];
-static OBJECT_POOL_ARRAY(rd_notifs_pool, rd_notifs);
-
-static struct sp_rd_sect_service rd_services[PLAT_SPM_SERVICES_MAX];
-static OBJECT_POOL_ARRAY(rd_services_pool, rd_services);
-
-/*******************************************************************************
- * Attribute section handler
- ******************************************************************************/
-static void rd_parse_attribute(struct sp_rd_sect_attribute *attr,
- const void *fdt, int node)
-{
- int rc = 0;
-
- /* The minimum size that can be read from the DTB is 32-bit. */
- uint32_t version, sp_type, runtime_el, exec_type;
- uint32_t panic_policy, xlat_granule;
-
- rc |= fdtw_read_cells(fdt, node, "version", 1, &version);
-
- if (version != 1) {
- ERROR("Unsupported resource description version: 0x%x\n",
- version);
- panic();
- }
-
- rc |= fdtw_read_cells(fdt, node, "sp_type", 1, &sp_type);
- rc |= fdtw_read_cells(fdt, node, "pe_mpidr", 1, &attr->pe_mpidr);
- rc |= fdtw_read_cells(fdt, node, "runtime_el", 1, &runtime_el);
- rc |= fdtw_read_cells(fdt, node, "exec_type", 1, &exec_type);
- rc |= fdtw_read_cells(fdt, node, "panic_policy", 1, &panic_policy);
- rc |= fdtw_read_cells(fdt, node, "xlat_granule", 1, &xlat_granule);
- rc |= fdtw_read_cells(fdt, node, "binary_size", 1, &attr->binary_size);
- rc |= fdtw_read_cells(fdt, node, "load_address", 2, &attr->load_address);
- rc |= fdtw_read_cells(fdt, node, "entrypoint", 2, &attr->entrypoint);
-
- attr->version = version;
- attr->sp_type = sp_type;
- attr->runtime_el = runtime_el;
- attr->exec_type = exec_type;
- attr->panic_policy = panic_policy;
- attr->xlat_granule = xlat_granule;
-
- VERBOSE(" Attribute Section:\n");
- VERBOSE(" version: 0x%x\n", version);
- VERBOSE(" sp_type: 0x%x\n", sp_type);
- VERBOSE(" pe_mpidr: 0x%x\n", attr->pe_mpidr);
- VERBOSE(" runtime_el: 0x%x\n", runtime_el);
- VERBOSE(" exec_type: 0x%x\n", exec_type);
- VERBOSE(" panic_policy: 0x%x\n", panic_policy);
- VERBOSE(" xlat_granule: 0x%x\n", xlat_granule);
- VERBOSE(" binary_size: 0x%x\n", attr->binary_size);
- VERBOSE(" load_address: 0x%llx\n", attr->load_address);
- VERBOSE(" entrypoint: 0x%llx\n", attr->entrypoint);
-
- if (rc) {
- ERROR("Failed to read attribute node elements.\n");
- panic();
- }
-}
-
-/*******************************************************************************
- * Memory regions section handlers
- ******************************************************************************/
-static void rd_parse_memory_region(struct sp_rd_sect_mem_region *rdmem,
- const void *fdt, int node)
-{
- int rc = 0;
- char name[RD_MEM_REGION_NAME_LEN];
-
- rc |= fdtw_read_string(fdt, node, "str", (char *)&name, sizeof(name));
- rc |= fdtw_read_cells(fdt, node, "attr", 1, &rdmem->attr);
- rc |= fdtw_read_cells(fdt, node, "base", 2, &rdmem->base);
- rc |= fdtw_read_cells(fdt, node, "size", 2, &rdmem->size);
-
- size_t len = strlcpy(rdmem->name, name, RD_MEM_REGION_NAME_LEN);
-
- if (len >= RD_MEM_REGION_NAME_LEN) {
- WARN("Memory region name truncated: '%s'\n", name);
- }
-
- VERBOSE(" Memory Region:\n");
- VERBOSE(" name: '%s'\n", rdmem->name);
- VERBOSE(" attr: 0x%x\n", rdmem->attr);
- VERBOSE(" base: 0x%llx\n", rdmem->base);
- VERBOSE(" size: 0x%llx\n", rdmem->size);
-
- if (rc) {
- ERROR("Failed to read mem_region node elements.\n");
- panic();
- }
-}
-
-static void rd_parse_memory_regions(struct sp_res_desc *rd, const void *fdt,
- int node)
-{
- int child;
- struct sp_rd_sect_mem_region *rdmem, *old_rdmem;
-
- fdt_for_each_subnode(child, fdt, node) {
- rdmem = pool_alloc(&rd_mem_regions_pool);
-
- /* Add element to the start of the list */
- old_rdmem = rd->mem_region;
- rd->mem_region = rdmem;
- rdmem->next = old_rdmem;
-
- rd_parse_memory_region(rdmem, fdt, child);
- }
-
- if ((child < 0) && (child != -FDT_ERR_NOTFOUND)) {
- ERROR("%d: fdt_for_each_subnode(): %d\n", __LINE__, node);
- panic();
- }
-}
-
-/*******************************************************************************
- * Notifications section handlers
- ******************************************************************************/
-static void rd_parse_notification(struct sp_rd_sect_notification *rdnot,
- const void *fdt, int node)
-{
- int rc = 0;
-
- rc |= fdtw_read_cells(fdt, node, "attr", 1, &rdnot->attr);
- rc |= fdtw_read_cells(fdt, node, "pe", 1, &rdnot->pe);
-
- VERBOSE(" Notification:\n");
- VERBOSE(" attr: 0x%x\n", rdnot->attr);
- VERBOSE(" pe: 0x%x\n", rdnot->pe);
-
- if (rc) {
- ERROR("Failed to read notification node elements.\n");
- panic();
- }
-}
-
-static void rd_parse_notifications(struct sp_res_desc *rd, const void *fdt, int node)
-{
- int child;
- struct sp_rd_sect_notification *rdnot, *old_rdnot;
-
- fdt_for_each_subnode(child, fdt, node) {
- rdnot = pool_alloc(&rd_notifs_pool);
-
- /* Add element to the start of the list */
- old_rdnot = rd->notification;
- rd->notification = rdnot;
- rdnot->next = old_rdnot;
-
- rd_parse_notification(rdnot, fdt, child);
- }
-
- if ((child < 0) && (child != -FDT_ERR_NOTFOUND)) {
- ERROR("%d: fdt_for_each_subnode(): %d\n", __LINE__, child);
- panic();
- }
-}
-
-/*******************************************************************************
- * Services section handlers
- ******************************************************************************/
-static void rd_parse_service(struct sp_rd_sect_service *rdsvc, const void *fdt,
- int node)
-{
- int rc = 0;
-
- /* The minimum size that can be read from the DTB is 32-bit. */
- uint32_t accessibility, request_type, connection_quota;
-
- rc |= fdtw_read_array(fdt, node, "uuid", 4, &rdsvc->uuid);
- rc |= fdtw_read_cells(fdt, node, "accessibility", 1, &accessibility);
- rc |= fdtw_read_cells(fdt, node, "request_type", 1, &request_type);
- rc |= fdtw_read_cells(fdt, node, "connection_quota", 1, &connection_quota);
- rc |= fdtw_read_cells(fdt, node, "sec_mem_size", 1, &rdsvc->secure_mem_size);
- rc |= fdtw_read_cells(fdt, node, "interrupt_num", 1, &rdsvc->interrupt_num);
-
- rdsvc->accessibility = accessibility;
- rdsvc->request_type = request_type;
- rdsvc->connection_quota = connection_quota;
-
- VERBOSE(" Service:\n");
- VERBOSE(" uuid: 0x%08x 0x%08x 0x%08x 0x%08x\n", rdsvc->uuid[0],
- rdsvc->uuid[1], rdsvc->uuid[2], rdsvc->uuid[3]);
- VERBOSE(" accessibility: 0x%x\n", accessibility);
- VERBOSE(" request_type: 0x%x\n", request_type);
- VERBOSE(" connection_quota: 0x%x\n", connection_quota);
- VERBOSE(" secure_memory_size: 0x%x\n", rdsvc->secure_mem_size);
- VERBOSE(" interrupt_num: 0x%x\n", rdsvc->interrupt_num);
-
- if (rc) {
- ERROR("Failed to read attribute node elements.\n");
- panic();
- }
-}
-
-static void rd_parse_services(struct sp_res_desc *rd, const void *fdt, int node)
-{
- int child;
- struct sp_rd_sect_service *rdsvc, *old_rdsvc;
-
- fdt_for_each_subnode(child, fdt, node) {
- rdsvc = pool_alloc(&rd_services_pool);
-
- /* Add element to the start of the list */
- old_rdsvc = rd->service;
- rd->service = rdsvc;
- rdsvc->next = old_rdsvc;
-
- rd_parse_service(rdsvc, fdt, child);
- }
-
- if ((child < 0) && (child != -FDT_ERR_NOTFOUND)) {
- ERROR("%d: fdt_for_each_subnode(): %d\n", __LINE__, node);
- panic();
- }
-}
-
-/*******************************************************************************
- * Root node handler
- ******************************************************************************/
-static void rd_parse_root(struct sp_res_desc *rd, const void *fdt, int root)
-{
- int node;
- char *str;
-
- str = "attribute";
- node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str));
- if (node < 0) {
- ERROR("Root node doesn't contain subnode '%s'\n", str);
- panic();
- } else {
- rd_parse_attribute(&rd->attribute, fdt, node);
- }
-
- str = "memory_regions";
- node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str));
- if (node < 0) {
- ERROR("Root node doesn't contain subnode '%s'\n", str);
- panic();
- } else {
- rd_parse_memory_regions(rd, fdt, node);
- }
-
- str = "notifications";
- node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str));
- if (node < 0) {
- WARN("Root node doesn't contain subnode '%s'\n", str);
- } else {
- rd_parse_notifications(rd, fdt, node);
- }
-
- str = "services";
- node = fdt_subnode_offset_namelen(fdt, root, str, strlen(str));
- if (node < 0) {
- WARN("Root node doesn't contain subnode '%s'\n", str);
- } else {
- rd_parse_services(rd, fdt, node);
- }
-}
-
-/*******************************************************************************
- * Platform handler to load resource descriptor blobs into the active Secure
- * Partition context.
- ******************************************************************************/
-int plat_spm_sp_rd_load(struct sp_res_desc *rd, const void *ptr, size_t size)
-{
- int rc;
- int root_node;
-
- assert(rd != NULL);
- assert(ptr != NULL);
-
- INFO("Reading RD blob at address %p\n", ptr);
-
- rc = fdt_check_header(ptr);
- if (rc != 0) {
- ERROR("Wrong format for resource descriptor blob (%d).\n", rc);
- return -1;
- }
-
- root_node = fdt_node_offset_by_compatible(ptr, -1, "arm,sp_rd");
- if (root_node < 0) {
- ERROR("Unrecognized resource descriptor blob (%d)\n", rc);
- return -1;
- }
-
- rd_parse_root(rd, ptr, root_node);
-
- return 0;
-}
diff --git a/plat/common/plat_spm_sp.c b/plat/common/plat_spm_sp.c
deleted file mode 100644
index bc3d6a0..0000000
--- a/plat/common/plat_spm_sp.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <plat/common/platform.h>
-#include <tools_share/sptool.h>
-
-static unsigned int sp_next;
-
-/*******************************************************************************
- * Platform handler get the address of a Secure Partition and its resource
- * description blob. It iterates through all SPs detected by the platform. If
- * there is information for another SP, it returns 0. If there are no more SPs,
- * it returns -1.
- ******************************************************************************/
-int plat_spm_sp_get_next_address(void **sp_base, size_t *sp_size,
- void **rd_base, size_t *rd_size)
-{
- assert((sp_base != NULL) && (sp_size != NULL));
- assert((rd_base != NULL) && (rd_base != NULL));
-
- const uint64_t *pkg_base = (uint64_t *)PLAT_SP_PACKAGE_BASE;
-
- struct sp_pkg_header *pkg_header = (struct sp_pkg_header *)pkg_base;
-
- if (sp_next == 0) {
- if (pkg_header->version != 0x1) {
- ERROR("SP package has an unsupported version 0x%llx\n",
- pkg_header->version);
- panic();
- }
- }
-
- if (sp_next >= pkg_header->number_of_sp) {
- /* No more partitions in the package */
- return -1;
- }
-
- const struct sp_pkg_entry *entry_list =
- (const struct sp_pkg_entry *)((uintptr_t)pkg_base
- + sizeof(struct sp_pkg_header));
-
- const struct sp_pkg_entry *entry = &(entry_list[sp_next]);
-
- uint64_t sp_offset = entry->sp_offset;
- uint64_t rd_offset = entry->rd_offset;
-
- uintptr_t pkg_sp_base = ((uintptr_t)PLAT_SP_PACKAGE_BASE + sp_offset);
- uintptr_t pkg_rd_base = ((uintptr_t)PLAT_SP_PACKAGE_BASE + rd_offset);
-
- uint64_t pkg_sp_size = entry->sp_size;
- uint64_t pkg_rd_size = entry->rd_size;
-
- uintptr_t pkg_end = (uintptr_t)PLAT_SP_PACKAGE_BASE
- + (uintptr_t)PLAT_SP_PACKAGE_SIZE - 1U;
-
- /*
- * Check for overflows. The package header isn't trusted, so assert()
- * can't be used here.
- */
-
- uintptr_t pkg_sp_end = pkg_sp_base + pkg_sp_size - 1U;
- uintptr_t pkg_rd_end = pkg_rd_base + pkg_rd_size - 1U;
-
- if ((pkg_sp_end > pkg_end) || (pkg_sp_end < pkg_sp_base)) {
- ERROR("Invalid Secure Partition size (0x%llx)\n", pkg_sp_size);
- panic();
- }
-
- if ((pkg_rd_end > pkg_end) || (pkg_rd_end < pkg_rd_base)) {
- ERROR("Invalid Resource Description blob size (0x%llx)\n",
- pkg_rd_size);
- panic();
- }
-
- /* Return location of the binaries. */
-
- *sp_base = (void *)pkg_sp_base;
- *sp_size = pkg_sp_size;
- *rd_base = (void *)pkg_rd_base;
- *rd_size = pkg_rd_size;
-
- sp_next++;
-
- return 0;
-}
diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S
index 00fe2d9..27b538a 100644
--- a/plat/intel/soc/common/aarch64/plat_helpers.S
+++ b/plat/intel/soc/common/aarch64/plat_helpers.S
@@ -8,6 +8,7 @@
#include <asm_macros.S>
#include <cpu_macros.S>
#include <platform_def.h>
+#include <el3_common_macros.S>
.globl plat_secondary_cold_boot_setup
.globl platform_is_primary_cpu
@@ -17,6 +18,7 @@
.globl plat_crash_console_putc
.globl plat_crash_console_flush
.globl platform_mem_init
+ .globl plat_secondary_cpus_bl31_entry
.globl plat_get_my_entrypoint
@@ -33,7 +35,6 @@
/* Wait until the it gets reset signal from rstmgr gets populated */
poll_mailbox:
wfi
-
mov_imm x0, PLAT_SEC_ENTRY
ldr x1, [x0]
mov_imm x2, PLAT_CPUID_RELEASE
@@ -114,3 +115,14 @@
mov x0, #0
ret
endfunc platform_mem_init
+
+func plat_secondary_cpus_bl31_entry
+ el3_entrypoint_common \
+ _init_sctlr=0 \
+ _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
+ _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
+ _init_memory=1 \
+ _init_c_runtime=1 \
+ _exception_vectors=runtime_exceptions \
+ _pie_fixup_size=BL31_LIMIT - BL31_BASE
+endfunc plat_secondary_cpus_bl31_entry
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index e57aafb..d6014d3 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -16,8 +16,8 @@
#define PLAT_SOCFPGA_STRATIX10 1
#define PLAT_SOCFPGA_AGILEX 2
-#define PLAT_CPUID_RELEASE 0xffe1b000
-#define PLAT_SEC_ENTRY 0xffe1b008
+/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
+#define PLAT_CPU_RELEASE_ADDR 0xffd12210
/* Define next boot image name and offset */
#define PLAT_NS_IMAGE_OFFSET 0x50000
@@ -106,19 +106,24 @@
*/
-#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
+#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
-#define BL1_RO_BASE (0xffe00000)
-#define BL1_RO_LIMIT (0xffe0f000)
-#define BL1_RW_BASE (0xffe10000)
-#define BL1_RW_LIMIT (0xffe1ffff)
-#define BL1_RW_SIZE (0x14000)
+#define BL1_RO_BASE (0xffe00000)
+#define BL1_RO_LIMIT (0xffe0f000)
+#define BL1_RW_BASE (0xffe10000)
+#define BL1_RW_LIMIT (0xffe1ffff)
+#define BL1_RW_SIZE (0x14000)
-#define BL2_BASE (0xffe00000)
-#define BL2_LIMIT (0xffe1b000)
+#define BL2_BASE (0xffe00000)
+#define BL2_LIMIT (0xffe1b000)
-#define BL31_BASE (0xffe1c000)
-#define BL31_LIMIT (0xffe3bfff)
+#define BL31_BASE (0x1000)
+#define BL31_LIMIT (0x81000)
+
+#define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET
+
+#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16)
+#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8)
/*******************************************************************************
* Platform specific page table and MMU setup constants
@@ -194,5 +199,16 @@
#define MAX_IO_DEVICES 4
#define MAX_IO_BLOCK_DEVICES 2
+#ifndef __ASSEMBLER__
+struct socfpga_bl31_params {
+ param_header_t h;
+ image_info_t *bl31_image_info;
+ entry_point_info_t *bl32_ep_info;
+ image_info_t *bl32_image_info;
+ entry_point_info_t *bl33_ep_info;
+ image_info_t *bl33_image_info;
+};
+#endif
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index db4c841..c5f2fbe 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -11,6 +11,7 @@
#define MBOX_OFFSET 0xffa30000
+#define MBOX_MAX_JOB_ID 0xf
#define MBOX_ATF_CLIENT_ID 0x1
#define MBOX_JOB_ID 0x1
@@ -66,6 +67,9 @@
#define MBOX_CMD_GET_IDCODE 16
#define MBOX_CMD_QSPI_SET_CS 52
+/* Mailbox CANCEL command */
+#define MBOX_CMD_CANCEL 0x3
+
/* Mailbox REBOOT commands */
#define MBOX_CMD_REBOOT_HPS 71
@@ -75,41 +79,31 @@
#define MBOX_WRONG_ID -3
/* Mailbox status */
-#define RECONFIG_STATUS_STATE 0
-#define RECONFIG_STATUS_PIN_STATUS 2
-#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
-#define PIN_STATUS_NSTATUS (U(1) << 31)
-#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3)
-#define SOFTFUNC_STATUS_INIT_DONE (1 << 1)
-#define SOFTFUNC_STATUS_CONF_DONE (1 << 0)
-#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
-
-/* SMC function IDs for SiP Service queries */
-#define SIP_SVC_CALL_COUNT 0x8200ff00
-#define SIP_SVC_UID 0x8200ff01
-#define SIP_SVC_VERSION 0x8200ff03
-
-/* SiP Service Calls version numbers */
-#define SIP_SVC_VERSION_MAJOR 0
-#define SIP_SVC_VERSION_MINOR 1
+#define RECONFIG_STATUS_STATE 0
+#define RECONFIG_STATUS_PIN_STATUS 2
+#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
+#define PIN_STATUS_NSTATUS (U(1) << 31)
+#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3)
+#define SOFTFUNC_STATUS_INIT_DONE (1 << 1)
+#define SOFTFUNC_STATUS_CONF_DONE (1 << 0)
+#define MBOX_CFGSTAT_STATE_IDLE 0x00000000
+#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
+#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000
+#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001
+#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002
+#define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003
+#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004
+#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005
+#define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006
+#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
+#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
/* Mailbox reconfiguration commands */
+#define MBOX_CONFIG_STATUS 4
#define MBOX_RECONFIG 6
#define MBOX_RECONFIG_DATA 8
#define MBOX_RECONFIG_STATUS 9
-/* Sip get memory */
-#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
-#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
-#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
-#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
-#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
-#define INTEL_SIP_SMC_STATUS_OK 0
-#define INTEL_SIP_SMC_STATUS_ERROR 0x4
-#define INTEL_SIP_SMC_STATUS_BUSY 0x1
-#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
-#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x1000
-#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216
void mailbox_set_int(int interrupt_input);
int mailbox_init(void);
@@ -117,11 +111,14 @@
void mailbox_set_qspi_open(void);
void mailbox_set_qspi_direct(void);
int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
- int len, int urgent, uint32_t *response);
-void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
+ int len, int urgent, uint32_t *response, int resp_len);
+int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
int len, int urgent);
-int mailbox_read_response(int job_id, uint32_t *response);
+int mailbox_read_response(int job_id, uint32_t *response, int resp_len);
int mailbox_get_qspi_clock(void);
void mailbox_reset_cold(void);
+void mailbox_clear_response(void);
+
+uint32_t intel_mailbox_get_config_status(uint32_t cmd);
#endif /* SOCFPGA_MBOX_H */
diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h
index 3754844..ca38f62 100644
--- a/plat/intel/soc/common/include/socfpga_private.h
+++ b/plat/intel/soc/common/include/socfpga_private.h
@@ -61,5 +61,6 @@
unsigned long socfpga_get_ns_image_entrypoint(void);
+void plat_secondary_cpus_bl31_entry(void);
#endif /* SOCFPGA_PRIVATE_H */
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
new file mode 100644
index 0000000..6bb41f3
--- /dev/null
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SOCFPGA_SIP_SVC_H
+#define SOCFPGA_SIP_SVC_H
+
+
+/* SiP status response */
+#define INTEL_SIP_SMC_STATUS_OK 0
+#define INTEL_SIP_SMC_STATUS_ERROR 0x4
+#define INTEL_SIP_SMC_STATUS_BUSY 0x1
+#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
+
+/* SMC SiP service function identifier */
+#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
+#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
+#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
+#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
+#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
+#define INTEL_SIP_SMC_REG_READ 0xC2000007
+#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
+#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
+#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
+#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
+#define INTEL_SIP_LEGACY_SMC_ECC_DBE 0xC200000D
+#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
+#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
+
+/* FPGA config helpers */
+#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
+#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216
+
+/* SMC function IDs for SiP Service queries */
+#define SIP_SVC_CALL_COUNT 0x8200ff00
+#define SIP_SVC_UID 0x8200ff01
+#define SIP_SVC_VERSION 0x8200ff03
+
+/* SiP Service Calls version numbers */
+#define SIP_SVC_VERSION_MAJOR 0
+#define SIP_SVC_VERSION_MINOR 1
+
+#endif /* SOCFPGA_SIP_SVC_H */
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 27838bf..eb35c4a 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -6,8 +6,10 @@
#include <lib/mmio.h>
#include <common/debug.h>
+#include <drivers/delay_timer.h>
#include "socfpga_mailbox.h"
+#include "socfpga_sip_svc.h"
static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args,
int len)
@@ -17,12 +19,6 @@
cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN);
- if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) {
- INFO("Insufficient buffer in mailbox\n");
- return MBOX_INSUFFICIENT_BUFFER;
- }
-
-
mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + (cmd_free_offset++ * 4),
header_cmd);
@@ -39,28 +35,21 @@
return 0;
}
-int mailbox_read_response(int job_id, uint32_t *response)
+int mailbox_read_response(int job_id, uint32_t *response, int resp_len)
{
int rin = 0;
int rout = 0;
int response_length = 0;
int resp = 0;
int total_resp_len = 0;
- int timeout = 100000;
-
- mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1);
- while (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) {
- if (timeout-- < 0)
- return MBOX_NO_RESPONSE;
- }
-
- mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0);
+ if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM))
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0);
rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
- while (rout != rin) {
+ if (rout != rin) {
resp = mmio_read_32(MBOX_OFFSET +
MBOX_RESP_BUFFER + ((rout++)*4));
@@ -84,8 +73,9 @@
resp = mmio_read_32(MBOX_OFFSET +
MBOX_RESP_BUFFER +
(rout)*4);
- if (response) {
+ if (response && resp_len) {
*(response + total_resp_len) = resp;
+ resp_len--;
total_resp_len++;
}
rout++;
@@ -99,25 +89,25 @@
}
-int mailbox_poll_response(int job_id, int urgent, uint32_t *response)
+int mailbox_poll_response(int job_id, int urgent, uint32_t *response,
+ int resp_len)
{
- int timeout = 80000;
+ int timeout = 0xFFFFFF;
int rin = 0;
int rout = 0;
int response_length = 0;
int resp = 0;
int total_resp_len = 0;
- mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1);
-
while (1) {
+
while (timeout > 0 &&
- mmio_read_32(MBOX_OFFSET +
- MBOX_DOORBELL_FROM_SDM) != 1) {
+ !(mmio_read_32(MBOX_OFFSET +
+ MBOX_DOORBELL_FROM_SDM) & 1)) {
timeout--;
}
- if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) {
+ if (!timeout) {
INFO("Timed out waiting for SDM");
return MBOX_TIMEOUT;
}
@@ -125,6 +115,7 @@
mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0);
if (urgent & 1) {
+ mdelay(5);
if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) &
MBOX_STATUS_UA_MASK) ^
(urgent & MBOX_STATUS_UA_MASK)) {
@@ -158,13 +149,13 @@
response_length = MBOX_RESP_LEN(resp);
while (response_length) {
-
response_length--;
resp = mmio_read_32(MBOX_OFFSET +
MBOX_RESP_BUFFER +
(rout)*4);
- if (response) {
+ if (response && resp_len) {
*(response + total_resp_len) = resp;
+ resp_len--;
total_resp_len++;
}
rout++;
@@ -176,7 +167,7 @@
}
}
-void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
+int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
int len, int urgent)
{
if (urgent)
@@ -187,29 +178,44 @@
MBOX_CMD_LEN_CMD(len) |
MBOX_INDIRECT |
cmd, args, len);
+
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1);
+
+ return 0;
}
int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
- int len, int urgent, uint32_t *response)
+ int len, int urgent, uint32_t *response, int resp_len)
{
- int status;
+ int status = 0;
if (urgent) {
urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) &
MBOX_STATUS_UA_MASK;
mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd);
- status = 0;
- } else {
+ }
+
+ else {
status = fill_mailbox_circular_buffer(
MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) |
MBOX_JOB_ID_CMD(job_id) |
+ MBOX_CMD_LEN_CMD(len) |
cmd, args, len);
}
if (status)
return status;
- return mailbox_poll_response(job_id, urgent, response);
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1);
+ status = mailbox_poll_response(job_id, urgent, response, resp_len);
+
+ return status;
+}
+
+void mailbox_clear_response(void)
+{
+ mmio_write_32(MBOX_OFFSET + MBOX_ROUT,
+ mmio_read_32(MBOX_OFFSET + MBOX_RIN));
}
void mailbox_set_int(int interrupt)
@@ -223,24 +229,25 @@
void mailbox_set_qspi_open(void)
{
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
- mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, 0);
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, NULL, 0);
}
void mailbox_set_qspi_direct(void)
{
- mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0);
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, NULL, 0);
}
void mailbox_set_qspi_close(void)
{
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
- mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, 0);
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, NULL, 0);
}
int mailbox_get_qspi_clock(void)
{
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
- return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0);
+ return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0,
+ NULL, 0);
}
void mailbox_qspi_set_cs(int device_select)
@@ -251,13 +258,13 @@
cs_setting = (cs_setting << 28);
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting,
- 1, 0, 0);
+ 1, 0, NULL, 0);
}
void mailbox_reset_cold(void)
{
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
- mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, 0);
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, NULL, 0);
}
int mailbox_init(void)
@@ -268,13 +275,44 @@
MBOX_INT_FLAG_UAE);
mmio_write_32(MBOX_OFFSET + MBOX_URG, 0);
mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0);
- status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, 0);
+
+ status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, NULL, 0);
if (status)
return status;
- mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
+ mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE |
+ MBOX_INT_FLAG_UAE);
return 0;
}
+uint32_t intel_mailbox_get_config_status(uint32_t cmd)
+{
+ uint32_t status, res;
+ uint32_t response[6];
+
+ status = mailbox_send_cmd(1, cmd, NULL, 0, 0, response,
+ sizeof(response) / sizeof(response[0]));
+
+ if (status < 0)
+ return status;
+
+ res = response[RECONFIG_STATUS_STATE];
+ if (res && res != MBOX_CFGSTAT_STATE_CONFIG)
+ return res;
+
+ res = response[RECONFIG_STATUS_PIN_STATUS];
+ if (!(res & PIN_STATUS_NSTATUS))
+ return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
+
+ res = response[RECONFIG_STATUS_SOFTFUNC_STATUS];
+ if (res & SOFTFUNC_STATUS_SEU_ERROR)
+ return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
+
+ if ((res & SOFTFUNC_STATUS_CONF_DONE) &&
+ (res & SOFTFUNC_STATUS_INIT_DONE))
+ return 0;
+
+ return MBOX_CFGSTAT_STATE_CONFIG;
+}
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
index e298361..65a4b09 100644
--- a/plat/intel/soc/common/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -15,8 +15,6 @@
#include "socfpga_plat_def.h"
-uintptr_t *socfpga_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
-uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
/*******************************************************************************
* plat handler called when a CPU is about to enter standby.
@@ -45,7 +43,7 @@
if (cpu_id == -1)
return PSCI_E_INTERN_FAIL;
- *cpuid_release = cpu_id;
+ mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
/* release core reset */
mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
@@ -183,8 +181,8 @@
const struct plat_psci_ops **psci_ops)
{
/* Save warm boot entrypoint.*/
- *socfpga_sec_entry = sec_entrypoint;
-
+ mmio_write_64(PLAT_SEC_ENTRY, sec_entrypoint);
*psci_ops = &socfpga_psci_pm_ops;
+
return 0;
}
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 88750d7..c3c6ae0 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -10,6 +10,7 @@
#include <tools_share/uuid.h>
#include "socfpga_mailbox.h"
+#include "socfpga_sip_svc.h"
/* Number of SiP Calls implemented */
#define SIP_NUM_CALLS 0x3
@@ -17,13 +18,14 @@
/* Total buffer the driver can hold */
#define FPGA_CONFIG_BUFFER_SIZE 4
-int current_block;
-int current_buffer;
-int current_id = 1;
-int max_blocks;
-uint32_t bytes_per_block;
-uint32_t blocks_submitted;
-uint32_t blocks_completed;
+static int current_block;
+static int read_block;
+static int current_buffer;
+static int send_id;
+static int rcv_id;
+static int max_blocks;
+static uint32_t bytes_per_block;
+static uint32_t blocks_submitted;
struct fpga_config_info {
uint32_t addr;
@@ -54,79 +56,54 @@
struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
-static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
+static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
{
uint32_t args[3];
while (max_blocks > 0 && buffer->size > buffer->size_written) {
- if (buffer->size - buffer->size_written <=
- bytes_per_block) {
- args[0] = (1<<8);
- args[1] = buffer->addr + buffer->size_written;
+ args[0] = (1<<8);
+ args[1] = buffer->addr + buffer->size_written;
+ if (buffer->size - buffer->size_written <= bytes_per_block) {
args[2] = buffer->size - buffer->size_written;
- buffer->size_written +=
- buffer->size - buffer->size_written;
- buffer->subblocks_sent++;
- mailbox_send_cmd_async(0x4,
- MBOX_RECONFIG_DATA,
- args, 3, 0);
current_buffer++;
current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
- } else {
- args[0] = (1<<8);
- args[1] = buffer->addr + buffer->size_written;
+ } else
args[2] = bytes_per_block;
- buffer->size_written += bytes_per_block;
- mailbox_send_cmd_async(0x4,
- MBOX_RECONFIG_DATA,
- args, 3, 0);
- buffer->subblocks_sent++;
- }
+
+ buffer->size_written += args[2];
+ mailbox_send_cmd_async(
+ send_id++ % MBOX_MAX_JOB_ID,
+ MBOX_RECONFIG_DATA,
+ args, 3, 0);
+
+ buffer->subblocks_sent++;
max_blocks--;
}
+
+ return !max_blocks;
}
static int intel_fpga_sdm_write_all(void)
{
- int i;
-
- for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
- intel_fpga_sdm_write_buffer(
- &fpga_config_buffers[current_buffer]);
-
+ for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
+ if (intel_fpga_sdm_write_buffer(
+ &fpga_config_buffers[current_buffer]))
+ break;
return 0;
}
uint32_t intel_mailbox_fpga_config_isdone(void)
{
- uint32_t args[2];
- uint32_t response[6];
- int status;
-
- status = mailbox_send_cmd(1, MBOX_RECONFIG_STATUS, args, 0, 0,
- response);
+ uint32_t ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS);
- if (status < 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if (response[RECONFIG_STATUS_STATE] &&
- response[RECONFIG_STATUS_STATE] != MBOX_CFGSTAT_STATE_CONFIG)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if (!(response[RECONFIG_STATUS_PIN_STATUS] & PIN_STATUS_NSTATUS))
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if (response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
- SOFTFUNC_STATUS_SEU_ERROR)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if ((response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
- SOFTFUNC_STATUS_CONF_DONE) &&
- (response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
- SOFTFUNC_STATUS_INIT_DONE))
- return INTEL_SIP_SMC_STATUS_OK;
+ if (ret) {
+ if (ret == MBOX_CFGSTAT_STATE_CONFIG)
+ return INTEL_SIP_SMC_STATUS_BUSY;
+ else
+ return INTEL_SIP_SMC_STATUS_ERROR;
+ }
- return INTEL_SIP_SMC_STATUS_ERROR;
+ return INTEL_SIP_SMC_STATUS_OK;
}
static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
@@ -151,15 +128,6 @@
return -1;
}
-unsigned int address_in_ddr(uint32_t *addr)
-{
- if (((unsigned long long)addr > DRAM_BASE) &&
- ((unsigned long long)addr < DRAM_BASE + DRAM_SIZE))
- return 0;
-
- return -1;
-}
-
int intel_fpga_config_completed_write(uint32_t *completed_addr,
uint32_t *count)
{
@@ -168,30 +136,29 @@
int resp_len = 0;
uint32_t resp[5];
int all_completed = 1;
- int count_check = 0;
- if (address_in_ddr(completed_addr) != 0 || address_in_ddr(count) != 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
+ while (*count < 3) {
- for (count_check = 0; count_check < 3; count_check++)
- if (address_in_ddr(&completed_addr[*count + count_check]) != 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
+ resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID,
+ resp, sizeof(resp) / sizeof(resp[0]));
- resp_len = mailbox_read_response(0x4, resp);
+ if (resp_len < 0)
+ break;
- while (resp_len >= 0 && *count < 3) {
max_blocks++;
+ rcv_id++;
+
if (mark_last_buffer_xfer_completed(
&completed_addr[*count]) == 0)
*count = *count + 1;
else
break;
- resp_len = mailbox_read_response(0x4, resp);
}
if (*count <= 0) {
if (resp_len != MBOX_NO_RESPONSE &&
resp_len != MBOX_TIMEOUT && resp_len != 0) {
+ mailbox_clear_response();
return INTEL_SIP_SMC_STATUS_ERROR;
}
@@ -223,8 +190,12 @@
uint32_t response[3];
int status = 0;
- status = mailbox_send_cmd(2, MBOX_RECONFIG, 0, 0, 0,
- response);
+ mailbox_clear_response();
+
+ mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0);
+
+ status = mailbox_send_cmd(1, MBOX_RECONFIG, 0, 0, 0,
+ response, sizeof(response) / sizeof(response[0]));
if (status < 0)
return status;
@@ -243,47 +214,60 @@
blocks_submitted = 0;
current_block = 0;
+ read_block = 0;
current_buffer = 0;
+ send_id = 0;
+ rcv_id = 0;
return 0;
}
+static bool is_fpga_config_buffer_full(void)
+{
+ for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
+ if (!fpga_config_buffers[i].write_requested)
+ return false;
+ return true;
+}
+
+static bool is_address_in_ddr_range(uint64_t addr)
+{
+ if (addr >= DRAM_BASE && addr <= DRAM_BASE + DRAM_SIZE)
+ return true;
+
+ return false;
+}
uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
{
- int i = 0;
- uint32_t status = INTEL_SIP_SMC_STATUS_OK;
+ int i;
- if (mem < DRAM_BASE || mem > DRAM_BASE + DRAM_SIZE)
- status = INTEL_SIP_SMC_STATUS_REJECTED;
+ intel_fpga_sdm_write_all();
- if (mem + size > DRAM_BASE + DRAM_SIZE)
- status = INTEL_SIP_SMC_STATUS_REJECTED;
+ if (!is_address_in_ddr_range(mem) ||
+ !is_address_in_ddr_range(mem + size) ||
+ is_fpga_config_buffer_full())
+ return INTEL_SIP_SMC_STATUS_REJECTED;
for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
- if (!fpga_config_buffers[i].write_requested) {
- fpga_config_buffers[i].addr = mem;
- fpga_config_buffers[i].size = size;
- fpga_config_buffers[i].size_written = 0;
- fpga_config_buffers[i].write_requested = 1;
- fpga_config_buffers[i].block_number =
+ int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
+
+ if (!fpga_config_buffers[j].write_requested) {
+ fpga_config_buffers[j].addr = mem;
+ fpga_config_buffers[j].size = size;
+ fpga_config_buffers[j].size_written = 0;
+ fpga_config_buffers[j].write_requested = 1;
+ fpga_config_buffers[j].block_number =
blocks_submitted++;
- fpga_config_buffers[i].subblocks_sent = 0;
+ fpga_config_buffers[j].subblocks_sent = 0;
break;
}
}
+ if (is_fpga_config_buffer_full())
+ return INTEL_SIP_SMC_STATUS_BUSY;
- if (i == FPGA_CONFIG_BUFFER_SIZE) {
- status = INTEL_SIP_SMC_STATUS_REJECTED;
- return status;
- } else if (i == FPGA_CONFIG_BUFFER_SIZE - 1) {
- status = INTEL_SIP_SMC_STATUS_BUSY;
- }
-
- intel_fpga_sdm_write_all();
-
- return status;
+ return INTEL_SIP_SMC_STATUS_OK;
}
/*
@@ -349,6 +333,7 @@
SMC_RET4(handle, status, 0, 0, 0);
break;
default:
+ mailbox_clear_response();
SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
}
break;
diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index a133f82..29bd176 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -53,23 +53,33 @@
void *from_bl2 = (void *) arg0;
bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
-
assert(params_from_bl2 != NULL);
- assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
- assert(params_from_bl2->h.version >= VERSION_2);
/*
* Copy BL32 (if populated by BL31) and BL33 entry point information.
* They are stored in Secure RAM, in BL31's address space.
*/
+ if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
+ params_from_bl2->h.version >= VERSION_2) {
+
- bl_params_node_t *bl_params = params_from_bl2->head;
+ bl_params_node_t *bl_params = params_from_bl2->head;
- while (bl_params) {
- if (bl_params->image_id == BL33_IMAGE_ID)
- bl33_image_ep_info = *bl_params->ep_info;
+ while (bl_params) {
+ if (bl_params->image_id == BL33_IMAGE_ID)
+ bl33_image_ep_info = *bl_params->ep_info;
- bl_params = bl_params->next_params_info;
+ bl_params = bl_params->next_params_info;
+ }
+ } else {
+ struct socfpga_bl31_params *arg_from_bl2 =
+ (struct socfpga_bl31_params *) from_bl2;
+
+ assert(arg_from_bl2->h.type == PARAM_BL31);
+ assert(arg_from_bl2->h.version >= VERSION_1);
+
+ bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
+ bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
}
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
}
@@ -100,6 +110,10 @@
gicv2_distif_init();
gicv2_pcpu_distif_init();
gicv2_cpuif_enable();
+
+ /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
+ mmio_write_64(PLAT_CPU_RELEASE_ADDR,
+ (uint64_t)plat_secondary_cpus_bl31_entry);
}
const mmap_region_t plat_stratix10_mmap[] = {
diff --git a/plat/intel/soc/stratix10/plat_psci.c b/plat/intel/soc/stratix10/plat_psci.c
deleted file mode 100644
index 73389c9..0000000
--- a/plat/intel/soc/stratix10/plat_psci.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <common/debug.h>
-#include <errno.h>
-#include <lib/mmio.h>
-#include <drivers/arm/gic_common.h>
-#include <drivers/arm/gicv2.h>
-#include <plat/common/platform.h>
-#include <lib/psci/psci.h>
-
-#include "platform_def.h"
-#include "s10_reset_manager.h"
-#include "socfpga_mailbox.h"
-
-#define S10_RSTMGR_OFST 0xffd11000
-#define S10_RSTMGR_MPUMODRST_OFST 0x20
-
-uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
-uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
-
-/*******************************************************************************
- * plat handler called when a CPU is about to enter standby.
- ******************************************************************************/
-void plat_cpu_standby(plat_local_state_t cpu_state)
-{
- /*
- * Enter standby state
- * dsb is good practice before using wfi to enter low power states
- */
- VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
- dsb();
- wfi();
-}
-
-/*******************************************************************************
- * plat handler called when a power domain is about to be turned on. The
- * mpidr determines the CPU to be turned on.
- ******************************************************************************/
-int plat_pwr_domain_on(u_register_t mpidr)
-{
- unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
-
- VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
-
- if (cpu_id == -1)
- return PSCI_E_INTERN_FAIL;
-
- *cpuid_release = cpu_id;
-
- /* release core reset */
- mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
- return PSCI_E_SUCCESS;
-}
-
-/*******************************************************************************
- * plat handler called when a power domain is about to be turned off. The
- * target_state encodes the power state that each level should transition to.
- ******************************************************************************/
-void plat_pwr_domain_off(const psci_power_state_t *target_state)
-{
- unsigned int cpu_id = plat_my_core_pos();
-
- for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
- VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
- __func__, i, target_state->pwr_domain_state[i]);
-
- /* TODO: Prevent interrupts from spuriously waking up this cpu */
- /* gicv2_cpuif_disable(); */
-
- /* assert core reset */
- mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
-}
-
-/*******************************************************************************
- * plat handler called when a power domain is about to be suspended. The
- * target_state encodes the power state that each level should transition to.
- ******************************************************************************/
-void plat_pwr_domain_suspend(const psci_power_state_t *target_state)
-{
- unsigned int cpu_id = plat_my_core_pos();
-
- for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
- VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
- __func__, i, target_state->pwr_domain_state[i]);
- /* assert core reset */
- mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
-
-}
-
-/*******************************************************************************
- * plat handler called when a power domain has just been powered on after
- * being turned off earlier. The target_state encodes the low power state that
- * each level has woken up from.
- ******************************************************************************/
-void plat_pwr_domain_on_finish(const psci_power_state_t *target_state)
-{
- for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
- VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
- __func__, i, target_state->pwr_domain_state[i]);
-
- /* Program the gic per-cpu distributor or re-distributor interface */
- gicv2_pcpu_distif_init();
- gicv2_set_pe_target_mask(plat_my_core_pos());
-
- /* Enable the gic cpu interface */
- gicv2_cpuif_enable();
-}
-
-/*******************************************************************************
- * plat handler called when a power domain has just been powered on after
- * having been suspended earlier. The target_state encodes the low power state
- * that each level has woken up from.
- * TODO: At the moment we reuse the on finisher and reinitialize the secure
- * context. Need to implement a separate suspend finisher.
- ******************************************************************************/
-void plat_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
-{
- unsigned int cpu_id = plat_my_core_pos();
-
- for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
- VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
- __func__, i, target_state->pwr_domain_state[i]);
-
- /* release core reset */
- mmio_clrbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
-}
-
-/*******************************************************************************
- * plat handlers to shutdown/reboot the system
- ******************************************************************************/
-static void __dead2 plat_system_off(void)
-{
- wfi();
- ERROR("System Off: operation not handled.\n");
- panic();
-}
-
-static void __dead2 plat_system_reset(void)
-{
- INFO("assert Peripheral from Reset\r\n");
-
- deassert_peripheral_reset();
- mailbox_reset_cold();
-
- while (1)
- wfi();
-}
-
-int plat_validate_power_state(unsigned int power_state,
- psci_power_state_t *req_state)
-{
- VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
-
- return PSCI_E_SUCCESS;
-}
-
-int plat_validate_ns_entrypoint(unsigned long ns_entrypoint)
-{
- VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint);
- return PSCI_E_SUCCESS;
-}
-
-void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
-{
- req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
- req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
-}
-
-/*******************************************************************************
- * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
- * platform layer will take care of registering the handlers with PSCI.
- ******************************************************************************/
-const plat_psci_ops_t plat_psci_pm_ops = {
- .cpu_standby = plat_cpu_standby,
- .pwr_domain_on = plat_pwr_domain_on,
- .pwr_domain_off = plat_pwr_domain_off,
- .pwr_domain_suspend = plat_pwr_domain_suspend,
- .pwr_domain_on_finish = plat_pwr_domain_on_finish,
- .pwr_domain_suspend_finish = plat_pwr_domain_suspend_finish,
- .system_off = plat_system_off,
- .system_reset = plat_system_reset,
- .validate_power_state = plat_validate_power_state,
- .validate_ns_entrypoint = plat_validate_ns_entrypoint,
- .get_sys_suspend_power_state = plat_get_sys_suspend_power_state
-};
-
-/*******************************************************************************
- * Export the platform specific power ops.
- ******************************************************************************/
-int plat_setup_psci_ops(uintptr_t sec_entrypoint,
- const struct plat_psci_ops **psci_ops)
-{
- /* Save warm boot entrypoint.*/
- *stratix10_sec_entry = sec_entrypoint;
-
- *psci_ops = &plat_psci_pm_ops;
- return 0;
-}
diff --git a/plat/intel/soc/stratix10/plat_sip_svc.c b/plat/intel/soc/stratix10/plat_sip_svc.c
deleted file mode 100644
index 23a009d..0000000
--- a/plat/intel/soc/stratix10/plat_sip_svc.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <lib/mmio.h>
-#include <socfpga_mailbox.h>
-#include <tools_share/uuid.h>
-
-/* Number of SiP Calls implemented */
-#define SIP_NUM_CALLS 0x3
-
-/* Total buffer the driver can hold */
-#define FPGA_CONFIG_BUFFER_SIZE 4
-
-int current_block;
-int current_buffer;
-int current_id = 1;
-int max_blocks;
-uint32_t bytes_per_block;
-uint32_t blocks_submitted;
-uint32_t blocks_completed;
-
-struct fpga_config_info {
- uint32_t addr;
- int size;
- int size_written;
- uint32_t write_requested;
- int subblocks_sent;
- int block_number;
-};
-
-/* SiP Service UUID */
-DEFINE_SVC_UUID2(intl_svc_uid,
- 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
- 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
-
-uint64_t plat_sip_handler(uint32_t smc_fid,
- uint64_t x1,
- uint64_t x2,
- uint64_t x3,
- uint64_t x4,
- void *cookie,
- void *handle,
- uint64_t flags)
-{
- ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
- SMC_RET1(handle, SMC_UNK);
-}
-
-struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
-
-static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
-{
- uint32_t args[3];
-
- while (max_blocks > 0 && buffer->size > buffer->size_written) {
- if (buffer->size - buffer->size_written <=
- bytes_per_block) {
- args[0] = (1<<8);
- args[1] = buffer->addr + buffer->size_written;
- args[2] = buffer->size - buffer->size_written;
- buffer->size_written +=
- buffer->size - buffer->size_written;
- buffer->subblocks_sent++;
- mailbox_send_cmd_async(0x4,
- MBOX_RECONFIG_DATA,
- args, 3, 0);
- current_buffer++;
- current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
- } else {
- args[0] = (1<<8);
- args[1] = buffer->addr + buffer->size_written;
- args[2] = bytes_per_block;
- buffer->size_written += bytes_per_block;
- mailbox_send_cmd_async(0x4,
- MBOX_RECONFIG_DATA,
- args, 3, 0);
- buffer->subblocks_sent++;
- }
- max_blocks--;
- }
-}
-
-static int intel_fpga_sdm_write_all(void)
-{
- int i;
-
- for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
- intel_fpga_sdm_write_buffer(
- &fpga_config_buffers[current_buffer]);
-
- return 0;
-}
-
-uint32_t intel_mailbox_fpga_config_isdone(void)
-{
- uint32_t args[2];
- uint32_t response[6];
- int status;
-
- status = mailbox_send_cmd(1, MBOX_RECONFIG_STATUS, args, 0, 0,
- response);
-
- if (status < 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if (response[RECONFIG_STATUS_STATE] &&
- response[RECONFIG_STATUS_STATE] != MBOX_CFGSTAT_STATE_CONFIG)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if (!(response[RECONFIG_STATUS_PIN_STATUS] & PIN_STATUS_NSTATUS))
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if (response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
- SOFTFUNC_STATUS_SEU_ERROR)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if ((response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
- SOFTFUNC_STATUS_CONF_DONE) &&
- (response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
- SOFTFUNC_STATUS_INIT_DONE))
- return INTEL_SIP_SMC_STATUS_OK;
-
- return INTEL_SIP_SMC_STATUS_ERROR;
-}
-
-static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
-{
- int i;
-
- for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
- if (fpga_config_buffers[i].block_number == current_block) {
- fpga_config_buffers[i].subblocks_sent--;
- if (fpga_config_buffers[i].subblocks_sent == 0
- && fpga_config_buffers[i].size <=
- fpga_config_buffers[i].size_written) {
- fpga_config_buffers[i].write_requested = 0;
- current_block++;
- *buffer_addr_completed =
- fpga_config_buffers[i].addr;
- return 0;
- }
- }
- }
-
- return -1;
-}
-
-unsigned int address_in_ddr(uint32_t *addr)
-{
- if (((unsigned long long)addr > DRAM_BASE) &&
- ((unsigned long long)addr < DRAM_BASE + DRAM_SIZE))
- return 0;
-
- return -1;
-}
-
-int intel_fpga_config_completed_write(uint32_t *completed_addr,
- uint32_t *count)
-{
- uint32_t status = INTEL_SIP_SMC_STATUS_OK;
- *count = 0;
- int resp_len = 0;
- uint32_t resp[5];
- int all_completed = 1;
- int count_check = 0;
-
- if (address_in_ddr(completed_addr) != 0 || address_in_ddr(count) != 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- for (count_check = 0; count_check < 3; count_check++)
- if (address_in_ddr(&completed_addr[*count + count_check]) != 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- resp_len = mailbox_read_response(0x4, resp);
-
- while (resp_len >= 0 && *count < 3) {
- max_blocks++;
- if (mark_last_buffer_xfer_completed(
- &completed_addr[*count]) == 0)
- *count = *count + 1;
- else
- break;
- resp_len = mailbox_read_response(0x4, resp);
- }
-
- if (*count <= 0) {
- if (resp_len != MBOX_NO_RESPONSE &&
- resp_len != MBOX_TIMEOUT && resp_len != 0) {
- return INTEL_SIP_SMC_STATUS_ERROR;
- }
-
- *count = 0;
- }
-
- intel_fpga_sdm_write_all();
-
- if (*count > 0)
- status = INTEL_SIP_SMC_STATUS_OK;
- else if (*count == 0)
- status = INTEL_SIP_SMC_STATUS_BUSY;
-
- for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
- if (fpga_config_buffers[i].write_requested != 0) {
- all_completed = 0;
- break;
- }
- }
-
- if (all_completed == 1)
- return INTEL_SIP_SMC_STATUS_OK;
-
- return status;
-}
-
-int intel_fpga_config_start(uint32_t config_type)
-{
- uint32_t response[3];
- int status = 0;
-
- status = mailbox_send_cmd(2, MBOX_RECONFIG, 0, 0, 0,
- response);
-
- if (status < 0)
- return status;
-
- max_blocks = response[0];
- bytes_per_block = response[1];
-
- for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
- fpga_config_buffers[i].size = 0;
- fpga_config_buffers[i].size_written = 0;
- fpga_config_buffers[i].addr = 0;
- fpga_config_buffers[i].write_requested = 0;
- fpga_config_buffers[i].block_number = 0;
- fpga_config_buffers[i].subblocks_sent = 0;
- }
-
- blocks_submitted = 0;
- current_block = 0;
- current_buffer = 0;
-
- return 0;
-}
-
-
-uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
-{
- int i = 0;
- uint32_t status = INTEL_SIP_SMC_STATUS_OK;
-
- if (mem < DRAM_BASE || mem > DRAM_BASE + DRAM_SIZE)
- status = INTEL_SIP_SMC_STATUS_REJECTED;
-
- if (mem + size > DRAM_BASE + DRAM_SIZE)
- status = INTEL_SIP_SMC_STATUS_REJECTED;
-
- for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
- if (!fpga_config_buffers[i].write_requested) {
- fpga_config_buffers[i].addr = mem;
- fpga_config_buffers[i].size = size;
- fpga_config_buffers[i].size_written = 0;
- fpga_config_buffers[i].write_requested = 1;
- fpga_config_buffers[i].block_number =
- blocks_submitted++;
- fpga_config_buffers[i].subblocks_sent = 0;
- break;
- }
- }
-
-
- if (i == FPGA_CONFIG_BUFFER_SIZE) {
- status = INTEL_SIP_SMC_STATUS_REJECTED;
- return status;
- } else if (i == FPGA_CONFIG_BUFFER_SIZE - 1) {
- status = INTEL_SIP_SMC_STATUS_BUSY;
- }
-
- intel_fpga_sdm_write_all();
-
- return status;
-}
-
-/*
- * This function is responsible for handling all SiP calls from the NS world
- */
-
-uintptr_t sip_smc_handler(uint32_t smc_fid,
- u_register_t x1,
- u_register_t x2,
- u_register_t x3,
- u_register_t x4,
- void *cookie,
- void *handle,
- u_register_t flags)
-{
- uint32_t status = INTEL_SIP_SMC_STATUS_OK;
- uint32_t completed_addr[3];
- uint32_t count = 0;
-
- switch (smc_fid) {
- case SIP_SVC_UID:
- /* Return UID to the caller */
- SMC_UUID_RET(handle, intl_svc_uid);
- break;
- case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
- status = intel_mailbox_fpga_config_isdone();
- SMC_RET4(handle, status, 0, 0, 0);
- break;
- case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
- SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
- INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
- INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
- INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
- break;
- case INTEL_SIP_SMC_FPGA_CONFIG_START:
- status = intel_fpga_config_start(x1);
- SMC_RET4(handle, status, 0, 0, 0);
- break;
- case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
- status = intel_fpga_config_write(x1, x2);
- SMC_RET4(handle, status, 0, 0, 0);
- break;
- case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
- status = intel_fpga_config_completed_write(completed_addr,
- &count);
- switch (count) {
- case 1:
- SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
- completed_addr[0], 0, 0);
- break;
- case 2:
- SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
- completed_addr[0],
- completed_addr[1], 0);
- break;
- case 3:
- SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
- completed_addr[0],
- completed_addr[1],
- completed_addr[2]);
- break;
- case 0:
- SMC_RET4(handle, status, 0, 0, 0);
- break;
- default:
- SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
- }
- break;
-
- default:
- return plat_sip_handler(smc_fid, x1, x2, x3, x4,
- cookie, handle, flags);
- }
-}
-
-DECLARE_RT_SVC(
- s10_sip_svc,
- OEN_SIP_START,
- OEN_SIP_END,
- SMC_TYPE_FAST,
- NULL,
- sip_smc_handler
-);
-
-DECLARE_RT_SVC(
- s10_sip_svc_std,
- OEN_SIP_START,
- OEN_SIP_END,
- SMC_TYPE_YIELD,
- NULL,
- sip_smc_handler
-);
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index a665276..25fd84c 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -54,8 +54,9 @@
static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
.tzdram_size = TZDRAM_SIZE
};
-static unsigned long bl32_mem_size;
-static unsigned long bl32_boot_params;
+#ifdef SPD_trusty
+static aapcs64_params_t bl32_args;
+#endif
/*******************************************************************************
* This variable holds the non-secure image entry address
@@ -155,8 +156,10 @@
if (arg_from_bl2->bl32_ep_info != NULL) {
bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
- bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0;
- bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2;
+#ifdef SPD_trusty
+ /* save BL32 boot parameters */
+ memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args));
+#endif
}
/*
@@ -273,17 +276,20 @@
#ifdef SPD_trusty
void plat_trusty_set_boot_args(aapcs64_params_t *args)
{
- args->arg0 = bl32_mem_size;
- args->arg1 = bl32_boot_params;
- args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
+ /*
+ * arg0 = TZDRAM aperture available for BL32
+ * arg1 = BL32 boot params
+ * arg2 = EKS Blob Length
+ * arg3 = Boot Profiler Carveout Base
+ */
+ args->arg0 = bl32_args.arg0;
+ args->arg1 = bl32_args.arg2;
/* update EKS size */
- if (args->arg4 != 0U) {
- args->arg2 = args->arg4;
- }
+ args->arg2 = bl32_args.arg4;
/* Profiler Carveout Base */
- args->arg3 = args->arg5;
+ args->arg3 = bl32_args.arg5;
}
#endif
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index a8c70ea..39dc42c 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -244,7 +244,7 @@
/*
* Initialize the GIC cpu and distributor interfaces
*/
- tegra_gic_init();
+ tegra_gic_pcpu_init();
/*
* Check if we are exiting from deep sleep.
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 1a9ba0a..67f5abb 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -10,6 +10,12 @@
#include <lib/utils_def.h>
/*******************************************************************************
+ * Chip specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40)
+
+/*******************************************************************************
* These values are used by the PSCI implementation during the `CPU_SUSPEND`
* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
* parameter.
diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
new file mode 100644
index 0000000..e0444c1
--- /dev/null
+++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
@@ -0,0 +1,650 @@
+/*
+ * Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __TEGRA_MC_DEF_H__
+#define __TEGRA_MC_DEF_H__
+
+/*******************************************************************************
+ * Memory Controller Order_id registers
+ ******************************************************************************/
+#define MC_CLIENT_ORDER_ID_9 U(0x2a24)
+#define MC_CLIENT_ORDER_ID_9_RESET_VAL 0x00000000U
+#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_MASK (0x3U << 12)
+#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_ORDER_ID (3U << 12)
+
+#define MC_CLIENT_ORDER_ID_27 U(0x2a6c)
+#define MC_CLIENT_ORDER_ID_27_RESET_VAL 0x00000000U
+#define MC_CLIENT_ORDER_ID_27_PCIE0W_MASK (0x3U << 4)
+#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (1U << 4)
+
+#define MC_CLIENT_ORDER_ID_28 U(0x2a70)
+#define MC_CLIENT_ORDER_ID_28_RESET_VAL 0x00000000U
+#define MC_CLIENT_ORDER_ID_28_PCIE4W_MASK (0x3U << 4)
+#define MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID (3U << 4)
+#define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12)
+#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (2U << 12)
+
+#define mc_client_order_id(id, client) \
+ (~MC_CLIENT_ORDER_ID_##id##_##client##_MASK | \
+ MC_CLIENT_ORDER_ID_##id##_##client##_ORDER_ID)
+
+/*******************************************************************************
+ * Memory Controller's VC ID configuration registers
+ ******************************************************************************/
+#define VC_NISO 0U
+#define VC_SISO 1U
+#define VC_ISO 2U
+
+#define MC_HUB_PC_VC_ID_0 U(0x2a78)
+#define MC_HUB_PC_VC_ID_0_RESET_VAL 0x00020100U
+#define MC_HUB_PC_VC_ID_0_APB_VC_ID_MASK (0x3U << 8)
+#define MC_HUB_PC_VC_ID_0_APB_VC_ID (VC_NISO << 8)
+
+#define MC_HUB_PC_VC_ID_2 U(0x2a80)
+#define MC_HUB_PC_VC_ID_2_RESET_VAL 0x10001000U
+#define MC_HUB_PC_VC_ID_2_SD_VC_ID_MASK (0x3U << 28)
+#define MC_HUB_PC_VC_ID_2_SD_VC_ID (VC_NISO << 28)
+
+#define MC_HUB_PC_VC_ID_4 U(0x2a88)
+#define MC_HUB_PC_VC_ID_4_RESET_VAL 0x10020011U
+#define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28)
+#define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28)
+
+#define mc_hub_vc_id(id, client) \
+ (~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK | \
+ MC_HUB_PC_VC_ID_##id##_##client##_VC_ID)
+
+/*******************************************************************************
+ * Memory Controller's PCFIFO client configuration registers
+ ******************************************************************************/
+#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0U
+
+#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4U
+#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20200000U
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0U << 17)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1U << 17)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0U << 21)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1U << 21)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0U << 29)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_ORDERED (1U << 29)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1U << 29)
+
+#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8U
+#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x00002800U
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0U << 11)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1U << 11)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_ORDERED (1U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_UNORDERED (0U << 21)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_MASK (1U << 21)
+
+#define MC_PCFIFO_CLIENT_CONFIG3 0xddcU
+#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0x08000080U
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_UNORDERED (0U << 4)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_MASK (1U << 4)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_UNORDERED (0U << 6)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_MASK (1U << 6)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0U << 7)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1U << 7)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_UNORDERED (0U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_MASK (1U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_UNORDERED (0U << 27)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_MASK (1U << 27)
+
+#define MC_PCFIFO_CLIENT_CONFIG4 0xde0U
+#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0x5552a022U
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0U << 1)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1U << 1)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0U << 5)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1U << 5)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_UNORDERED (0U << 7)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK (1U << 7)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1U << 15)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_UNORDERED (0U << 20)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_MASK (1U << 20)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0U << 22)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1U << 22)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_UNORDERED (0U << 24)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_MASK (1U << 24)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0U << 26)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1U << 26)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_UNORDERED (0U << 28)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_MASK (1U << 28)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0U << 30)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1U << 30)
+
+#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4U
+#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0x20000001U
+#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0U << 0)
+#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1U << 0)
+#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_UNORDERED (0U << 30)
+#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_MASK (1U << 30)
+
+#define MC_PCFIFO_CLIENT_CONFIG6 0xb90U
+#define MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL 0xaa280000U
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_UNORDERED (0U << 19)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_MASK (1U << 19)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_UNORDERED (0U << 21)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_MASK (1U << 21)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_UNORDERED (0U << 25)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_MASK (1U << 25)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_ORDERED (1U << 27)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_MASK (1U << 27)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_ORDERED (1U << 29)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_MASK (1U << 29)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_ORDERED (1U << 31)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_MASK (1U << 31)
+
+#define MC_PCFIFO_CLIENT_CONFIG7 0xaccU
+#define MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL 0x0000000aU
+#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_UNORDERED (0U << 1)
+#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_MASK (1U << 1)
+#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_UNORDERED (0U << 3)
+#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_MASK (1U << 3)
+
+/*******************************************************************************
+ * StreamID to indicate no SMMU translations (requests to be steered on the
+ * SMMU bypass path)
+ ******************************************************************************/
+#define MC_STREAM_ID_MAX 0x7FU
+
+/*******************************************************************************
+ * Stream ID Override Config registers
+ ******************************************************************************/
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U
+#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xe0U
+#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3f8U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5f0U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U
+#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4f8U
+#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2a0U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5f8U
+#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U
+#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1c8U
+#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U
+#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U
+#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6d8U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U
+#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U
+#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1e8U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6f0U
+#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U
+#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4e8U
+#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xb0U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U
+#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U
+#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6e8U
+#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U
+#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U
+#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4d0U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U
+#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U
+#define MC_STREAMID_OVERRIDE_CFG_HDAR 0xa8U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U
+#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U
+#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6a8U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2a8U
+#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U
+#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3f0U
+#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4c8U
+#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4d8U
+#define MC_STREAMID_OVERRIDE_CFG_MIU5W 0x7e8U
+#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6b0U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U
+#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6c8U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U
+#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U
+#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U
+#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U
+#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U
+#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6a0U
+#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U
+#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3c8U
+#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U
+#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U
+#define MC_STREAMID_OVERRIDE_CFG_APER 0x3d0U
+#define MC_STREAMID_OVERRIDE_CFG_MIU7R 0x8U
+#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7c8U
+#define MC_STREAMID_OVERRIDE_CFG_MIU7W 0x10U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U
+#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4c0U
+#define MC_STREAMID_OVERRIDE_CFG_MIU4W 0x598U
+#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1a8U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4a0U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U
+#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U
+#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U
+#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4b0U
+#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7d8U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U
+#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U
+#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6b8U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6c0U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6f8U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U
+#define MC_STREAMID_OVERRIDE_CFG_MIU6W 0x7f8U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6d0U
+#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7d0U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U
+#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U
+#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U
+#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U
+#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U
+#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4b8U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4a8U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U
+#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5e8U
+#define MC_STREAMID_OVERRIDE_CFG_MIU6R 0x7f0U
+#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U
+#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3c0U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U
+#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U
+#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4f0U
+#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3d8U
+#define MC_STREAMID_OVERRIDE_CFG_MIU5R 0x7e0U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U
+#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U
+#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0U
+#define MC_STREAMID_OVERRIDE_CFG_MIU4R 0x590U
+#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U
+#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5e0U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6e0U
+#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U
+#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U
+#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4e0U
+#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U
+#define MC_STREAMID_OVERRIDE_CFG_SATAR 0xf8U
+#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U
+#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U
+#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U
+
+/*******************************************************************************
+ * Macro to calculate Security cfg register addr from StreamID Override register
+ ******************************************************************************/
+#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t))
+
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4)
+
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8)
+
+#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12)
+#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12)
+
+/*******************************************************************************
+ * Memory Controller transaction override config registers
+ ******************************************************************************/
+#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U
+#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16dcU
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644U
+#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U
+#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U
+#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U
+#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162cU
+#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U
+#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654U
+#define MC_TXN_OVERRIDE_CONFIG_MIU6R 0x17f4U
+#define MC_TXN_OVERRIDE_CONFIG_MIU5R 0x17e4U
+#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16c4U
+#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U
+#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U
+#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178cU
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774U
+#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16bcU
+#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U
+#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U
+#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714U
+#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U
+#define MC_TXN_OVERRIDE_CONFIG_MIU6W 0x17fcU
+#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179cU
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764U
+#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U
+#define MC_TXN_OVERRIDE_CONFIG_MIU7R 0x1008U
+#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U
+#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15f4U
+#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U
+#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17dcU
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176cU
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166cU
+#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U
+#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U
+#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16ecU
+#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16d4U
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674U
+#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164cU
+#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U
+#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16ccU
+#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17ccU
+#define MC_TXN_OVERRIDE_CONFIG_MIU7W 0x1010U
+#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U
+#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580U
+#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158cU
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U
+#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U
+#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U
+#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U
+#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U
+#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634U
+#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U
+#define MC_TXN_OVERRIDE_CONFIG_ISPFALR 0x1228U
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175cU
+#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16b4U
+#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664U
+#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174cU
+#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U
+#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U
+#define MC_TXN_OVERRIDE_CONFIG_AXIAPR 0x1410U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16e4U
+#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U
+#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578U
+#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170cU
+#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U
+#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U
+#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U
+#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U
+#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U
+#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17d4U
+#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614U
+#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U
+#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161cU
+#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U
+#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169cU
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U
+#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604U
+#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15e4U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16f4U
+#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171cU
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U
+#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538U
+#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160cU
+#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15ecU
+#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15fcU
+#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16fcU
+#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530U
+#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165cU
+#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U
+#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U
+#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U
+#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U
+#define MC_TXN_OVERRIDE_CONFIG_AXIAPW 0x1418U
+#define MC_TXN_OVERRIDE_CONFIG_MIU4R 0x1594U
+#define MC_TXN_OVERRIDE_CONFIG_MIU4W 0x159cU
+#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U
+#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U
+#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U
+#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U
+#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754U
+#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684U
+#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U
+#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168cU
+#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16a4U
+#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794U
+#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U
+#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16acU
+#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U
+#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U
+#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U
+#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U
+#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177cU
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163cU
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U
+#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167cU
+#define MC_TXN_OVERRIDE_CONFIG_MIU5W 0x17ecU
+#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U
+#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570U
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U
+#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704U
+#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U
+
+#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12)
+
+/*******************************************************************************
+ * Non-SO_DEV transactions override values for CGID_TAG bitfield for the
+ * MC_TXN_OVERRIDE_CONFIG_{module} registers
+ ******************************************************************************/
+#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U
+#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U
+#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U
+#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U
+#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3ULL
+
+/*******************************************************************************
+ * Memory Controller Reset Control registers
+ ******************************************************************************/
+#define MC_CLIENT_HOTRESET_CTRL0 0x200U
+#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U
+#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0)
+#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6)
+#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7)
+#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8)
+#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9)
+#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11)
+#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15)
+#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17)
+#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18)
+#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19)
+#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20)
+#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22)
+#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29)
+#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30)
+#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31)
+#define MC_CLIENT_HOTRESET_STATUS0 0x204U
+#define MC_CLIENT_HOTRESET_CTRL1 0x970U
+#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U
+#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0)
+#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2)
+#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5)
+#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6)
+#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7)
+#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8)
+#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12)
+#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13)
+#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 17)
+#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 18)
+#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 19)
+#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 20)
+#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 21)
+#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 22)
+#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 23)
+#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1U << 26)
+#define MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB (1U << 31)
+#define MC_CLIENT_HOTRESET_STATUS1 0x974U
+#define MC_CLIENT_HOTRESET_CTRL2 0x97cU
+#define MC_CLIENT_HOTRESET_CTRL2_RESET_VAL 0U
+#define MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB (1U << 0)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB (1U << 2)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB (1U << 4)
+#define MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB (1U << 9)
+#define MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB (1U << 10)
+#define MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB (1U << 11)
+#define MC_CLIENT_HOTRESET_CTRL2_APEDMA_FLUSH_ENB (1U << 14)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB (1U << 16)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB (1U << 17)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB (1U << 22)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB (1U << 23)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB (1U << 25)
+#define MC_CLIENT_HOTRESET_STATUS2 0x1898U
+
+/*******************************************************************************
+ * Tegra TSA Controller constants
+ ******************************************************************************/
+#define TEGRA_TSA_BASE U(0x02000000)
+
+#define TSA_CONFIG_STATIC0_CSR_RESET_R 0x20000000U
+#define TSA_CONFIG_STATIC0_CSW_RESET_W 0x20001000U
+#define TSA_CONFIG_STATIC0_CSW_RESET_SO_DEV 0x20001000U
+
+#define TSA_CONFIG_STATIC0_CSW_PCIE1W 0x1004U
+#define TSA_CONFIG_STATIC0_CSW_PCIE2AW 0x1008U
+#define TSA_CONFIG_STATIC0_CSW_PCIE3W 0x100cU
+#define TSA_CONFIG_STATIC0_CSW_PCIE4W 0x1028U
+#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x2004U
+#define TSA_CONFIG_STATIC0_CSR_SATAR 0x2010U
+#define TSA_CONFIG_STATIC0_CSW_SATAW 0x2014U
+#define TSA_CONFIG_STATIC0_CSW_PCIE0W 0x2020U
+#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x202cU
+#define TSA_CONFIG_STATIC0_CSW_NVENC1SWR 0x3004U
+#define TSA_CONFIG_STATIC0_CSW_NVENCSWR 0x3010U
+#define TSA_CONFIG_STATIC0_CSW_NVDEC1SWR 0x4004U
+#define TSA_CONFIG_STATIC0_CSR_ISPFALR 0x4010U
+#define TSA_CONFIG_STATIC0_CSW_ISPWA 0x4014U
+#define TSA_CONFIG_STATIC0_CSW_ISPWB 0x4018U
+#define TSA_CONFIG_STATIC0_CSW_ISPFALW 0x401cU
+#define TSA_CONFIG_STATIC0_CSW_NVDECSWR 0x5004U
+#define TSA_CONFIG_STATIC0_CSR_EQOSR 0x5010U
+#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x5014U
+#define TSA_CONFIG_STATIC0_CSR_SDMMCRAB 0x5020U
+#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5024U
+#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6004U
+#define TSA_CONFIG_STATIC0_CSR_SDMMCR 0x6010U
+#define TSA_CONFIG_STATIC0_CSR_SDMMCRA 0x6014U
+#define TSA_CONFIG_STATIC0_CSW_SDMMCW 0x6018U
+#define TSA_CONFIG_STATIC0_CSW_SDMMCWA 0x601cU
+#define TSA_CONFIG_STATIC0_CSR_RCER 0x6030U
+#define TSA_CONFIG_STATIC0_CSR_RCEDMAR 0x6034U
+#define TSA_CONFIG_STATIC0_CSW_RCEW 0x6038U
+#define TSA_CONFIG_STATIC0_CSW_RCEDMAW 0x603cU
+#define TSA_CONFIG_STATIC0_CSR_SCER 0x6050U
+#define TSA_CONFIG_STATIC0_CSR_SCEDMAR 0x6054U
+#define TSA_CONFIG_STATIC0_CSW_SCEW 0x6058U
+#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x605cU
+#define TSA_CONFIG_STATIC0_CSR_AXIAPR 0x7004U
+#define TSA_CONFIG_STATIC0_CSR_ETRR 0x7008U
+#define TSA_CONFIG_STATIC0_CSR_HOST1XDMAR 0x700cU
+#define TSA_CONFIG_STATIC0_CSW_AXIAPW 0x7010U
+#define TSA_CONFIG_STATIC0_CSW_ETRW 0x7014U
+#define TSA_CONFIG_STATIC0_CSR_NVJPGSRD 0x8004U
+#define TSA_CONFIG_STATIC0_CSW_NVJPGSWR 0x8008U
+#define TSA_CONFIG_STATIC0_CSR_AXISR 0x8014U
+#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8018U
+#define TSA_CONFIG_STATIC0_CSR_BPMPR 0x9004U
+#define TSA_CONFIG_STATIC0_CSR_BPMPDMAR 0x9008U
+#define TSA_CONFIG_STATIC0_CSW_BPMPW 0x900cU
+#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9010U
+#define TSA_CONFIG_STATIC0_CSR_SESRD 0x9024U
+#define TSA_CONFIG_STATIC0_CSR_TSECSRD 0x9028U
+#define TSA_CONFIG_STATIC0_CSR_TSECSRDB 0x902cU
+#define TSA_CONFIG_STATIC0_CSW_SESWR 0x9030U
+#define TSA_CONFIG_STATIC0_CSW_TSECSWR 0x9034U
+#define TSA_CONFIG_STATIC0_CSW_TSECSWRB 0x9038U
+#define TSA_CONFIG_STATIC0_CSW_PCIE5W 0xb004U
+#define TSA_CONFIG_STATIC0_CSW_VICSWR 0xc004U
+#define TSA_CONFIG_STATIC0_CSR_APER 0xd004U
+#define TSA_CONFIG_STATIC0_CSR_APEDMAR 0xd008U
+#define TSA_CONFIG_STATIC0_CSW_APEW 0xd00cU
+#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xd010U
+#define TSA_CONFIG_STATIC0_CSR_HDAR 0xf004U
+#define TSA_CONFIG_STATIC0_CSW_HDAW 0xf008U
+#define TSA_CONFIG_STATIC0_CSR_NVDISPLAYR 0xf014U
+#define TSA_CONFIG_STATIC0_CSR_VIFALR 0x10004U
+#define TSA_CONFIG_STATIC0_CSW_VIW 0x10008U
+#define TSA_CONFIG_STATIC0_CSW_VIFALW 0x1000cU
+#define TSA_CONFIG_STATIC0_CSR_AONR 0x12004U
+#define TSA_CONFIG_STATIC0_CSR_AONDMAR 0x12008U
+#define TSA_CONFIG_STATIC0_CSW_AONW 0x1200cU
+#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0x12010U
+#define TSA_CONFIG_STATIC0_CSR_PCIE1R 0x14004U
+#define TSA_CONFIG_STATIC0_CSR_PCIE2AR 0x14008U
+#define TSA_CONFIG_STATIC0_CSR_PCIE3R 0x1400cU
+#define TSA_CONFIG_STATIC0_CSR_PCIE4R 0x14028U
+#define TSA_CONFIG_STATIC0_CSR_XUSB_DEVR 0x15004U
+#define TSA_CONFIG_STATIC0_CSR_XUSB_HOSTR 0x15010U
+#define TSA_CONFIG_STATIC0_CSR_UFSHCR 0x16004U
+#define TSA_CONFIG_STATIC0_CSW_DLA1WRA 0x18004U
+#define TSA_CONFIG_STATIC0_CSR_DLA1FALRDB 0x18010U
+#define TSA_CONFIG_STATIC0_CSW_DLA1FALWRB 0x18014U
+#define TSA_CONFIG_STATIC0_CSW_DLA0WRA 0x19004U
+#define TSA_CONFIG_STATIC0_CSR_DLA0FALRDB 0x19010U
+#define TSA_CONFIG_STATIC0_CSW_DLA0FALWRB 0x19014U
+#define TSA_CONFIG_STATIC0_CSR_PVA1RDC 0x1a004U
+#define TSA_CONFIG_STATIC0_CSW_PVA1WRC 0x1a008U
+#define TSA_CONFIG_STATIC0_CSW_PVA1WRA 0x1a014U
+#define TSA_CONFIG_STATIC0_CSW_PVA1WRB 0x1a020U
+#define TSA_CONFIG_STATIC0_CSW_PVA0WRB 0x1b004U
+#define TSA_CONFIG_STATIC0_CSR_PVA0RDC 0x1b010U
+#define TSA_CONFIG_STATIC0_CSW_PVA0WRC 0x1b014U
+#define TSA_CONFIG_STATIC0_CSW_PVA0WRA 0x1b020U
+#define TSA_CONFIG_STATIC0_CSR_NVENC1SRD 0x1d004U
+#define TSA_CONFIG_STATIC0_CSR_NVENCSRD 0x1d010U
+#define TSA_CONFIG_STATIC0_CSR_NVDEC1SRD 0x1e004U
+#define TSA_CONFIG_STATIC0_CSR_ISPRA 0x1e010U
+#define TSA_CONFIG_STATIC0_CSR_NVDECSRD 0x1f004U
+#define TSA_CONFIG_STATIC0_CSR_PCIE0R 0x21004U
+#define TSA_CONFIG_STATIC0_CSR_PCIE5R 0x23004U
+#define TSA_CONFIG_STATIC0_CSR_VICSRD 0x24004U
+#define TSA_CONFIG_STATIC0_CSR_DLA1RDA 0x26004U
+#define TSA_CONFIG_STATIC0_CSR_DLA0RDA 0x27004U
+#define TSA_CONFIG_STATIC0_CSR_PVA1RDA 0x28004U
+#define TSA_CONFIG_STATIC0_CSR_PVA1RDB 0x28010U
+#define TSA_CONFIG_STATIC0_CSR_PVA0RDB 0x29004U
+#define TSA_CONFIG_STATIC0_CSR_PVA0RDA 0x29010U
+
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11)
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11)
+
+#endif /* __TEGRA_MC_DEF_H__ */
diff --git a/plat/nvidia/tegra/scat/bl31.scat b/plat/nvidia/tegra/scat/bl31.scat
index 2f5fd9e..2d6d2b3 100644
--- a/plat/nvidia/tegra/scat/bl31.scat
+++ b/plat/nvidia/tegra/scat/bl31.scat
@@ -95,7 +95,7 @@
/* cpu_ops must always be defined */
ScatterAssert(ImageLength(__CPU_OPS__) > 0)
-#if ENABLE_SPM
+#if SPM_MM
LR_SPM +0
{
/*
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index 948fade..1188a3b 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -66,10 +66,10 @@
<< TEGRA194_WAKE_TIME_SHIFT;
/*
- * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that
- * the correct value is read in tegra_soc_pwr_domain_suspend(), which
- * is called with caches disabled. It is possible to read a stale value
- * from DRAM in that function, because the L2 cache is not flushed
+ * Clean t19x_percpu_data[cpu] to DRAM. This needs to be done to ensure
+ * that the correct value is read in tegra_soc_pwr_domain_suspend(),
+ * which is called with caches disabled. It is possible to read a stale
+ * value from DRAM in that function, because the L2 cache is not flushed
* unless the cluster is entering CC6/CC7.
*/
clean_dcache_range((uint64_t)&t19x_percpu_data[cpu],
@@ -125,7 +125,7 @@
val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
(uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7;
ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
- percpu_data[cpu].wake_time, 0);
+ t19x_percpu_data[cpu].wake_time, 0);
assert(ret == 0);
} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c
index 1696d59..640ef4d 100644
--- a/plat/nvidia/tegra/soc/t194/plat_smmu.c
+++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c
@@ -270,143 +270,8 @@
mc_make_sid_override_cfg(MIU2W),
mc_make_sid_override_cfg(MIU3R),
mc_make_sid_override_cfg(MIU3W),
- smmu_make_gnsr0_nsec_cfg(CR0),
- smmu_make_gnsr0_sec_cfg(IDR0),
- smmu_make_gnsr0_sec_cfg(IDR1),
- smmu_make_gnsr0_sec_cfg(IDR2),
- smmu_make_gnsr0_nsec_cfg(GFSR),
- smmu_make_gnsr0_nsec_cfg(GFSYNR0),
- smmu_make_gnsr0_nsec_cfg(GFSYNR1),
- smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
- smmu_make_gnsr0_nsec_cfg(PIDR2),
- smmu_make_smrg_group(0),
- smmu_make_smrg_group(1),
- smmu_make_smrg_group(2),
- smmu_make_smrg_group(3),
- smmu_make_smrg_group(4),
- smmu_make_smrg_group(5),
- smmu_make_smrg_group(6),
- smmu_make_smrg_group(7),
- smmu_make_smrg_group(8),
- smmu_make_smrg_group(9),
- smmu_make_smrg_group(10),
- smmu_make_smrg_group(11),
- smmu_make_smrg_group(12),
- smmu_make_smrg_group(13),
- smmu_make_smrg_group(14),
- smmu_make_smrg_group(15),
- smmu_make_smrg_group(16),
- smmu_make_smrg_group(17),
- smmu_make_smrg_group(18),
- smmu_make_smrg_group(19),
- smmu_make_smrg_group(20),
- smmu_make_smrg_group(21),
- smmu_make_smrg_group(22),
- smmu_make_smrg_group(23),
- smmu_make_smrg_group(24),
- smmu_make_smrg_group(25),
- smmu_make_smrg_group(26),
- smmu_make_smrg_group(27),
- smmu_make_smrg_group(28),
- smmu_make_smrg_group(29),
- smmu_make_smrg_group(30),
- smmu_make_smrg_group(31),
- smmu_make_smrg_group(32),
- smmu_make_smrg_group(33),
- smmu_make_smrg_group(34),
- smmu_make_smrg_group(35),
- smmu_make_smrg_group(36),
- smmu_make_smrg_group(37),
- smmu_make_smrg_group(38),
- smmu_make_smrg_group(39),
- smmu_make_smrg_group(40),
- smmu_make_smrg_group(41),
- smmu_make_smrg_group(42),
- smmu_make_smrg_group(43),
- smmu_make_smrg_group(44),
- smmu_make_smrg_group(45),
- smmu_make_smrg_group(46),
- smmu_make_smrg_group(47),
- smmu_make_smrg_group(48),
- smmu_make_smrg_group(49),
- smmu_make_smrg_group(50),
- smmu_make_smrg_group(51),
- smmu_make_smrg_group(52),
- smmu_make_smrg_group(53),
- smmu_make_smrg_group(54),
- smmu_make_smrg_group(55),
- smmu_make_smrg_group(56),
- smmu_make_smrg_group(57),
- smmu_make_smrg_group(58),
- smmu_make_smrg_group(59),
- smmu_make_smrg_group(60),
- smmu_make_smrg_group(61),
- smmu_make_smrg_group(62),
- smmu_make_smrg_group(63),
- smmu_make_cb_group(0),
- smmu_make_cb_group(1),
- smmu_make_cb_group(2),
- smmu_make_cb_group(3),
- smmu_make_cb_group(4),
- smmu_make_cb_group(5),
- smmu_make_cb_group(6),
- smmu_make_cb_group(7),
- smmu_make_cb_group(8),
- smmu_make_cb_group(9),
- smmu_make_cb_group(10),
- smmu_make_cb_group(11),
- smmu_make_cb_group(12),
- smmu_make_cb_group(13),
- smmu_make_cb_group(14),
- smmu_make_cb_group(15),
- smmu_make_cb_group(16),
- smmu_make_cb_group(17),
- smmu_make_cb_group(18),
- smmu_make_cb_group(19),
- smmu_make_cb_group(20),
- smmu_make_cb_group(21),
- smmu_make_cb_group(22),
- smmu_make_cb_group(23),
- smmu_make_cb_group(24),
- smmu_make_cb_group(25),
- smmu_make_cb_group(26),
- smmu_make_cb_group(27),
- smmu_make_cb_group(28),
- smmu_make_cb_group(29),
- smmu_make_cb_group(30),
- smmu_make_cb_group(31),
- smmu_make_cb_group(32),
- smmu_make_cb_group(33),
- smmu_make_cb_group(34),
- smmu_make_cb_group(35),
- smmu_make_cb_group(36),
- smmu_make_cb_group(37),
- smmu_make_cb_group(38),
- smmu_make_cb_group(39),
- smmu_make_cb_group(40),
- smmu_make_cb_group(41),
- smmu_make_cb_group(42),
- smmu_make_cb_group(43),
- smmu_make_cb_group(44),
- smmu_make_cb_group(45),
- smmu_make_cb_group(46),
- smmu_make_cb_group(47),
- smmu_make_cb_group(48),
- smmu_make_cb_group(49),
- smmu_make_cb_group(50),
- smmu_make_cb_group(51),
- smmu_make_cb_group(52),
- smmu_make_cb_group(53),
- smmu_make_cb_group(54),
- smmu_make_cb_group(55),
- smmu_make_cb_group(56),
- smmu_make_cb_group(57),
- smmu_make_cb_group(58),
- smmu_make_cb_group(59),
- smmu_make_cb_group(60),
- smmu_make_cb_group(61),
- smmu_make_cb_group(62),
- smmu_make_cb_group(63),
+ smmu_make_cfg(TEGRA_SMMU0_BASE),
+ smmu_make_cfg(TEGRA_SMMU2_BASE),
smmu_bypass_cfg, /* TBU settings */
_END_OF_TABLE_,
};
diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S
index 33c7e6f..696a577 100644
--- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S
@@ -12,7 +12,7 @@
#define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7
#define TEGRA194_STATE_SYSTEM_RESUME 0x600D
-#define TEGRA194_SMMU_CTX_SIZE 0x490
+#define TEGRA194_SMMU_CTX_SIZE 0x80B
.align 4
.globl tegra194_cpu_reset_handler
diff --git a/plat/rockchip/px30/drivers/pmu/pmu.c b/plat/rockchip/px30/drivers/pmu/pmu.c
index 0a2515d..5f4e64f 100644
--- a/plat/rockchip/px30/drivers/pmu/pmu.c
+++ b/plat/rockchip/px30/drivers/pmu/pmu.c
@@ -22,6 +22,7 @@
#include <plat_private.h>
#include <pmu.h>
#include <px30_def.h>
+#include <secure.h>
#include <soc.h>
DEFINE_BAKERY_LOCK(rockchip_pd_lock);
diff --git a/plat/rockchip/px30/drivers/secure/secure.c b/plat/rockchip/px30/drivers/secure/secure.c
new file mode 100644
index 0000000..144f945
--- /dev/null
+++ b/plat/rockchip/px30/drivers/secure/secure.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <ddr_parameter.h>
+#include <plat_private.h>
+#include <secure.h>
+#include <px30_def.h>
+
+/**
+ * There are 8 regions for DDR security control
+ * @rgn - the DDR regions 0 ~ 7 which are can be configured.
+ * @st - start address to set as secure
+ * @sz - length of area to set as secure
+ * The internal unit is megabytes, so memory areas need to be aligned
+ * to megabyte borders.
+ */
+static void secure_ddr_region(uint32_t rgn,
+ uintptr_t st, size_t sz)
+{
+ uintptr_t ed = st + sz;
+ uintptr_t st_mb, ed_mb;
+ uint32_t val;
+
+ assert(rgn <= 7);
+ assert(st < ed);
+
+ /* check aligned 1MB */
+ assert(st % SIZE_M(1) == 0);
+ assert(ed % SIZE_M(1) == 0);
+
+ st_mb = st / SIZE_M(1);
+ ed_mb = ed / SIZE_M(1);
+
+ /* map top and base */
+ mmio_write_32(FIREWALL_DDR_BASE +
+ FIREWALL_DDR_FW_DDR_RGN(rgn),
+ RG_MAP_SECURE(ed_mb, st_mb));
+
+ /* enable secure */
+ val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG);
+ val |= BIT(rgn);
+ mmio_write_32(FIREWALL_DDR_BASE +
+ FIREWALL_DDR_FW_DDR_CON_REG, val);
+}
+
+void secure_timer_init(void)
+{
+ mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
+ TIMER_DIS);
+
+ mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);
+ mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);
+
+ /* auto reload & enable the timer */
+ mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
+ TIMER_EN | TIMER_FMODE);
+}
+
+void sgrf_init(void)
+{
+#ifdef PLAT_RK_SECURE_DDR_MINILOADER
+ uint32_t i;
+ struct param_ddr_usage usg;
+
+ /* general secure regions */
+ usg = ddr_region_usage_parse(DDR_PARAM_BASE,
+ PLAT_MAX_DDR_CAPACITY_MB);
+
+ /* region-0 for TF-A, region-1 for optional OP-TEE */
+ assert(usg.s_nr < 7);
+
+ for (i = 0; i < usg.s_nr; i++)
+ secure_ddr_region(7 - i, usg.s_top[i], usg.s_base[i]);
+#endif
+
+ /* secure the trustzone ram */
+ secure_ddr_region(0, TZRAM_BASE, TZRAM_SIZE);
+
+ /* set all slave ip into no-secure, except stimer */
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS);
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS);
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS);
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS);
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000);
+
+ /* set master crypto to no-secure, dcf to secure */
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003);
+
+ /* set DMAC into no-secure */
+ mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS);
+ mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0);
+ mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16);
+ mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS);
+
+ /* soft reset dma before use */
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ);
+ udelay(5);
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS);
+}
diff --git a/plat/rockchip/px30/drivers/secure/secure.h b/plat/rockchip/px30/drivers/secure/secure.h
new file mode 100644
index 0000000..498027d
--- /dev/null
+++ b/plat/rockchip/px30/drivers/secure/secure.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SECURE_H
+#define SECURE_H
+
+/***************************************************************************
+ * SGRF
+ ***************************************************************************/
+#define SGRF_SOC_CON(i) ((i) * 0x4)
+#define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4)
+
+#define SGRF_MST_S_ALL_NS 0xffffffff
+#define SGRF_SLV_S_ALL_NS 0xffff0000
+#define DMA_IRQ_BOOT_NS 0xffffffff
+#define DMA_PERI_CH_NS_15_0 0xffffffff
+#define DMA_PERI_CH_NS_19_16 0x000f000f
+#define DMA_MANAGER_BOOT_NS 0x00010001
+#define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12)
+#define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12)
+
+/***************************************************************************
+ * DDR FIREWALL
+ ***************************************************************************/
+#define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4)
+#define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4)
+#define FIREWALL_DDR_FW_DDR_CON_REG 0x40
+#define FIREWALL_DDR_FW_DDR_RGN_NUM 8
+#define FIREWALL_DDR_FW_DDR_MST_NUM 6
+
+#define PLAT_MAX_DDR_CAPACITY_MB 4096
+#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
+
+/**************************************************
+ * secure timer
+ **************************************************/
+
+/* chanal0~5 */
+#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
+
+#define TIMER_LOAD_COUNT0 0x0
+#define TIMER_LOAD_COUNT1 0x4
+
+#define TIMER_CUR_VALUE0 0x8
+#define TIMER_CUR_VALUE1 0xc
+
+#define TIMER_CONTROL_REG 0x10
+#define TIMER_INTSTATUS 0x18
+
+#define TIMER_DIS 0x0
+#define TIMER_EN 0x1
+
+#define TIMER_FMODE (0x0 << 1)
+#define TIMER_RMODE (0x1 << 1)
+
+#define TIMER_LOAD_COUNT0_MSK (0xffffffff)
+#define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000)
+
+void secure_timer_init(void);
+void sgrf_init(void);
+
+#endif /* SECURE_H */
diff --git a/plat/rockchip/px30/drivers/soc/soc.c b/plat/rockchip/px30/drivers/soc/soc.c
index e00561d..200563d 100644
--- a/plat/rockchip/px30/drivers/soc/soc.c
+++ b/plat/rockchip/px30/drivers/soc/soc.c
@@ -12,10 +12,10 @@
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
-#include <ddr_parameter.h>
#include <platform_def.h>
#include <pmu.h>
#include <px30_def.h>
+#include <secure.h>
#include <soc.h>
#include <rockchip_sip_svc.h>
@@ -83,65 +83,6 @@
0xffff0000);
}
-void secure_timer_init(void)
-{
- mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
- TIMER_DIS);
-
- mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);
- mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);
-
- /* auto reload & enable the timer */
- mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
- TIMER_EN | TIMER_FMODE);
-}
-
-static void sgrf_init(void)
-{
- uint32_t i, val;
- struct param_ddr_usage usg;
-
- /* general secure regions */
- usg = ddr_region_usage_parse(DDR_PARAM_BASE,
- PLAT_MAX_DDR_CAPACITY_MB);
- for (i = 0; i < usg.s_nr; i++) {
- /* enable secure */
- val = mmio_read_32(FIREWALL_DDR_BASE +
- FIREWALL_DDR_FW_DDR_CON_REG);
- val |= BIT(7 - i);
- mmio_write_32(FIREWALL_DDR_BASE +
- FIREWALL_DDR_FW_DDR_CON_REG, val);
- /* map top and base */
- mmio_write_32(FIREWALL_DDR_BASE +
- FIREWALL_DDR_FW_DDR_RGN(7 - i),
- RG_MAP_SECURE(usg.s_top[i], usg.s_base[i]));
- }
-
- /* set ddr rgn0_top and rga0_top as 0 */
- mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
-
- /* set all slave ip into no-secure, except stimer */
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS);
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS);
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS);
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS);
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000);
-
- /* set master crypto to no-secure, dcf to secure */
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003);
-
- /* set DMAC into no-secure */
- mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS);
- mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0);
- mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16);
- mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS);
-
- /* soft reset dma before use */
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ);
- udelay(5);
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS);
-}
-
static void soc_reset_config_all(void)
{
uint32_t tmp;
diff --git a/plat/rockchip/px30/drivers/soc/soc.h b/plat/rockchip/px30/drivers/soc/soc.h
index 69f2de4..648d18b 100644
--- a/plat/rockchip/px30/drivers/soc/soc.h
+++ b/plat/rockchip/px30/drivers/soc/soc.h
@@ -29,21 +29,6 @@
};
/***************************************************************************
- * SGRF
- ***************************************************************************/
-#define SGRF_SOC_CON(i) ((i) * 0x4)
-#define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4)
-
-#define SGRF_MST_S_ALL_NS 0xffffffff
-#define SGRF_SLV_S_ALL_NS 0xffff0000
-#define DMA_IRQ_BOOT_NS 0xffffffff
-#define DMA_PERI_CH_NS_15_0 0xffffffff
-#define DMA_PERI_CH_NS_19_16 0x000f000f
-#define DMA_MANAGER_BOOT_NS 0x00010001
-#define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12)
-#define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12)
-
-/***************************************************************************
* GRF
***************************************************************************/
#define GRF_SOC_CON(i) (0x0400 + (i) * 4)
@@ -61,18 +46,6 @@
#define GRF_SOC_CON2_NSWDT_RST_EN 12
/***************************************************************************
- * DDR FIREWALL
- ***************************************************************************/
-#define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4)
-#define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4)
-#define FIREWALL_DDR_FW_DDR_CON_REG 0x40
-#define FIREWALL_DDR_FW_DDR_RGN_NUM 8
-#define FIREWALL_DDR_FW_DDR_MST_NUM 6
-
-#define PLAT_MAX_DDR_CAPACITY_MB 4096
-#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
-
-/***************************************************************************
* cru
***************************************************************************/
#define CRU_MODE 0xa0
@@ -136,37 +109,10 @@
#define GPIO_INT_STATUS 0x40
#define GPIO_NUMS 4
-/**************************************************
- * secure timer
- **************************************************/
-
-/* chanal0~5 */
-#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
-
-#define TIMER_LOAD_COUNT0 0x0
-#define TIMER_LOAD_COUNT1 0x4
-
-#define TIMER_CUR_VALUE0 0x8
-#define TIMER_CUR_VALUE1 0xc
-
-#define TIMER_CONTROL_REG 0x10
-#define TIMER_INTSTATUS 0x18
-
-#define TIMER_DIS 0x0
-#define TIMER_EN 0x1
-
-#define TIMER_FMODE (0x0 << 1)
-#define TIMER_RMODE (0x1 << 1)
-
-#define TIMER_LOAD_COUNT0_MSK (0xffffffff)
-#define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000)
-
void clk_gate_con_save(uint32_t *clkgt_save);
void clk_gate_con_restore(uint32_t *clkgt_save);
void clk_gate_con_disable(void);
-void secure_timer_init(void);
-void secure_timer_disable(void);
void px30_soc_reset_config(void);
#endif /* __SOC_H__ */
diff --git a/plat/rockchip/px30/include/platform_def.h b/plat/rockchip/px30/include/platform_def.h
index 9dccab8..2f4f672 100644
--- a/plat/rockchip/px30/include/platform_def.h
+++ b/plat/rockchip/px30/include/platform_def.h
@@ -69,9 +69,9 @@
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
-/* TF text, ro, rw, Size: 512KB */
+/* TF text, ro, rw, Size: 1MB */
#define TZRAM_BASE (0x0)
-#define TZRAM_SIZE (0x80000)
+#define TZRAM_SIZE (0x100000)
/*******************************************************************************
* BL31 specific defines.
diff --git a/plat/rockchip/px30/platform.mk b/plat/rockchip/px30/platform.mk
index ee85cd3..87cf187 100644
--- a/plat/rockchip/px30/platform.mk
+++ b/plat/rockchip/px30/platform.mk
@@ -20,6 +20,7 @@
-I${RK_PLAT_COMMON}/pmusram \
-I${RK_PLAT_SOC}/ \
-I${RK_PLAT_SOC}/drivers/pmu/ \
+ -I${RK_PLAT_SOC}/drivers/secure/ \
-I${RK_PLAT_SOC}/drivers/soc/ \
-I${RK_PLAT_SOC}/include/
@@ -45,16 +46,20 @@
${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
${RK_PLAT_COMMON}/aarch64/platform_common.c \
${RK_PLAT_COMMON}/bl31_plat_setup.c \
- ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \
${RK_PLAT_COMMON}/params_setup.c \
${RK_PLAT_COMMON}/pmusram/cpus_on_fixed_addr.S \
${RK_PLAT_COMMON}/plat_pm.c \
${RK_PLAT_COMMON}/plat_topology.c \
${RK_PLAT_COMMON}/rockchip_sip_svc.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
+ ${RK_PLAT_SOC}/drivers/secure/secure.c \
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/plat_sip_calls.c
+ifdef PLAT_RK_SECURE_DDR_MINILOADER
+BL31_SOURCES += ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c
+endif
+
ENABLE_PLAT_COMPAT := 0
MULTI_CONSOLE_API := 1
diff --git a/plat/rockchip/px30/px30_def.h b/plat/rockchip/px30/px30_def.h
index 283b606..efe789e 100644
--- a/plat/rockchip/px30/px30_def.h
+++ b/plat/rockchip/px30/px30_def.h
@@ -11,6 +11,7 @@
#define MINOR_VERSION (0)
#define SIZE_K(n) ((n) * 1024)
+#define SIZE_M(n) ((n) * 1024 * 1024)
#define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits))
diff --git a/plat/rockchip/rk3288/drivers/secure/secure.c b/plat/rockchip/rk3288/drivers/secure/secure.c
index 68994e4..25e1cca 100644
--- a/plat/rockchip/rk3288/drivers/secure/secure.c
+++ b/plat/rockchip/rk3288/drivers/secure/secure.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -38,15 +38,18 @@
* SGRF_SOC_CON21 - end address of the RGN_7 + RGN_X control
*
* @rgn - the DDR regions 0 ~ 7 which are can be configured.
- * The @st and @ed indicate the start and end addresses for which to set
- * the security, and the unit is byte. When the st_mb == 0, ed_mb == 0, the
+ * @st - start address to set as secure
+ * @sz - length of area to set as secure
+ * The @st_mb and @ed_mb indicate the start and end addresses for which to set
+ * the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
* address range 0x0 ~ 0xfffff is secure.
*
* For example, if we would like to set the range [0, 32MB) is security via
* DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
*/
-static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, uintptr_t ed)
+static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, size_t sz)
{
+ uintptr_t ed = st + sz;
uintptr_t st_mb, ed_mb;
assert(rgn <= 7);
diff --git a/plat/rockchip/rk3328/drivers/soc/soc.c b/plat/rockchip/rk3328/drivers/soc/soc.c
index 59d8572..306308f 100644
--- a/plat/rockchip/rk3328/drivers/soc/soc.c
+++ b/plat/rockchip/rk3328/drivers/soc/soc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -97,6 +97,7 @@
void sgrf_init(void)
{
+#ifdef PLAT_RK_SECURE_DDR_MINILOADER
uint32_t i, val;
struct param_ddr_usage usg;
@@ -115,6 +116,7 @@
FIREWALL_DDR_FW_DDR_RGN(7 - i),
RG_MAP_SECURE(usg.s_top[i], usg.s_base[i]));
}
+#endif
/* set ddr rgn0_top and rga0_top as 0 */
mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h
index baac12d..e9eb3fa 100644
--- a/plat/rockchip/rk3328/include/platform_def.h
+++ b/plat/rockchip/rk3328/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -66,9 +66,9 @@
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
-/* TF text, ro, rw, Size: 512KB */
+/* TF text, ro, rw, Size: 1MB */
#define TZRAM_BASE (0x0)
-#define TZRAM_SIZE (0x80000)
+#define TZRAM_SIZE (0x100000)
/*******************************************************************************
* BL31 specific defines.
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index 0da4f2d..0c5cfae 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -42,7 +42,6 @@
drivers/delay_timer/generic_delay_timer.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
- ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \
${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
${RK_PLAT_COMMON}/params_setup.c \
${RK_PLAT_COMMON}/bl31_plat_setup.c \
@@ -53,6 +52,10 @@
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/soc/soc.c
+ifdef PLAT_RK_SECURE_DDR_MINILOADER
+BL31_SOURCES += ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c
+endif
+
include lib/coreboot/coreboot.mk
include lib/libfdt/libfdt.mk
diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h
index 9334a83..2abd56b 100644
--- a/plat/rockchip/rk3368/include/platform_def.h
+++ b/plat/rockchip/rk3368/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -67,9 +67,9 @@
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
-/* TF text, ro, rw, Size: 512KB */
+/* TF text, ro, rw, Size: 1MB */
#define TZRAM_BASE (0x0)
-#define TZRAM_SIZE (0x80000)
+#define TZRAM_SIZE (0x100000)
/*******************************************************************************
* BL31 specific defines.
diff --git a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c
index aa71fde..a8773f4 100644
--- a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c
+++ b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c
@@ -18,7 +18,7 @@
".global hdcp_handler\n"
".balign 4\n"
"hdcp_handler:\n"
- ".incbin \"" __XSTRING(HDCPFW) "\"\n"
+ ".incbin \"" HDCPFW "\"\n"
".type hdcp_handler, %function\n"
".size hdcp_handler, .- hdcp_handler\n"
".popsection\n"
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index 30941fd..faee678 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -400,6 +400,25 @@
clk_gate_con_restore();
}
+void pmu_power_domains_on(void)
+{
+ clk_gate_con_disable();
+ pmu_set_power_domain(PD_VDU, pmu_pd_on);
+ pmu_set_power_domain(PD_VCODEC, pmu_pd_on);
+ pmu_set_power_domain(PD_RGA, pmu_pd_on);
+ pmu_set_power_domain(PD_IEP, pmu_pd_on);
+ pmu_set_power_domain(PD_EDP, pmu_pd_on);
+ pmu_set_power_domain(PD_GMAC, pmu_pd_on);
+ pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on);
+ pmu_set_power_domain(PD_HDCP, pmu_pd_on);
+ pmu_set_power_domain(PD_ISP1, pmu_pd_on);
+ pmu_set_power_domain(PD_ISP0, pmu_pd_on);
+ pmu_set_power_domain(PD_VO, pmu_pd_on);
+ pmu_set_power_domain(PD_TCPD1, pmu_pd_on);
+ pmu_set_power_domain(PD_TCPD0, pmu_pd_on);
+ pmu_set_power_domain(PD_GPU, pmu_pd_on);
+}
+
void rk3399_flush_l2_b(void)
{
uint32_t wait_cnt = 0;
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h
index 74db82f..bb7de50 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.h
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h
@@ -136,5 +136,6 @@
extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT];
extern void sram_func_set_ddrctl_pll(uint32_t pll_src);
+void pmu_power_domains_on(void);
#endif /* PMU_H */
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c b/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c
index a09ad21..25596b1 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c
@@ -5,20 +5,18 @@
*/
/* convoluted way to make sure that the define is pasted just the right way */
-#define _INCBIN(file, sym, sec) \
+#define INCBIN(file, sym, sec) \
__asm__( \
- ".section " #sec "\n" \
- ".global " #sym "\n" \
- ".type " #sym ", %object\n" \
+ ".section " sec "\n" \
+ ".global " sym "\n" \
+ ".type " sym ", %object\n" \
".align 4\n" \
- #sym ":\n" \
- ".incbin \"" #file "\"\n" \
- ".size " #sym ", .-" #sym "\n" \
- ".global " #sym "_end\n" \
- #sym "_end:\n" \
+ sym ":\n" \
+ ".incbin \"" file "\"\n" \
+ ".size " sym ", .-" sym "\n" \
+ ".global " sym "_end\n" \
+ sym "_end:\n" \
)
-#define INCBIN(file, sym, sec) _INCBIN(file, sym, sec)
-
-INCBIN(RK3399M0FW, rk3399m0_bin, ".sram.incbin");
-INCBIN(RK3399M0PMUFW, rk3399m0pmu_bin, ".pmusram.incbin");
+INCBIN(RK3399M0FW, "rk3399m0_bin", ".sram.incbin");
+INCBIN(RK3399M0PMUFW, "rk3399m0pmu_bin", ".pmusram.incbin");
diff --git a/plat/rockchip/rk3399/drivers/secure/secure.c b/plat/rockchip/rk3399/drivers/secure/secure.c
index 8286f17..13c83ca 100644
--- a/plat/rockchip/rk3399/drivers/secure/secure.c
+++ b/plat/rockchip/rk3399/drivers/secure/secure.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -45,6 +45,8 @@
* bypass, 1: enable bypass
*
* @rgn - the DDR regions 0 ~ 7 which are can be configured.
+ * @st - start address to set as secure
+ * @sz - length of area to set as secure
* The @st_mb and @ed_mb indicate the start and end addresses for which to set
* the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
* address range 0x0 ~ 0xfffff is secure.
@@ -53,8 +55,9 @@
* DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
*/
static void sgrf_ddr_rgn_config(uint32_t rgn,
- uintptr_t st, uintptr_t ed)
+ uintptr_t st, size_t sz)
{
+ uintptr_t ed = st + sz;
uintptr_t st_mb, ed_mb;
assert(rgn <= 7);
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
index c877dbd..98b5ad6 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.c
+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
@@ -17,6 +17,7 @@
#include <dram.h>
#include <m0_ctl.h>
#include <plat_private.h>
+#include <pmu.h>
#include <rk3399_def.h>
#include <secure.h>
#include <soc.h>
@@ -327,6 +328,7 @@
void __dead2 soc_global_soft_reset(void)
{
+ pmu_power_domains_on();
set_pll_slow_mode(VPLL_ID);
set_pll_slow_mode(NPLL_ID);
set_pll_slow_mode(GPLL_ID);
diff --git a/plat/rockchip/rk3399/plat_sip_calls.c b/plat/rockchip/rk3399/plat_sip_calls.c
index c2cc5b1..ce8476c 100644
--- a/plat/rockchip/rk3399/plat_sip_calls.c
+++ b/plat/rockchip/rk3399/plat_sip_calls.c
@@ -56,17 +56,21 @@
void *handle,
u_register_t flags)
{
+#ifdef PLAT_RK_DP_HDCP
uint64_t x5, x6;
+#endif
switch (smc_fid) {
case RK_SIP_DDR_CFG:
SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4));
+#ifdef PLAT_RK_DP_HDCP
case RK_SIP_HDCP_CONTROL:
SMC_RET1(handle, dp_hdcp_ctrl(x1));
case RK_SIP_HDCP_KEY_DATA64:
x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5);
x6 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X6);
SMC_RET1(handle, dp_hdcp_store_key(x1, x2, x3, x4, x5, x6));
+#endif
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
SMC_RET1(handle, SMC_UNK);
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index cfc48e8..5a23d3c 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -56,7 +56,6 @@
${RK_PLAT_COMMON}/aarch64/platform_common.c \
${RK_PLAT_COMMON}/rockchip_sip_svc.c \
${RK_PLAT_SOC}/plat_sip_calls.c \
- ${RK_PLAT_SOC}/drivers/dp/cdn_dp.c \
${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c \
@@ -82,22 +81,26 @@
BUILD_M0 := ${BUILD_PLAT}/m0
RK3399M0FW=${BUILD_M0}/${PLAT_M0}.bin
-$(eval $(call add_define,RK3399M0FW))
+$(eval $(call add_define_val,RK3399M0FW,\"$(RK3399M0FW)\"))
RK3399M0PMUFW=${BUILD_M0}/${PLAT_M0}pmu.bin
-$(eval $(call add_define,RK3399M0PMUFW))
+$(eval $(call add_define_val,RK3399M0PMUFW,\"$(RK3399M0PMUFW)\"))
+
+ifdef PLAT_RK_DP_HDCP
+BL31_SOURCES += ${RK_PLAT_SOC}/drivers/dp/cdn_dp.c
HDCPFW=${RK_PLAT_SOC}/drivers/dp/hdcp.bin
-$(eval $(call add_define,HDCPFW))
+$(eval $(call add_define_val,HDCPFW,\"$(HDCPFW)\"))
+
+${BUILD_PLAT}/bl31/cdn_dp.o: CCACHE_EXTRAFILES=$(HDCPFW)
+${RK_PLAT_SOC}/drivers/dp/cdn_dp.c: $(HDCPFW)
+endif
# CCACHE_EXTRAFILES is needed because ccache doesn't handle .incbin
export CCACHE_EXTRAFILES
${BUILD_PLAT}/bl31/pmu_fw.o: CCACHE_EXTRAFILES=$(RK3399M0FW):$(RK3399M0PMUFW)
${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c: $(RK3399M0FW)
-${BUILD_PLAT}/bl31/cdn_dp.o: CCACHE_EXTRAFILES=$(HDCPFW)
-${RK_PLAT_SOC}/drivers/dp/cdn_dp.c: $(HDCPFW)
-
$(eval $(call MAKE_PREREQ_DIR,${BUILD_M0},${BUILD_PLAT}))
.PHONY: $(RK3399M0FW)
$(RK3399M0FW): | ${BUILD_M0}
diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk
index fe1448f..ab1f69e 100644
--- a/plat/socionext/synquacer/platform.mk
+++ b/plat/socionext/synquacer/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -57,7 +57,7 @@
drivers/arm/css/mhu/css_mhu_doorbell.c
endif
-ifeq (${ENABLE_SPM},1)
+ifeq (${SPM_MM},1)
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
BL31_SOURCES += $(PLAT_PATH)/sq_spm.c
diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c
index c78fe91..b864021 100644
--- a/plat/socionext/synquacer/sq_bl31_setup.c
+++ b/plat/socionext/synquacer/sq_bl31_setup.c
@@ -159,7 +159,7 @@
void bl31_plat_arch_setup(void)
{
static const mmap_region_t secure_partition_mmap[] = {
-#if ENABLE_SPM && SPM_MM
+#if SPM_MM
MAP_REGION_FLAT(PLAT_SPM_BUF_BASE,
PLAT_SPM_BUF_SIZE,
MT_RW_DATA | MT_SECURE),
@@ -173,7 +173,7 @@
sq_mmap_setup(BL31_BASE, BL31_SIZE, secure_partition_mmap);
enable_mmu_el3(XLAT_TABLE_NC);
-#if ENABLE_SPM && SPM_MM
+#if SPM_MM
memcpy((void *)SPM_SHIM_EXCEPTIONS_START,
(void *)SPM_SHIM_EXCEPTIONS_LMA,
(uintptr_t)SPM_SHIM_EXCEPTIONS_END -
diff --git a/plat/socionext/synquacer/sq_spm.c b/plat/socionext/synquacer/sq_spm.c
index 01cce17..7bea111 100644
--- a/plat/socionext/synquacer/sq_spm.c
+++ b/plat/socionext/synquacer/sq_spm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,7 @@
#include <bl31/ehf.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
-#include <services/secure_partition.h>
+#include <services/spm_mm_partition.h>
static const mmap_region_t plat_arm_secure_partition_mmap[] = {
PLAT_SQ_FLASH_MMAP,
@@ -27,7 +27,7 @@
* Boot information passed to a secure partition during initialisation. Linear
* indices in MP information will be filled at runtime.
*/
-static secure_partition_mp_info_t sp_mp_info[] = {
+static spm_mm_mp_info_t sp_mp_info[] = {
{0x80000000, 0}, {0x80000001, 0}, {0x80000100, 0}, {0x80000101, 0},
{0x80000200, 0}, {0x80000201, 0}, {0x80000300, 0}, {0x80000301, 0},
{0x80000400, 0}, {0x80000401, 0}, {0x80000500, 0}, {0x80000501, 0},
@@ -36,10 +36,10 @@
{0x80000a00, 0}, {0x80000a01, 0}, {0x80000b00, 0}, {0x80000b01, 0},
};
-const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
+const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
.h.type = PARAM_SP_IMAGE_BOOT_INFO,
.h.version = VERSION_1,
- .h.size = sizeof(secure_partition_boot_info_t),
+ .h.size = sizeof(spm_mm_boot_info_t),
.h.attr = 0,
.sp_mem_base = BL32_BASE,
.sp_mem_limit = BL32_LIMIT,
@@ -63,7 +63,7 @@
return plat_arm_secure_partition_mmap;
}
-const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
+const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
void *cookie)
{
return &plat_arm_secure_partition_boot_info;
diff --git a/services/std_svc/spm/README.rst b/services/std_svc/spm/README.rst
deleted file mode 100644
index 63406a3..0000000
--- a/services/std_svc/spm/README.rst
+++ /dev/null
@@ -1,3 +0,0 @@
-This is a prototype loosely based on the SPCI Alpha and SPRT pre-alpha
-specifications. Any interface / platform API introduced for this is subject to
-change as it evolves.
diff --git a/services/std_svc/spm/aarch64/spm_helpers.S b/services/std_svc/spm/aarch64/spm_helpers.S
deleted file mode 100644
index aa35811..0000000
--- a/services/std_svc/spm/aarch64/spm_helpers.S
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include "../spm_private.h"
-
- .global spm_secure_partition_enter
- .global spm_secure_partition_exit
-
- /* ---------------------------------------------------------------------
- * This function is called with SP_EL0 as stack. Here we stash our EL3
- * callee-saved registers on to the stack as a part of saving the C
- * runtime and enter the secure payload.
- * 'x0' contains a pointer to the memory where the address of the C
- * runtime context is to be saved.
- * ---------------------------------------------------------------------
- */
-func spm_secure_partition_enter
- /* Make space for the registers that we're going to save */
- mov x3, sp
- str x3, [x0, #0]
- sub sp, sp, #SP_C_RT_CTX_SIZE
-
- /* Save callee-saved registers on to the stack */
- stp x19, x20, [sp, #SP_C_RT_CTX_X19]
- stp x21, x22, [sp, #SP_C_RT_CTX_X21]
- stp x23, x24, [sp, #SP_C_RT_CTX_X23]
- stp x25, x26, [sp, #SP_C_RT_CTX_X25]
- stp x27, x28, [sp, #SP_C_RT_CTX_X27]
- stp x29, x30, [sp, #SP_C_RT_CTX_X29]
-
- /* ---------------------------------------------------------------------
- * Everything is setup now. el3_exit() will use the secure context to
- * restore to the general purpose and EL3 system registers to ERET
- * into the secure payload.
- * ---------------------------------------------------------------------
- */
- b el3_exit
-endfunc spm_secure_partition_enter
-
- /* ---------------------------------------------------------------------
- * This function is called with 'x0' pointing to a C runtime context
- * saved in spm_secure_partition_enter().
- * It restores the saved registers and jumps to that runtime with 'x0'
- * as the new SP register. This destroys the C runtime context that had
- * been built on the stack below the saved context by the caller. Later
- * the second parameter 'x1' is passed as a return value to the caller.
- * ---------------------------------------------------------------------
- */
-func spm_secure_partition_exit
- /* Restore the previous stack */
- mov sp, x0
-
- /* Restore callee-saved registers on to the stack */
- ldp x19, x20, [x0, #(SP_C_RT_CTX_X19 - SP_C_RT_CTX_SIZE)]
- ldp x21, x22, [x0, #(SP_C_RT_CTX_X21 - SP_C_RT_CTX_SIZE)]
- ldp x23, x24, [x0, #(SP_C_RT_CTX_X23 - SP_C_RT_CTX_SIZE)]
- ldp x25, x26, [x0, #(SP_C_RT_CTX_X25 - SP_C_RT_CTX_SIZE)]
- ldp x27, x28, [x0, #(SP_C_RT_CTX_X27 - SP_C_RT_CTX_SIZE)]
- ldp x29, x30, [x0, #(SP_C_RT_CTX_X29 - SP_C_RT_CTX_SIZE)]
-
- /* ---------------------------------------------------------------------
- * This should take us back to the instruction after the call to the
- * last spm_secure_partition_enter().* Place the second parameter to x0
- * so that the caller will see it as a return value from the original
- * entry call.
- * ---------------------------------------------------------------------
- */
- mov x0, x1
- ret
-endfunc spm_secure_partition_exit
diff --git a/services/std_svc/spm/aarch64/spm_shim_exceptions.S b/services/std_svc/spm/aarch64/spm_shim_exceptions.S
deleted file mode 100644
index dab6150..0000000
--- a/services/std_svc/spm/aarch64/spm_shim_exceptions.S
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <context.h>
-
-/* -----------------------------------------------------------------------------
- * Very simple stackless exception handlers used by the spm shim layer.
- * -----------------------------------------------------------------------------
- */
- .globl spm_shim_exceptions_ptr
-
-vector_base spm_shim_exceptions_ptr, .spm_shim_exceptions
-
- /* -----------------------------------------------------
- * Current EL with SP0 : 0x0 - 0x200
- * -----------------------------------------------------
- */
-vector_entry SynchronousExceptionSP0, .spm_shim_exceptions
- b .
-end_vector_entry SynchronousExceptionSP0
-
-vector_entry IrqSP0, .spm_shim_exceptions
- b .
-end_vector_entry IrqSP0
-
-vector_entry FiqSP0, .spm_shim_exceptions
- b .
-end_vector_entry FiqSP0
-
-vector_entry SErrorSP0, .spm_shim_exceptions
- b .
-end_vector_entry SErrorSP0
-
- /* -----------------------------------------------------
- * Current EL with SPx: 0x200 - 0x400
- * -----------------------------------------------------
- */
-vector_entry SynchronousExceptionSPx, .spm_shim_exceptions
- b .
-end_vector_entry SynchronousExceptionSPx
-
-vector_entry IrqSPx, .spm_shim_exceptions
- b .
-end_vector_entry IrqSPx
-
-vector_entry FiqSPx, .spm_shim_exceptions
- b .
-end_vector_entry FiqSPx
-
-vector_entry SErrorSPx, .spm_shim_exceptions
- b .
-end_vector_entry SErrorSPx
-
- /* -----------------------------------------------------
- * Lower EL using AArch64 : 0x400 - 0x600. No exceptions
- * are handled since secure_partition does not implement
- * a lower EL
- * -----------------------------------------------------
- */
-vector_entry SynchronousExceptionA64, .spm_shim_exceptions
- msr tpidr_el1, x30
- mrs x30, esr_el1
- ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
-
- cmp x30, #EC_AARCH64_SVC
- b.eq do_smc
-
- cmp x30, #EC_AARCH32_SVC
- b.eq do_smc
-
- cmp x30, #EC_AARCH64_SYS
- b.eq handle_sys_trap
-
- /* Fail in all the other cases */
- b panic
-
- /* ---------------------------------------------
- * Tell SPM that we are done initialising
- * ---------------------------------------------
- */
-do_smc:
- mrs x30, tpidr_el1
- smc #0
- eret
-
- /* AArch64 system instructions trap are handled as a panic for now */
-handle_sys_trap:
-panic:
- b panic
-end_vector_entry SynchronousExceptionA64
-
-vector_entry IrqA64, .spm_shim_exceptions
- b .
-end_vector_entry IrqA64
-
-vector_entry FiqA64, .spm_shim_exceptions
- b .
-end_vector_entry FiqA64
-
-vector_entry SErrorA64, .spm_shim_exceptions
- b .
-end_vector_entry SErrorA64
-
- /* -----------------------------------------------------
- * Lower EL using AArch32 : 0x600 - 0x800
- * -----------------------------------------------------
- */
-vector_entry SynchronousExceptionA32, .spm_shim_exceptions
- b .
-end_vector_entry SynchronousExceptionA32
-
-vector_entry IrqA32, .spm_shim_exceptions
- b .
-end_vector_entry IrqA32
-
-vector_entry FiqA32, .spm_shim_exceptions
- b .
-end_vector_entry FiqA32
-
-vector_entry SErrorA32, .spm_shim_exceptions
- b .
-end_vector_entry SErrorA32
diff --git a/services/std_svc/spm/spci.c b/services/std_svc/spm/spci.c
deleted file mode 100644
index 2e12a6c..0000000
--- a/services/std_svc/spm/spci.c
+++ /dev/null
@@ -1,769 +0,0 @@
-/*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <lib/el3_runtime/context_mgmt.h>
-#include <lib/smccc.h>
-#include <lib/spinlock.h>
-#include <lib/utils.h>
-#include <services/spci_svc.h>
-#include <services/sprt_svc.h>
-#include <smccc_helpers.h>
-#include <sprt_host.h>
-
-#include "spm_private.h"
-
-/*******************************************************************************
- * Macros to print UUIDs.
- ******************************************************************************/
-#define PRINT_UUID_FORMAT "%08x-%08x-%08x-%08x"
-#define PRINT_UUID_ARGS(x) x[0], x[1], x[2], x[3]
-
-/*******************************************************************************
- * Array of structs that contains information about all handles of Secure
- * Services that are currently open.
- ******************************************************************************/
-typedef enum spci_handle_status {
- HANDLE_STATUS_CLOSED = 0,
- HANDLE_STATUS_OPEN,
-} spci_handle_status_t;
-
-typedef struct spci_handle {
- /* 16-bit value used as reference in all SPCI calls */
- uint16_t handle;
-
- /* Client ID of the client that requested the handle */
- uint16_t client_id;
-
- /* Current status of the handle */
- spci_handle_status_t status;
-
- /*
- * Context of the Secure Partition that provides the Secure Service
- * referenced by this handle.
- */
- sp_context_t *sp_ctx;
-
- /*
- * The same handle might be used for multiple requests, keep a reference
- * counter of them.
- */
- unsigned int num_active_requests;
-} spci_handle_t;
-
-static spci_handle_t spci_handles[PLAT_SPCI_HANDLES_MAX_NUM];
-static spinlock_t spci_handles_lock;
-
-/*
- * Given a handle and a client ID, return the element of the spci_handles
- * array that contains the information of the handle. It can only return open
- * handles. It returns NULL if it couldn't find the element in the array.
- */
-static spci_handle_t *spci_handle_info_get(uint16_t handle, uint16_t client_id)
-{
- size_t i;
-
- for (i = 0; i < ARRAY_SIZE(spci_handles); i++) {
- spci_handle_t *h = &(spci_handles[i]);
-
- /* Only check for open handles */
- if (h->status == HANDLE_STATUS_CLOSED) {
- continue;
- }
-
- /* Check if either the handle or the client ID are different */
- if ((h->handle != handle) || (h->client_id != client_id)) {
- continue;
- }
-
- return h;
- }
-
- return NULL;
-}
-
-/*
- * Returns a unique value for a handle. This function must be called while
- * spci_handles_lock is locked. It returns 0 on success, -1 on error.
- */
-static int spci_create_handle_value(uint16_t *handle)
-{
- /*
- * Trivial implementation that relies on the fact that any handle will
- * be closed before 2^16 more handles have been opened.
- */
- static uint16_t handle_count;
-
- *handle = handle_count;
-
- handle_count++;
-
- return 0;
-}
-
-/*******************************************************************************
- * Returns a unique token for a Secure Service request.
- ******************************************************************************/
-static uint32_t spci_create_token_value(void)
-{
- /*
- * Trivial implementation that relies on the fact that any response will
- * be read before 2^32 more service requests have been done.
- */
- static uint32_t token_count;
-
- return token_count++;
-}
-
-/*******************************************************************************
- * This function looks for a Secure Partition that has a Secure Service
- * identified by the given UUID. It returns a handle that the client can use to
- * access the service, and an SPCI_*** error code.
- ******************************************************************************/
-static uint64_t spci_service_handle_open_poll(void *handle, u_register_t x1,
- u_register_t x2, u_register_t x3, u_register_t x4,
- u_register_t x5, u_register_t x6, u_register_t x7)
-{
- unsigned int i;
- sp_context_t *sp_ptr;
- uint16_t service_handle;
-
- /* Bits 31:16 of w7 are reserved (MBZ). */
- assert((x7 & 0xFFFF0000U) == 0);
-
- uint16_t client_id = x7 & 0x0000FFFFU;
- uint32_t uuid[4] = { x1, x2, x3, x4 };
-
- /* Get pointer to the Secure Partition that handles this service */
- sp_ptr = spm_sp_get_by_uuid(&uuid);
- if (sp_ptr == NULL) {
- WARN("SPCI: Service requested by client 0x%04x not found\n",
- client_id);
- WARN("SPCI: UUID: " PRINT_UUID_FORMAT "\n",
- PRINT_UUID_ARGS(uuid));
-
- SMC_RET2(handle, SPCI_NOT_PRESENT, 0);
- }
-
- /* Get lock of the array of handles */
- spin_lock(&spci_handles_lock);
-
- /*
- * We need to record the client ID and Secure Partition that correspond
- * to this handle. Look for the first free entry in the array.
- */
- for (i = 0; i < PLAT_SPCI_HANDLES_MAX_NUM; i++) {
- if (spci_handles[i].status == HANDLE_STATUS_CLOSED) {
- break;
- }
- }
-
- if (i == PLAT_SPCI_HANDLES_MAX_NUM) {
- spin_unlock(&spci_handles_lock);
-
- WARN("SPCI: Can't open more handles. Client 0x%04x\n",
- client_id);
- WARN("SPCI: UUID: " PRINT_UUID_FORMAT "\n",
- PRINT_UUID_ARGS(uuid));
-
- SMC_RET2(handle, SPCI_NO_MEMORY, 0);
- }
-
- /* Create new handle value */
- if (spci_create_handle_value(&service_handle) != 0) {
- spin_unlock(&spci_handles_lock);
-
- WARN("SPCI: Can't create a new handle value. Client 0x%04x\n",
- client_id);
- WARN("SPCI: UUID: " PRINT_UUID_FORMAT "\n",
- PRINT_UUID_ARGS(uuid));
-
- SMC_RET2(handle, SPCI_NO_MEMORY, 0);
- }
-
- /* Save all information about this handle */
- spci_handles[i].status = HANDLE_STATUS_OPEN;
- spci_handles[i].client_id = client_id;
- spci_handles[i].handle = service_handle;
- spci_handles[i].num_active_requests = 0U;
- spci_handles[i].sp_ctx = sp_ptr;
-
- /* Release lock of the array of handles */
- spin_unlock(&spci_handles_lock);
-
- VERBOSE("SPCI: Service handle request by client 0x%04x: 0x%04x\n",
- client_id, service_handle);
- VERBOSE("SPCI: UUID: " PRINT_UUID_FORMAT "\n", PRINT_UUID_ARGS(uuid));
-
- /* The handle is returned in the top 16 bits of x1 */
- SMC_RET2(handle, SPCI_SUCCESS, ((uint32_t)service_handle) << 16);
-}
-
-/*******************************************************************************
- * This function closes a handle that a specific client uses to access a Secure
- * Service. It returns a SPCI_*** error code.
- ******************************************************************************/
-static uint64_t spci_service_handle_close(void *handle, u_register_t x1)
-{
- spci_handle_t *handle_info;
- uint16_t client_id = x1 & 0x0000FFFFU;
- uint16_t service_handle = (x1 >> 16) & 0x0000FFFFU;
-
- spin_lock(&spci_handles_lock);
-
- handle_info = spci_handle_info_get(service_handle, client_id);
-
- if (handle_info == NULL) {
- spin_unlock(&spci_handles_lock);
-
- WARN("SPCI: Tried to close invalid handle 0x%04x by client 0x%04x\n",
- service_handle, client_id);
-
- SMC_RET1(handle, SPCI_INVALID_PARAMETER);
- }
-
- if (handle_info->status != HANDLE_STATUS_OPEN) {
- spin_unlock(&spci_handles_lock);
-
- WARN("SPCI: Tried to close handle 0x%04x by client 0x%04x in status %d\n",
- service_handle, client_id, handle_info->status);
-
- SMC_RET1(handle, SPCI_INVALID_PARAMETER);
- }
-
- if (handle_info->num_active_requests != 0U) {
- spin_unlock(&spci_handles_lock);
-
- /* A handle can't be closed if there are requests left */
- WARN("SPCI: Tried to close handle 0x%04x by client 0x%04x with %d requests left\n",
- service_handle, client_id,
- handle_info->num_active_requests);
-
- SMC_RET1(handle, SPCI_BUSY);
- }
-
- memset(handle_info, 0, sizeof(spci_handle_t));
-
- handle_info->status = HANDLE_STATUS_CLOSED;
-
- spin_unlock(&spci_handles_lock);
-
- VERBOSE("SPCI: Closed handle 0x%04x by client 0x%04x.\n",
- service_handle, client_id);
-
- SMC_RET1(handle, SPCI_SUCCESS);
-}
-
-/*******************************************************************************
- * This function requests a Secure Service from a given handle and client ID.
- ******************************************************************************/
-static uint64_t spci_service_request_blocking(void *handle,
- uint32_t smc_fid, u_register_t x1, u_register_t x2,
- u_register_t x3, u_register_t x4, u_register_t x5,
- u_register_t x6, u_register_t x7)
-{
- spci_handle_t *handle_info;
- sp_context_t *sp_ctx;
- cpu_context_t *cpu_ctx;
- uint32_t rx0;
- u_register_t rx1, rx2, rx3;
- uint16_t request_handle, client_id;
-
- /* Get handle array lock */
- spin_lock(&spci_handles_lock);
-
- /* Get pointer to struct of this open handle and client ID. */
- request_handle = (x7 >> 16U) & 0x0000FFFFU;
- client_id = x7 & 0x0000FFFFU;
-
- handle_info = spci_handle_info_get(request_handle, client_id);
- if (handle_info == NULL) {
- spin_unlock(&spci_handles_lock);
-
- WARN("SPCI_SERVICE_TUN_REQUEST_BLOCKING: Not found.\n");
- WARN(" Handle 0x%04x. Client ID 0x%04x\n", request_handle,
- client_id);
-
- SMC_RET1(handle, SPCI_BUSY);
- }
-
- /* Get pointer to the Secure Partition that handles the service */
- sp_ctx = handle_info->sp_ctx;
- assert(sp_ctx != NULL);
- cpu_ctx = &(sp_ctx->cpu_ctx);
-
- /* Blocking requests are only allowed if the queue is empty */
- if (handle_info->num_active_requests > 0) {
- spin_unlock(&spci_handles_lock);
-
- SMC_RET1(handle, SPCI_BUSY);
- }
-
- if (spm_sp_request_increase_if_zero(sp_ctx) == -1) {
- spin_unlock(&spci_handles_lock);
-
- SMC_RET1(handle, SPCI_BUSY);
- }
-
- /* Prevent this handle from being closed */
- handle_info->num_active_requests += 1;
-
- /* Release handle lock */
- spin_unlock(&spci_handles_lock);
-
- /* Save the Normal world context */
- cm_el1_sysregs_context_save(NON_SECURE);
-
- /* Wait until the Secure Partition is idle and set it to busy. */
- sp_state_wait_switch(sp_ctx, SP_STATE_IDLE, SP_STATE_BUSY);
-
- /* Pass arguments to the Secure Partition */
- struct sprt_queue_entry_message message = {
- .type = SPRT_MSG_TYPE_SERVICE_TUN_REQUEST,
- .client_id = client_id,
- .service_handle = request_handle,
- .session_id = x6,
- .token = 0, /* No token needed for blocking requests */
- .args = {smc_fid, x1, x2, x3, x4, x5}
- };
-
- spin_lock(&(sp_ctx->spm_sp_buffer_lock));
- int rc = sprt_push_message((void *)sp_ctx->spm_sp_buffer_base, &message,
- SPRT_QUEUE_NUM_BLOCKING);
- spin_unlock(&(sp_ctx->spm_sp_buffer_lock));
- if (rc != 0) {
- /*
- * This shouldn't happen, blocking requests can only be made if
- * the request queue is empty.
- */
- assert(rc == -ENOMEM);
- ERROR("SPCI_SERVICE_TUN_REQUEST_BLOCKING: Queue is full.\n");
- panic();
- }
-
- /* Jump to the Secure Partition. */
- rx0 = spm_sp_synchronous_entry(sp_ctx, 0);
-
- /* Verify returned value */
- if (rx0 != SPRT_PUT_RESPONSE_AARCH64) {
- ERROR("SPM: %s: Unexpected x0 value 0x%x\n", __func__, rx0);
- panic();
- }
-
- rx1 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X3);
- rx2 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X4);
- rx3 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X5);
-
- /* Flag Secure Partition as idle. */
- assert(sp_ctx->state == SP_STATE_BUSY);
- sp_state_set(sp_ctx, SP_STATE_IDLE);
-
- /* Decrease count of requests. */
- spin_lock(&spci_handles_lock);
- handle_info->num_active_requests -= 1;
- spin_unlock(&spci_handles_lock);
- spm_sp_request_decrease(sp_ctx);
-
- /* Restore non-secure state */
- cm_el1_sysregs_context_restore(NON_SECURE);
- cm_set_next_eret_context(NON_SECURE);
-
- SMC_RET4(handle, SPCI_SUCCESS, rx1, rx2, rx3);
-}
-
-/*******************************************************************************
- * This function handles the returned values from the Secure Partition.
- ******************************************************************************/
-static void spci_handle_returned_values(const cpu_context_t *cpu_ctx,
- uint64_t ret)
-{
- if (ret == SPRT_PUT_RESPONSE_AARCH64) {
- uint32_t token;
- uint64_t x3, x4, x5, x6;
-
- token = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X1);
- x3 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X3);
- x4 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X4);
- x5 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X5);
- x6 = read_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X6);
-
- uint16_t client_id = x6 & 0xFFFFU;
- uint16_t service_handle = x6 >> 16;
-
- int rc = spm_response_add(client_id, service_handle, token,
- x3, x4, x5);
- if (rc != 0) {
- /*
- * This is error fatal because we can't return to the SP
- * from this SMC. The SP has crashed.
- */
- panic();
- }
- } else if ((ret != SPRT_YIELD_AARCH64) &&
- (ret != SPM_SECURE_PARTITION_PREEMPTED)) {
- ERROR("SPM: %s: Unexpected x0 value 0x%llx\n", __func__, ret);
- panic();
- }
-}
-
-/*******************************************************************************
- * This function requests a Secure Service from a given handle and client ID.
- ******************************************************************************/
-static uint64_t spci_service_request_start(void *handle,
- uint32_t smc_fid, u_register_t x1, u_register_t x2,
- u_register_t x3, u_register_t x4, u_register_t x5,
- u_register_t x6, u_register_t x7)
-{
- spci_handle_t *handle_info;
- sp_context_t *sp_ctx;
- cpu_context_t *cpu_ctx;
- uint16_t request_handle, client_id;
- uint32_t token;
-
- /* Get handle array lock */
- spin_lock(&spci_handles_lock);
-
- /* Get pointer to struct of this open handle and client ID. */
- request_handle = (x7 >> 16U) & 0x0000FFFFU;
- client_id = x7 & 0x0000FFFFU;
-
- handle_info = spci_handle_info_get(request_handle, client_id);
- if (handle_info == NULL) {
- spin_unlock(&spci_handles_lock);
-
- WARN("SPCI_SERVICE_TUN_REQUEST_START: Not found.\n"
- " Handle 0x%04x. Client ID 0x%04x\n", request_handle,
- client_id);
-
- SMC_RET1(handle, SPCI_INVALID_PARAMETER);
- }
-
- /* Get pointer to the Secure Partition that handles the service */
- sp_ctx = handle_info->sp_ctx;
- assert(sp_ctx != NULL);
- cpu_ctx = &(sp_ctx->cpu_ctx);
-
- /* Prevent this handle from being closed */
- handle_info->num_active_requests += 1;
-
- spm_sp_request_increase(sp_ctx);
-
- /* Create new token for this request */
- token = spci_create_token_value();
-
- /* Release handle lock */
- spin_unlock(&spci_handles_lock);
-
- /* Pass arguments to the Secure Partition */
- struct sprt_queue_entry_message message = {
- .type = SPRT_MSG_TYPE_SERVICE_TUN_REQUEST,
- .client_id = client_id,
- .service_handle = request_handle,
- .session_id = x6,
- .token = token,
- .args = {smc_fid, x1, x2, x3, x4, x5}
- };
-
- spin_lock(&(sp_ctx->spm_sp_buffer_lock));
- int rc = sprt_push_message((void *)sp_ctx->spm_sp_buffer_base, &message,
- SPRT_QUEUE_NUM_NON_BLOCKING);
- spin_unlock(&(sp_ctx->spm_sp_buffer_lock));
- if (rc != 0) {
- WARN("SPCI_SERVICE_TUN_REQUEST_START: SPRT queue full.\n"
- " Handle 0x%04x. Client ID 0x%04x\n", request_handle,
- client_id);
- SMC_RET1(handle, SPCI_NO_MEMORY);
- }
-
- /* Try to enter the partition. If it's not possible, simply return. */
- if (sp_state_try_switch(sp_ctx, SP_STATE_IDLE, SP_STATE_BUSY) != 0) {
- SMC_RET2(handle, SPCI_SUCCESS, token);
- }
-
- /* Save the Normal world context */
- cm_el1_sysregs_context_save(NON_SECURE);
-
- /*
- * This request is non-blocking and needs to be interruptible by
- * non-secure interrupts. Enable their routing to EL3 during the
- * processing of the Secure Partition's service on this core.
- */
-
- /* Jump to the Secure Partition. */
- uint64_t ret = spm_sp_synchronous_entry(sp_ctx, 1);
-
- /* Handle returned values */
- spci_handle_returned_values(cpu_ctx, ret);
-
- /* Flag Secure Partition as idle. */
- assert(sp_ctx->state == SP_STATE_BUSY);
- sp_state_set(sp_ctx, SP_STATE_IDLE);
-
- /* Restore non-secure state */
- cm_el1_sysregs_context_restore(NON_SECURE);
- cm_set_next_eret_context(NON_SECURE);
-
- SMC_RET2(handle, SPCI_SUCCESS, token);
-}
-
-/*******************************************************************************
- * This function returns the response of a Secure Service given a handle, a
- * client ID and a token. If not available, it will schedule a Secure Partition
- * and give it CPU time.
- ******************************************************************************/
-static uint64_t spci_service_request_resume(void *handle, u_register_t x1,
- u_register_t x7)
-{
- int rc;
- u_register_t rx1 = 0, rx2 = 0, rx3 = 0;
- spci_handle_t *handle_info;
- sp_context_t *sp_ctx;
- cpu_context_t *cpu_ctx;
- uint32_t token = (uint32_t) x1;
- uint16_t client_id = x7 & 0x0000FFFF;
- uint16_t service_handle = (x7 >> 16) & 0x0000FFFF;
-
- /* Get pointer to struct of this open handle and client ID. */
- spin_lock(&spci_handles_lock);
-
- handle_info = spci_handle_info_get(service_handle, client_id);
- if (handle_info == NULL) {
- spin_unlock(&spci_handles_lock);
- WARN("SPCI_SERVICE_REQUEST_RESUME: Not found.\n"
- "Handle 0x%04x. Client ID 0x%04x, Token 0x%08x.\n",
- client_id, service_handle, token);
-
- SMC_RET1(handle, SPCI_INVALID_PARAMETER);
- }
-
- /* Get pointer to the Secure Partition that handles the service */
- sp_ctx = handle_info->sp_ctx;
- assert(sp_ctx != NULL);
- cpu_ctx = &(sp_ctx->cpu_ctx);
-
- spin_unlock(&spci_handles_lock);
-
- /* Look for a valid response in the global queue */
- rc = spm_response_get(client_id, service_handle, token,
- &rx1, &rx2, &rx3);
- if (rc == 0) {
- /* Decrease request count */
- spin_lock(&spci_handles_lock);
- handle_info->num_active_requests -= 1;
- spin_unlock(&spci_handles_lock);
- spm_sp_request_decrease(sp_ctx);
-
- SMC_RET4(handle, SPCI_SUCCESS, rx1, rx2, rx3);
- }
-
- /* Try to enter the partition. If it's not possible, simply return. */
- if (sp_state_try_switch(sp_ctx, SP_STATE_IDLE, SP_STATE_BUSY) != 0) {
- SMC_RET1(handle, SPCI_QUEUED);
- }
-
- /* Save the Normal world context */
- cm_el1_sysregs_context_save(NON_SECURE);
-
- /*
- * This request is non-blocking and needs to be interruptible by
- * non-secure interrupts. Enable their routing to EL3 during the
- * processing of the Secure Partition's service on this core.
- */
-
- /* Jump to the Secure Partition. */
- uint64_t ret = spm_sp_synchronous_entry(sp_ctx, 1);
-
- /* Handle returned values */
- spci_handle_returned_values(cpu_ctx, ret);
-
- /* Flag Secure Partition as idle. */
- assert(sp_ctx->state == SP_STATE_BUSY);
- sp_state_set(sp_ctx, SP_STATE_IDLE);
-
- /* Restore non-secure state */
- cm_el1_sysregs_context_restore(NON_SECURE);
- cm_set_next_eret_context(NON_SECURE);
-
- /* Look for a valid response in the global queue */
- rc = spm_response_get(client_id, service_handle, token,
- &rx1, &rx2, &rx3);
- if (rc != 0) {
- SMC_RET1(handle, SPCI_QUEUED);
- }
-
- /* Decrease request count */
- spin_lock(&spci_handles_lock);
- handle_info->num_active_requests -= 1;
- spin_unlock(&spci_handles_lock);
- spm_sp_request_decrease(sp_ctx);
-
- /* Return response */
- SMC_RET4(handle, SPCI_SUCCESS, rx1, rx2, rx3);
-}
-
-/*******************************************************************************
- * This function returns the response of a Secure Service given a handle, a
- * client ID and a token.
- ******************************************************************************/
-static uint64_t spci_service_get_response(void *handle, u_register_t x1,
- u_register_t x7)
-
-{
- int rc;
- u_register_t rx1 = 0, rx2 = 0, rx3 = 0;
- spci_handle_t *handle_info;
- uint32_t token = (uint32_t) x1;
- uint16_t client_id = x7 & 0x0000FFFF;
- uint16_t service_handle = (x7 >> 16) & 0x0000FFFF;
-
- /* Get pointer to struct of this open handle and client ID. */
-
- spin_lock(&spci_handles_lock);
-
- handle_info = spci_handle_info_get(service_handle, client_id);
- if (handle_info == NULL) {
- spin_unlock(&spci_handles_lock);
- WARN("SPCI_SERVICE_GET_RESPONSE: Not found.\n"
- "Handle 0x%04x. Client ID 0x%04x, Token 0x%08x.\n",
- client_id, service_handle, token);
-
- SMC_RET1(handle, SPCI_INVALID_PARAMETER);
- }
-
- spin_unlock(&spci_handles_lock);
-
- /* Look for a valid response in the global queue */
- rc = spm_response_get(client_id, service_handle, token,
- &rx1, &rx2, &rx3);
-
- if (rc != 0) {
- SMC_RET1(handle, SPCI_QUEUED);
- }
-
- /* Decrease request count */
- spin_lock(&spci_handles_lock);
- handle_info->num_active_requests -= 1;
- sp_context_t *sp_ctx;
- sp_ctx = handle_info->sp_ctx;
- spin_unlock(&spci_handles_lock);
- spm_sp_request_decrease(sp_ctx);
-
- /* Return response */
- SMC_RET4(handle, SPCI_SUCCESS, rx1, rx2, rx3);
-}
-
-/*******************************************************************************
- * This function handles all SMCs in the range reserved for SPCI.
- ******************************************************************************/
-static uintptr_t spci_smc_handler(uint32_t smc_fid, u_register_t x1,
- u_register_t x2, u_register_t x3,
- u_register_t x4, void *cookie, void *handle,
- u_register_t flags)
-{
- uint32_t spci_fid;
-
- /* SPCI only supported from the Non-secure world for now */
- if (is_caller_non_secure(flags) == SMC_FROM_SECURE) {
- SMC_RET1(handle, SMC_UNK);
- }
-
- if ((smc_fid & SPCI_FID_TUN_FLAG) == 0) {
-
- /* Miscellaneous calls */
-
- spci_fid = (smc_fid >> SPCI_FID_MISC_SHIFT) & SPCI_FID_MISC_MASK;
-
- switch (spci_fid) {
-
- case SPCI_FID_VERSION:
- SMC_RET1(handle, SPCI_VERSION_COMPILED);
-
- case SPCI_FID_SERVICE_HANDLE_OPEN:
- {
- if ((smc_fid & SPCI_SERVICE_HANDLE_OPEN_NOTIFY_BIT) != 0) {
- /* Not supported for now */
- WARN("SPCI_SERVICE_HANDLE_OPEN_NOTIFY not supported.\n");
- SMC_RET1(handle, SPCI_INVALID_PARAMETER);
- }
-
- uint64_t x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
- uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- uint64_t x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
-
- return spci_service_handle_open_poll(handle, x1, x2, x3,
- x4, x5, x6, x7);
- }
- case SPCI_FID_SERVICE_HANDLE_CLOSE:
- return spci_service_handle_close(handle, x1);
-
- case SPCI_FID_SERVICE_REQUEST_BLOCKING:
- {
- uint64_t x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
- uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- uint64_t x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
-
- return spci_service_request_blocking(handle,
- smc_fid, x1, x2, x3, x4, x5, x6, x7);
- }
-
- case SPCI_FID_SERVICE_REQUEST_START:
- {
- uint64_t x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
- uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- uint64_t x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
-
- return spci_service_request_start(handle,
- smc_fid, x1, x2, x3, x4, x5, x6, x7);
- }
-
- case SPCI_FID_SERVICE_GET_RESPONSE:
- {
- uint64_t x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
-
- return spci_service_get_response(handle, x1, x7);
- }
-
- default:
- break;
- }
-
- } else {
-
- /* Tunneled calls */
-
- spci_fid = (smc_fid >> SPCI_FID_TUN_SHIFT) & SPCI_FID_TUN_MASK;
-
- switch (spci_fid) {
-
- case SPCI_FID_SERVICE_REQUEST_RESUME:
- {
- uint64_t x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
-
- return spci_service_request_resume(handle, x1, x7);
- }
-
- default:
- break;
- }
- }
-
- WARN("SPCI: Unsupported call 0x%08x\n", smc_fid);
- SMC_RET1(handle, SPCI_NOT_SUPPORTED);
-}
-
-DECLARE_RT_SVC(
- spci_handler,
- OEN_SPCI_START,
- OEN_SPCI_END,
- SMC_TYPE_FAST,
- NULL,
- spci_smc_handler
-);
diff --git a/services/std_svc/spm/spm.mk b/services/std_svc/spm/spm.mk
deleted file mode 100644
index 448aba4..0000000
--- a/services/std_svc/spm/spm.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-#
-# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifneq (${SPD},none)
- $(error "Error: SPD and SPM are incompatible build options.")
-endif
-ifneq (${ARCH},aarch64)
- $(error "Error: SPM is only supported on aarch64.")
-endif
-
-include lib/sprt/sprt_host.mk
-
-SPM_SOURCES := $(addprefix services/std_svc/spm/, \
- ${ARCH}/spm_helpers.S \
- ${ARCH}/spm_shim_exceptions.S \
- spci.c \
- spm_buffers.c \
- spm_main.c \
- spm_setup.c \
- spm_xlat.c \
- sprt.c) \
- ${SPRT_LIB_SOURCES}
-
-INCLUDES += ${SPRT_LIB_INCLUDES}
-
-# Let the top-level Makefile know that we intend to include a BL32 image
-NEED_BL32 := yes
diff --git a/services/std_svc/spm/spm_buffers.c b/services/std_svc/spm/spm_buffers.c
deleted file mode 100644
index 79398ba..0000000
--- a/services/std_svc/spm/spm_buffers.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <lib/spinlock.h>
-#include <lib/utils_def.h>
-#include <platform_def.h>
-
-#include "./spm_private.h"
-
-/*******************************************************************************
- * Secure Service response global array. All the responses to the requests done
- * to the Secure Partition are stored here. They are removed from the array as
- * soon as their value is read.
- ******************************************************************************/
-struct sprt_response {
- int is_valid;
- uint32_t token;
- uint16_t client_id, handle;
- u_register_t x1, x2, x3;
-};
-
-static struct sprt_response responses[PLAT_SPM_RESPONSES_MAX];
-
-static spinlock_t responses_lock;
-
-/* Add response to the global response buffer. Returns 0 on success else -1. */
-int spm_response_add(uint16_t client_id, uint16_t handle, uint32_t token,
- u_register_t x1, u_register_t x2, u_register_t x3)
-{
- spin_lock(&responses_lock);
-
- /* Make sure that there isn't any other response with the same token. */
- for (unsigned int i = 0U; i < ARRAY_SIZE(responses); i++) {
- struct sprt_response *resp = &(responses[i]);
-
- if ((resp->is_valid == 1) && (resp->token == token)) {
- spin_unlock(&responses_lock);
-
- return -1;
- }
- }
-
- for (unsigned int i = 0U; i < ARRAY_SIZE(responses); i++) {
- struct sprt_response *resp = &(responses[i]);
-
- if (resp->is_valid == 0) {
- resp->token = token;
- resp->client_id = client_id;
- resp->handle = handle;
- resp->x1 = x1;
- resp->x2 = x2;
- resp->x3 = x3;
-
- dmbish();
-
- resp->is_valid = 1;
-
- spin_unlock(&responses_lock);
-
- return 0;
- }
- }
-
- spin_unlock(&responses_lock);
-
- return -1;
-}
-
-/*
- * Returns a response from the requests array and removes it from it. Returns 0
- * on success, -1 if it wasn't found.
- */
-int spm_response_get(uint16_t client_id, uint16_t handle, uint32_t token,
- u_register_t *x1, u_register_t *x2, u_register_t *x3)
-{
- spin_lock(&responses_lock);
-
- for (unsigned int i = 0U; i < ARRAY_SIZE(responses); i++) {
- struct sprt_response *resp = &(responses[i]);
-
- /* Ignore invalid entries */
- if (resp->is_valid == 0) {
- continue;
- }
-
- /* Make sure that all the information matches the stored one */
- if ((resp->token != token) || (resp->client_id != client_id) ||
- (resp->handle != handle)) {
- continue;
- }
-
- *x1 = resp->x1;
- *x2 = resp->x2;
- *x3 = resp->x3;
-
- dmbish();
-
- resp->is_valid = 0;
-
- spin_unlock(&responses_lock);
-
- return 0;
- }
-
- spin_unlock(&responses_lock);
-
- return -1;
-}
diff --git a/services/std_svc/spm/spm_main.c b/services/std_svc/spm/spm_main.c
deleted file mode 100644
index 3a63f1c..0000000
--- a/services/std_svc/spm/spm_main.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <string.h>
-
-#include <arch_helpers.h>
-#include <bl31/bl31.h>
-#include <bl31/ehf.h>
-#include <bl31/interrupt_mgmt.h>
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <lib/el3_runtime/context_mgmt.h>
-#include <lib/smccc.h>
-#include <lib/spinlock.h>
-#include <lib/utils.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include <plat/common/platform.h>
-#include <services/spm_svc.h>
-#include <services/sprt_svc.h>
-#include <smccc_helpers.h>
-
-#include "spm_private.h"
-
-/*******************************************************************************
- * Secure Partition context information.
- ******************************************************************************/
-sp_context_t sp_ctx_array[PLAT_SPM_MAX_PARTITIONS];
-
-/* Last Secure Partition last used by the CPU */
-sp_context_t *cpu_sp_ctx[PLATFORM_CORE_COUNT];
-
-void spm_cpu_set_sp_ctx(unsigned int linear_id, sp_context_t *sp_ctx)
-{
- assert(linear_id < PLATFORM_CORE_COUNT);
-
- cpu_sp_ctx[linear_id] = sp_ctx;
-}
-
-sp_context_t *spm_cpu_get_sp_ctx(unsigned int linear_id)
-{
- assert(linear_id < PLATFORM_CORE_COUNT);
-
- return cpu_sp_ctx[linear_id];
-}
-
-/*******************************************************************************
- * Functions to keep track of how many requests a Secure Partition has received
- * and hasn't finished.
- ******************************************************************************/
-void spm_sp_request_increase(sp_context_t *sp_ctx)
-{
- spin_lock(&(sp_ctx->request_count_lock));
- sp_ctx->request_count++;
- spin_unlock(&(sp_ctx->request_count_lock));
-}
-
-void spm_sp_request_decrease(sp_context_t *sp_ctx)
-{
- spin_lock(&(sp_ctx->request_count_lock));
- sp_ctx->request_count--;
- spin_unlock(&(sp_ctx->request_count_lock));
-}
-
-/* Returns 0 if it was originally 0, -1 otherwise. */
-int spm_sp_request_increase_if_zero(sp_context_t *sp_ctx)
-{
- int ret = -1;
-
- spin_lock(&(sp_ctx->request_count_lock));
- if (sp_ctx->request_count == 0U) {
- sp_ctx->request_count++;
- ret = 0U;
- }
- spin_unlock(&(sp_ctx->request_count_lock));
-
- return ret;
-}
-
-/*******************************************************************************
- * This function returns a pointer to the context of the Secure Partition that
- * handles the service specified by an UUID. It returns NULL if the UUID wasn't
- * found.
- ******************************************************************************/
-sp_context_t *spm_sp_get_by_uuid(const uint32_t (*svc_uuid)[4])
-{
- unsigned int i;
-
- for (i = 0U; i < PLAT_SPM_MAX_PARTITIONS; i++) {
-
- sp_context_t *sp_ctx = &sp_ctx_array[i];
-
- if (sp_ctx->is_present == 0) {
- continue;
- }
-
- struct sp_rd_sect_service *rdsvc;
-
- for (rdsvc = sp_ctx->rd.service; rdsvc != NULL;
- rdsvc = rdsvc->next) {
- uint32_t *rd_uuid = (uint32_t *)(rdsvc->uuid);
-
- if (memcmp(rd_uuid, svc_uuid, sizeof(*svc_uuid)) == 0) {
- return sp_ctx;
- }
- }
- }
-
- return NULL;
-}
-
-/*******************************************************************************
- * Set state of a Secure Partition context.
- ******************************************************************************/
-void sp_state_set(sp_context_t *sp_ptr, sp_state_t state)
-{
- spin_lock(&(sp_ptr->state_lock));
- sp_ptr->state = state;
- spin_unlock(&(sp_ptr->state_lock));
-}
-
-/*******************************************************************************
- * Wait until the state of a Secure Partition is the specified one and change it
- * to the desired state.
- ******************************************************************************/
-void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to)
-{
- int success = 0;
-
- while (success == 0) {
- spin_lock(&(sp_ptr->state_lock));
-
- if (sp_ptr->state == from) {
- sp_ptr->state = to;
-
- success = 1;
- }
-
- spin_unlock(&(sp_ptr->state_lock));
- }
-}
-
-/*******************************************************************************
- * Check if the state of a Secure Partition is the specified one and, if so,
- * change it to the desired state. Returns 0 on success, -1 on error.
- ******************************************************************************/
-int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to)
-{
- int ret = -1;
-
- spin_lock(&(sp_ptr->state_lock));
-
- if (sp_ptr->state == from) {
- sp_ptr->state = to;
-
- ret = 0;
- }
-
- spin_unlock(&(sp_ptr->state_lock));
-
- return ret;
-}
-
-/*******************************************************************************
- * This function takes an SP context pointer and performs a synchronous entry
- * into it.
- ******************************************************************************/
-uint64_t spm_sp_synchronous_entry(sp_context_t *sp_ctx, int can_preempt)
-{
- uint64_t rc;
- unsigned int linear_id = plat_my_core_pos();
-
- assert(sp_ctx != NULL);
-
- /* Assign the context of the SP to this CPU */
- spm_cpu_set_sp_ctx(linear_id, sp_ctx);
- cm_set_context(&(sp_ctx->cpu_ctx), SECURE);
-
- /* Restore the context assigned above */
- cm_el1_sysregs_context_restore(SECURE);
- cm_set_next_eret_context(SECURE);
-
- /* Invalidate TLBs at EL1. */
- tlbivmalle1();
- dsbish();
-
- if (can_preempt == 1) {
- enable_intr_rm_local(INTR_TYPE_NS, SECURE);
- } else {
- disable_intr_rm_local(INTR_TYPE_NS, SECURE);
- }
-
- /* Enter Secure Partition */
- rc = spm_secure_partition_enter(&sp_ctx->c_rt_ctx);
-
- /* Save secure state */
- cm_el1_sysregs_context_save(SECURE);
-
- return rc;
-}
-
-/*******************************************************************************
- * This function returns to the place where spm_sp_synchronous_entry() was
- * called originally.
- ******************************************************************************/
-__dead2 void spm_sp_synchronous_exit(uint64_t rc)
-{
- /* Get context of the SP in use by this CPU. */
- unsigned int linear_id = plat_my_core_pos();
- sp_context_t *ctx = spm_cpu_get_sp_ctx(linear_id);
-
- /*
- * The SPM must have initiated the original request through a
- * synchronous entry into the secure partition. Jump back to the
- * original C runtime context with the value of rc in x0;
- */
- spm_secure_partition_exit(ctx->c_rt_ctx, rc);
-
- panic();
-}
-
-/*******************************************************************************
- * This function is the handler registered for Non secure interrupts by the SPM.
- * It validates the interrupt and upon success arranges entry into the normal
- * world for handling the interrupt.
- ******************************************************************************/
-static uint64_t spm_ns_interrupt_handler(uint32_t id, uint32_t flags,
- void *handle, void *cookie)
-{
- /* Check the security state when the exception was generated */
- assert(get_interrupt_src_ss(flags) == SECURE);
-
- spm_sp_synchronous_exit(SPM_SECURE_PARTITION_PREEMPTED);
-}
-
-/*******************************************************************************
- * Jump to each Secure Partition for the first time.
- ******************************************************************************/
-static int32_t spm_init(void)
-{
- uint64_t rc = 0;
- sp_context_t *ctx;
-
- for (unsigned int i = 0U; i < PLAT_SPM_MAX_PARTITIONS; i++) {
-
- ctx = &sp_ctx_array[i];
-
- if (ctx->is_present == 0) {
- continue;
- }
-
- INFO("Secure Partition %u init...\n", i);
-
- ctx->state = SP_STATE_RESET;
-
- rc = spm_sp_synchronous_entry(ctx, 0);
- if (rc != SPRT_YIELD_AARCH64) {
- ERROR("Unexpected return value 0x%llx\n", rc);
- panic();
- }
-
- ctx->state = SP_STATE_IDLE;
-
- INFO("Secure Partition %u initialized.\n", i);
- }
-
- return rc;
-}
-
-/*******************************************************************************
- * Initialize contexts of all Secure Partitions.
- ******************************************************************************/
-int32_t spm_setup(void)
-{
- int rc;
- sp_context_t *ctx;
- void *sp_base, *rd_base;
- size_t sp_size, rd_size;
- uint64_t flags = 0U;
-
- /* Disable MMU at EL1 (initialized by BL2) */
- disable_mmu_icache_el1();
-
- /*
- * Non-blocking services can be interrupted by Non-secure interrupts.
- * Register an interrupt handler for NS interrupts when generated while
- * the CPU is in secure state. They are routed to EL3.
- */
- set_interrupt_rm_flag(flags, SECURE);
-
- uint64_t rc_int = register_interrupt_type_handler(INTR_TYPE_NS,
- spm_ns_interrupt_handler, flags);
- if (rc_int) {
- ERROR("SPM: Failed to register NS interrupt handler with rc = %llx\n",
- rc_int);
- panic();
- }
-
- /* Setup shim layer */
- spm_exceptions_xlat_init_context();
-
- /*
- * Setup all Secure Partitions.
- */
- unsigned int i = 0U;
-
- while (1) {
- rc = plat_spm_sp_get_next_address(&sp_base, &sp_size,
- &rd_base, &rd_size);
- if (rc < 0) {
- /* Reached the end of the package. */
- break;
- }
-
- if (i >= PLAT_SPM_MAX_PARTITIONS) {
- ERROR("Too many partitions in the package.\n");
- panic();
- }
-
- ctx = &sp_ctx_array[i];
-
- assert(ctx->is_present == 0);
-
- /* Initialize context of the SP */
- INFO("Secure Partition %u context setup start...\n", i);
-
- /* Save location of the image in physical memory */
- ctx->image_base = (uintptr_t)sp_base;
- ctx->image_size = sp_size;
-
- rc = plat_spm_sp_rd_load(&ctx->rd, rd_base, rd_size);
- if (rc < 0) {
- ERROR("Error while loading RD blob.\n");
- panic();
- }
-
- spm_sp_setup(ctx);
-
- ctx->is_present = 1;
-
- INFO("Secure Partition %u setup done.\n", i);
-
- i++;
- }
-
- if (i == 0U) {
- ERROR("No present partitions in the package.\n");
- panic();
- }
-
- /* Register init function for deferred init. */
- bl31_register_bl32_init(&spm_init);
-
- return 0;
-}
diff --git a/services/std_svc/spm/spm_private.h b/services/std_svc/spm/spm_private.h
deleted file mode 100644
index efc91cb..0000000
--- a/services/std_svc/spm/spm_private.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SPM_PRIVATE_H
-#define SPM_PRIVATE_H
-
-#include <context.h>
-
-/*******************************************************************************
- * Constants that allow assembler code to preserve callee-saved registers of the
- * C runtime context while performing a security state switch.
- ******************************************************************************/
-#define SP_C_RT_CTX_X19 0x0
-#define SP_C_RT_CTX_X20 0x8
-#define SP_C_RT_CTX_X21 0x10
-#define SP_C_RT_CTX_X22 0x18
-#define SP_C_RT_CTX_X23 0x20
-#define SP_C_RT_CTX_X24 0x28
-#define SP_C_RT_CTX_X25 0x30
-#define SP_C_RT_CTX_X26 0x38
-#define SP_C_RT_CTX_X27 0x40
-#define SP_C_RT_CTX_X28 0x48
-#define SP_C_RT_CTX_X29 0x50
-#define SP_C_RT_CTX_X30 0x58
-
-#define SP_C_RT_CTX_SIZE 0x60
-#define SP_C_RT_CTX_ENTRIES (SP_C_RT_CTX_SIZE >> DWORD_SHIFT)
-
-/* Value returned by spm_sp_synchronous_entry() when a partition is preempted */
-#define SPM_SECURE_PARTITION_PREEMPTED U(0x1234)
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include <lib/spinlock.h>
-#include <services/sp_res_desc.h>
-
-typedef enum sp_state {
- SP_STATE_RESET = 0,
- SP_STATE_IDLE,
- SP_STATE_BUSY
-} sp_state_t;
-
-typedef struct sp_context {
- /* 1 if the partition is present, 0 otherwise */
- int is_present;
-
- /* Location of the image in physical memory */
- unsigned long long image_base;
- size_t image_size;
-
- uint64_t c_rt_ctx;
- cpu_context_t cpu_ctx;
- struct sp_res_desc rd;
-
- /* Translation tables context */
- xlat_ctx_t *xlat_ctx_handle;
- spinlock_t xlat_ctx_lock;
-
- sp_state_t state;
- spinlock_t state_lock;
-
- unsigned int request_count;
- spinlock_t request_count_lock;
-
- /* Base and size of the shared SPM<->SP buffer */
- uintptr_t spm_sp_buffer_base;
- size_t spm_sp_buffer_size;
- spinlock_t spm_sp_buffer_lock;
-} sp_context_t;
-
-/* Functions used to enter/exit a Secure Partition synchronously */
-uint64_t spm_sp_synchronous_entry(sp_context_t *sp_ctx, int can_preempt);
-__dead2 void spm_sp_synchronous_exit(uint64_t rc);
-
-/* Assembly helpers */
-uint64_t spm_secure_partition_enter(uint64_t *c_rt_ctx);
-void __dead2 spm_secure_partition_exit(uint64_t c_rt_ctx, uint64_t ret);
-
-/* Secure Partition setup */
-void spm_sp_setup(sp_context_t *sp_ctx);
-
-/* Secure Partition state management helpers */
-void sp_state_set(sp_context_t *sp_ptr, sp_state_t state);
-void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to);
-int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to);
-
-/* Functions to keep track of the number of active requests per SP */
-void spm_sp_request_increase(sp_context_t *sp_ctx);
-void spm_sp_request_decrease(sp_context_t *sp_ctx);
-int spm_sp_request_increase_if_zero(sp_context_t *sp_ctx);
-
-/* Functions related to the shim layer translation tables */
-void spm_exceptions_xlat_init_context(void);
-uint64_t *spm_exceptions_xlat_get_base_table(void);
-
-/* Functions related to the translation tables management */
-void spm_sp_xlat_context_alloc(sp_context_t *sp_ctx);
-void sp_map_memory_regions(sp_context_t *sp_ctx);
-
-/* Functions to handle Secure Partition contexts */
-void spm_cpu_set_sp_ctx(unsigned int linear_id, sp_context_t *sp_ctx);
-sp_context_t *spm_cpu_get_sp_ctx(unsigned int linear_id);
-sp_context_t *spm_sp_get_by_uuid(const uint32_t (*svc_uuid)[4]);
-
-/* Functions to manipulate response and requests buffers */
-int spm_response_add(uint16_t client_id, uint16_t handle, uint32_t token,
- u_register_t x1, u_register_t x2, u_register_t x3);
-int spm_response_get(uint16_t client_id, uint16_t handle, uint32_t token,
- u_register_t *x1, u_register_t *x2, u_register_t *x3);
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* SPM_PRIVATE_H */
diff --git a/services/std_svc/spm/spm_setup.c b/services/std_svc/spm/spm_setup.c
deleted file mode 100644
index 2ed44d1..0000000
--- a/services/std_svc/spm/spm_setup.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <string.h>
-
-#include <platform_def.h>
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <context.h>
-#include <common/debug.h>
-#include <lib/el3_runtime/context_mgmt.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include <plat/common/common_def.h>
-#include <plat/common/platform.h>
-#include <services/sp_res_desc.h>
-#include <sprt_host.h>
-
-#include "spm_private.h"
-#include "spm_shim_private.h"
-
-/* Setup context of the Secure Partition */
-void spm_sp_setup(sp_context_t *sp_ctx)
-{
- cpu_context_t *ctx = &(sp_ctx->cpu_ctx);
-
- /*
- * Initialize CPU context
- * ----------------------
- */
-
- entry_point_info_t ep_info = {0};
-
- SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
-
- /* Setup entrypoint and SPSR */
- ep_info.pc = sp_ctx->rd.attribute.entrypoint;
- ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS);
-
- /*
- * X0: Unused (MBZ).
- * X1: Unused (MBZ).
- * X2: cookie value (Implementation Defined)
- * X3: cookie value (Implementation Defined)
- * X4 to X7 = 0
- */
- ep_info.args.arg0 = 0;
- ep_info.args.arg1 = 0;
- ep_info.args.arg2 = PLAT_SPM_COOKIE_0;
- ep_info.args.arg3 = PLAT_SPM_COOKIE_1;
-
- cm_setup_context(ctx, &ep_info);
-
- /*
- * Setup translation tables
- * ------------------------
- */
-
- /* Assign translation tables context. */
- spm_sp_xlat_context_alloc(sp_ctx);
-
- sp_map_memory_regions(sp_ctx);
-
- /*
- * MMU-related registers
- * ---------------------
- */
- xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle;
-
- uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
-
- setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table,
- xlat_ctx->pa_max_address, xlat_ctx->va_max_address,
- EL1_EL0_REGIME);
-
- write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1,
- mmu_cfg_params[MMU_CFG_MAIR]);
-
- /* Enable translations using TTBR1_EL1 */
- int t1sz = 64 - __builtin_ctzll(SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE);
- mmu_cfg_params[MMU_CFG_TCR] &= ~TCR_EPD1_BIT;
- mmu_cfg_params[MMU_CFG_TCR] |=
- ((uint64_t)t1sz << TCR_T1SZ_SHIFT) |
- TCR_SH1_INNER_SHAREABLE |
- TCR_RGN1_OUTER_WBA | TCR_RGN1_INNER_WBA |
- TCR_TG1_4K;
-
- write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1,
- mmu_cfg_params[MMU_CFG_TCR]);
-
- write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1,
- mmu_cfg_params[MMU_CFG_TTBR0]);
-
- write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR1_EL1,
- (uint64_t)spm_exceptions_xlat_get_base_table());
-
- /* Setup SCTLR_EL1 */
- u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1);
-
- sctlr_el1 |=
- /*SCTLR_EL1_RES1 |*/
- /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */
- SCTLR_UCI_BIT |
- /* RW regions at xlat regime EL1&0 are forced to be XN. */
- SCTLR_WXN_BIT |
- /* Don't trap to EL1 execution of WFI or WFE at EL0. */
- SCTLR_NTWI_BIT | SCTLR_NTWE_BIT |
- /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */
- SCTLR_UCT_BIT |
- /* Don't trap to EL1 execution of DZ ZVA at EL0. */
- SCTLR_DZE_BIT |
- /* Enable SP Alignment check for EL0 */
- SCTLR_SA0_BIT |
- /* Allow cacheable data and instr. accesses to normal memory. */
- SCTLR_C_BIT | SCTLR_I_BIT |
- /* Alignment fault checking enabled when at EL1 and EL0. */
- SCTLR_A_BIT |
- /* Enable MMU. */
- SCTLR_M_BIT
- ;
-
- sctlr_el1 &= ~(
- /* Explicit data accesses at EL0 are little-endian. */
- SCTLR_E0E_BIT |
- /* Accesses to DAIF from EL0 are trapped to EL1. */
- SCTLR_UMA_BIT
- );
-
- write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
-
- /*
- * Setup other system registers
- * ----------------------------
- */
-
- /*
- * Shim exception vector base address. It is mapped at the start of the
- * address space accessed by TTBR1_EL1, which means that the base
- * address of the exception vectors depends on the size of the address
- * space specified in TCR_EL1.T1SZ.
- */
- write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1,
- UINT64_MAX - (SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE - 1ULL));
-
- /*
- * FPEN: Allow the Secure Partition to access FP/SIMD registers.
- * Note that SPM will not do any saving/restoring of these registers on
- * behalf of the SP. This falls under the SP's responsibility.
- * TTA: Enable access to trace registers.
- * ZEN (v8.2): Trap SVE instructions and access to SVE registers.
- */
- write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1,
- CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE));
-
- /*
- * Prepare shared buffers
- * ----------------------
- */
-
- /* Initialize SPRT queues */
- sprt_initialize_queues((void *)sp_ctx->spm_sp_buffer_base,
- sp_ctx->spm_sp_buffer_size);
-}
diff --git a/services/std_svc/spm/spm_shim_private.h b/services/std_svc/spm/spm_shim_private.h
deleted file mode 100644
index fc510b1..0000000
--- a/services/std_svc/spm/spm_shim_private.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SPM_SHIM_PRIVATE_H
-#define SPM_SHIM_PRIVATE_H
-
-#include <stdint.h>
-
-#include <lib/utils_def.h>
-
-/* Assembly source */
-IMPORT_SYM(uintptr_t, spm_shim_exceptions_ptr, SPM_SHIM_EXCEPTIONS_PTR);
-
-/* Linker symbols */
-IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START);
-IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END);
-
-/* Definitions */
-
-#define SPM_SHIM_EXCEPTIONS_SIZE \
- (SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START)
-
-/*
- * Use the smallest virtual address space size allowed in ARMv8.0 for
- * compatibility.
- */
-#define SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 25)
-#define SPM_SHIM_MMAP_REGIONS 1
-#define SPM_SHIM_XLAT_TABLES 1
-
-#endif /* SPM_SHIM_PRIVATE_H */
diff --git a/services/std_svc/spm/spm_xlat.c b/services/std_svc/spm/spm_xlat.c
deleted file mode 100644
index 5d5bc51..0000000
--- a/services/std_svc/spm/spm_xlat.c
+++ /dev/null
@@ -1,381 +0,0 @@
-/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <arch_features.h>
-#include <arch_helpers.h>
-#include <assert.h>
-#include <errno.h>
-#include <string.h>
-
-#include <platform_def.h>
-
-#include <lib/object_pool.h>
-#include <lib/utils.h>
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include <plat/common/platform.h>
-#include <services/sp_res_desc.h>
-
-#include "spm_private.h"
-#include "spm_shim_private.h"
-
-/*******************************************************************************
- * Instantiation of translation table context
- ******************************************************************************/
-
-/* Place translation tables by default along with the ones used by BL31. */
-#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME
-#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table"
-#endif
-
-/*
- * Allocate elements of the translation contexts for the Secure Partitions.
- */
-
-/* Allocate an array of mmap_region per partition. */
-static struct mmap_region sp_mmap_regions[PLAT_SP_IMAGE_MMAP_REGIONS + 1]
- [PLAT_SPM_MAX_PARTITIONS];
-static OBJECT_POOL(sp_mmap_regions_pool, sp_mmap_regions,
- sizeof(mmap_region_t) * (PLAT_SP_IMAGE_MMAP_REGIONS + 1),
- PLAT_SPM_MAX_PARTITIONS);
-
-/* Allocate individual translation tables. */
-static uint64_t sp_xlat_tables[XLAT_TABLE_ENTRIES]
- [(PLAT_SP_IMAGE_MAX_XLAT_TABLES + 1) * PLAT_SPM_MAX_PARTITIONS]
- __aligned(XLAT_TABLE_SIZE) __section(PLAT_SP_IMAGE_XLAT_SECTION_NAME);
-static OBJECT_POOL(sp_xlat_tables_pool, sp_xlat_tables,
- XLAT_TABLE_ENTRIES * sizeof(uint64_t),
- (PLAT_SP_IMAGE_MAX_XLAT_TABLES + 1) * PLAT_SPM_MAX_PARTITIONS);
-
-/* Allocate arrays. */
-static int sp_xlat_mapped_regions[PLAT_SP_IMAGE_MAX_XLAT_TABLES]
- [PLAT_SPM_MAX_PARTITIONS];
-static OBJECT_POOL(sp_xlat_mapped_regions_pool, sp_xlat_mapped_regions,
- sizeof(int) * PLAT_SP_IMAGE_MAX_XLAT_TABLES, PLAT_SPM_MAX_PARTITIONS);
-
-/* Allocate individual contexts. */
-static xlat_ctx_t sp_xlat_ctx[PLAT_SPM_MAX_PARTITIONS];
-static OBJECT_POOL(sp_xlat_ctx_pool, sp_xlat_ctx, sizeof(xlat_ctx_t),
- PLAT_SPM_MAX_PARTITIONS);
-
-/* Get handle of Secure Partition translation context */
-void spm_sp_xlat_context_alloc(sp_context_t *sp_ctx)
-{
- /* Allocate xlat context elements */
-
- xlat_ctx_t *ctx = pool_alloc(&sp_xlat_ctx_pool);
-
- struct mmap_region *mmap = pool_alloc(&sp_mmap_regions_pool);
-
- uint64_t *base_table = pool_alloc(&sp_xlat_tables_pool);
- uint64_t **tables = pool_alloc_n(&sp_xlat_tables_pool,
- PLAT_SP_IMAGE_MAX_XLAT_TABLES);
-
- int *mapped_regions = pool_alloc(&sp_xlat_mapped_regions_pool);
-
- /* Calculate the size of the virtual address space needed */
-
- uintptr_t va_size = 0U;
- struct sp_rd_sect_mem_region *rdmem;
-
- for (rdmem = sp_ctx->rd.mem_region; rdmem != NULL; rdmem = rdmem->next) {
- uintptr_t end_va = (uintptr_t)rdmem->base +
- (uintptr_t)rdmem->size;
-
- if (end_va > va_size)
- va_size = end_va;
- }
-
- if (va_size == 0U) {
- ERROR("No regions in resource description.\n");
- panic();
- }
-
- /*
- * Get the power of two that is greater or equal to the top VA. The
- * values of base and size in the resource description are 32-bit wide
- * so the values will never overflow when using a uintptr_t.
- */
- if (!IS_POWER_OF_TWO(va_size)) {
- va_size = 1ULL <<
- ((sizeof(va_size) * 8) - __builtin_clzll(va_size));
- }
-
- if (va_size > PLAT_VIRT_ADDR_SPACE_SIZE) {
- ERROR("Resource description requested too much virtual memory.\n");
- panic();
- }
-
- uintptr_t min_va_size;
-
- /* The following sizes are only valid for 4KB pages */
- assert(PAGE_SIZE == (4U * 1024U));
-
- if (is_armv8_4_ttst_present()) {
- VERBOSE("Using ARMv8.4-TTST\n");
- min_va_size = 1ULL << (64 - TCR_TxSZ_MAX_TTST);
- } else {
- min_va_size = 1ULL << (64 - TCR_TxSZ_MAX);
- }
-
- if (va_size < min_va_size) {
- va_size = min_va_size;
- }
-
- /* Initialize xlat context */
-
- xlat_setup_dynamic_ctx(ctx, PLAT_PHY_ADDR_SPACE_SIZE - 1ULL,
- va_size - 1ULL, mmap,
- PLAT_SP_IMAGE_MMAP_REGIONS, tables,
- PLAT_SP_IMAGE_MAX_XLAT_TABLES, base_table,
- EL1_EL0_REGIME, mapped_regions);
-
- sp_ctx->xlat_ctx_handle = ctx;
-};
-
-/*******************************************************************************
- * Translation table context used for S-EL1 exception vectors
- ******************************************************************************/
-
-REGISTER_XLAT_CONTEXT2(spm_sel1, SPM_SHIM_MMAP_REGIONS, SPM_SHIM_XLAT_TABLES,
- SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE,
- EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME);
-
-void spm_exceptions_xlat_init_context(void)
-{
- /* This region contains the exception vectors used at S-EL1. */
- mmap_region_t sel1_exception_vectors =
- MAP_REGION(SPM_SHIM_EXCEPTIONS_PTR,
- 0x0UL,
- SPM_SHIM_EXCEPTIONS_SIZE,
- MT_CODE | MT_SECURE | MT_PRIVILEGED);
-
- mmap_add_region_ctx(&spm_sel1_xlat_ctx,
- &sel1_exception_vectors);
-
- init_xlat_tables_ctx(&spm_sel1_xlat_ctx);
-}
-
-uint64_t *spm_exceptions_xlat_get_base_table(void)
-{
- return spm_sel1_xlat_ctx.base_table;
-}
-
-/*******************************************************************************
- * Functions to allocate memory for regions.
- ******************************************************************************/
-
-/*
- * The region with base PLAT_SPM_HEAP_BASE and size PLAT_SPM_HEAP_SIZE is
- * reserved for SPM to use as heap to allocate memory regions of Secure
- * Partitions. This is only done at boot.
- */
-static OBJECT_POOL(spm_heap_mem, (void *)PLAT_SPM_HEAP_BASE, 1U,
- PLAT_SPM_HEAP_SIZE);
-
-static uintptr_t spm_alloc_heap(size_t size)
-{
- return (uintptr_t)pool_alloc_n(&spm_heap_mem, size);
-}
-
-/*******************************************************************************
- * Functions to map memory regions described in the resource description.
- ******************************************************************************/
-static unsigned int rdmem_attr_to_mmap_attr(uint32_t attr)
-{
- unsigned int index = attr & RD_MEM_MASK;
-
- const unsigned int mmap_attr_arr[8] = {
- MT_DEVICE | MT_RW | MT_SECURE, /* RD_MEM_DEVICE */
- MT_CODE | MT_SECURE, /* RD_MEM_NORMAL_CODE */
- MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_DATA */
- MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_BSS */
- MT_RO_DATA | MT_SECURE, /* RD_MEM_NORMAL_RODATA */
- MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_SPM_SP_SHARED_MEM */
- MT_MEMORY | MT_RW | MT_SECURE, /* RD_MEM_NORMAL_CLIENT_SHARED_MEM */
- MT_MEMORY | MT_RW | MT_SECURE /* RD_MEM_NORMAL_MISCELLANEOUS */
- };
-
- if (index >= ARRAY_SIZE(mmap_attr_arr)) {
- ERROR("Unsupported RD memory attributes 0x%x\n", attr);
- panic();
- }
-
- return mmap_attr_arr[index];
-}
-
-/*
- * The data provided in the resource description structure is not directly
- * compatible with a mmap_region structure. This function handles the conversion
- * and maps it.
- */
-static void map_rdmem(sp_context_t *sp_ctx, struct sp_rd_sect_mem_region *rdmem)
-{
- int rc;
- mmap_region_t mmap;
-
- /* Location of the SP image */
- uintptr_t sp_size = sp_ctx->image_size;
- uintptr_t sp_base_va = sp_ctx->rd.attribute.load_address;
- unsigned long long sp_base_pa = sp_ctx->image_base;
-
- /* Location of the memory region to map */
- size_t rd_size = rdmem->size;
- uintptr_t rd_base_va = rdmem->base;
- unsigned long long rd_base_pa;
-
- unsigned int memtype = rdmem->attr & RD_MEM_MASK;
-
- if (rd_size == 0U) {
- VERBOSE("Memory region '%s' is empty. Ignored.\n", rdmem->name);
- return;
- }
-
- VERBOSE("Adding memory region '%s'\n", rdmem->name);
-
- mmap.granularity = REGION_DEFAULT_GRANULARITY;
-
- /* Check if the RD region is inside of the SP image or not */
- int is_outside = (rd_base_va + rd_size <= sp_base_va) ||
- (sp_base_va + sp_size <= rd_base_va);
-
- /* Set to 1 if it is needed to zero this region */
- int zero_region = 0;
-
- switch (memtype) {
- case RD_MEM_DEVICE:
- /* Device regions are mapped 1:1 */
- rd_base_pa = rd_base_va;
- break;
-
- case RD_MEM_NORMAL_CODE:
- case RD_MEM_NORMAL_RODATA:
- {
- if (is_outside == 1) {
- ERROR("Code and rodata sections must be fully contained in the image.");
- panic();
- }
-
- /* Get offset into the image */
- rd_base_pa = sp_base_pa + rd_base_va - sp_base_va;
- break;
- }
- case RD_MEM_NORMAL_DATA:
- {
- if (is_outside == 1) {
- ERROR("Data sections must be fully contained in the image.");
- panic();
- }
-
- rd_base_pa = spm_alloc_heap(rd_size);
-
- /* Get offset into the image */
- void *img_pa = (void *)(sp_base_pa + rd_base_va - sp_base_va);
-
- VERBOSE(" Copying data from %p to 0x%llx\n", img_pa, rd_base_pa);
-
- /* Map destination */
- rc = mmap_add_dynamic_region(rd_base_pa, rd_base_pa,
- rd_size, MT_MEMORY | MT_RW | MT_SECURE);
- if (rc != 0) {
- ERROR("Unable to map data region at EL3: %d\n", rc);
- panic();
- }
-
- /* Copy original data to destination */
- memcpy((void *)rd_base_pa, img_pa, rd_size);
-
- /* Unmap destination region */
- rc = mmap_remove_dynamic_region(rd_base_pa, rd_size);
- if (rc != 0) {
- ERROR("Unable to remove data region at EL3: %d\n", rc);
- panic();
- }
-
- break;
- }
- case RD_MEM_NORMAL_MISCELLANEOUS:
- /* Allow SPM to change the attributes of the region. */
- mmap.granularity = PAGE_SIZE;
- rd_base_pa = spm_alloc_heap(rd_size);
- zero_region = 1;
- break;
-
- case RD_MEM_NORMAL_SPM_SP_SHARED_MEM:
- if ((sp_ctx->spm_sp_buffer_base != 0) ||
- (sp_ctx->spm_sp_buffer_size != 0)) {
- ERROR("A partition must have only one SPM<->SP buffer.\n");
- panic();
- }
- rd_base_pa = spm_alloc_heap(rd_size);
- zero_region = 1;
- /* Save location of this buffer, it is needed by SPM */
- sp_ctx->spm_sp_buffer_base = rd_base_pa;
- sp_ctx->spm_sp_buffer_size = rd_size;
- break;
-
- case RD_MEM_NORMAL_CLIENT_SHARED_MEM:
- /* Fallthrough */
- case RD_MEM_NORMAL_BSS:
- rd_base_pa = spm_alloc_heap(rd_size);
- zero_region = 1;
- break;
-
- default:
- panic();
- }
-
- mmap.base_pa = rd_base_pa;
- mmap.base_va = rd_base_va;
- mmap.size = rd_size;
-
- /* Only S-EL0 mappings supported for now */
- mmap.attr = rdmem_attr_to_mmap_attr(rdmem->attr) | MT_USER;
-
- VERBOSE(" VA: 0x%lx PA: 0x%llx (0x%lx, attr: 0x%x)\n",
- mmap.base_va, mmap.base_pa, mmap.size, mmap.attr);
-
- /* Map region in the context of the Secure Partition */
- mmap_add_region_ctx(sp_ctx->xlat_ctx_handle, &mmap);
-
- if (zero_region == 1) {
- VERBOSE(" Zeroing region...\n");
-
- rc = mmap_add_dynamic_region(mmap.base_pa, mmap.base_pa,
- mmap.size, MT_MEMORY | MT_RW | MT_SECURE);
- if (rc != 0) {
- ERROR("Unable to map memory at EL3 to zero: %d\n",
- rc);
- panic();
- }
-
- zeromem((void *)mmap.base_pa, mmap.size);
-
- /*
- * Unmap destination region unless it is the SPM<->SP buffer,
- * which must be used by SPM.
- */
- if (memtype != RD_MEM_NORMAL_SPM_SP_SHARED_MEM) {
- rc = mmap_remove_dynamic_region(rd_base_pa, rd_size);
- if (rc != 0) {
- ERROR("Unable to remove region at EL3: %d\n", rc);
- panic();
- }
- }
- }
-}
-
-void sp_map_memory_regions(sp_context_t *sp_ctx)
-{
- struct sp_rd_sect_mem_region *rdmem;
-
- for (rdmem = sp_ctx->rd.mem_region; rdmem != NULL; rdmem = rdmem->next) {
- map_rdmem(sp_ctx, rdmem);
- }
-
- init_xlat_tables_ctx(sp_ctx->xlat_ctx_handle);
-}
diff --git a/services/std_svc/spm/sprt.c b/services/std_svc/spm/sprt.c
deleted file mode 100644
index 20ad2af..0000000
--- a/services/std_svc/spm/sprt.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <limits.h>
-
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <lib/el3_runtime/context_mgmt.h>
-#include <lib/smccc.h>
-#include <lib/utils.h>
-#include <plat/common/platform.h>
-#include <services/sprt_svc.h>
-#include <smccc_helpers.h>
-
-#include "spm_private.h"
-
-/*******************************************************************************
- * Functions to manipulate memory regions
- ******************************************************************************/
-
-/*
- * Attributes are encoded using a different format in the SMC interface than in
- * the Trusted Firmware, where the mmap_attr_t enum type is used. This function
- * converts an attributes value from the SMC format to the mmap_attr_t format by
- * setting MT_RW/MT_RO, MT_USER/MT_PRIVILEGED and MT_EXECUTE/MT_EXECUTE_NEVER.
- * The other fields are left as 0 because they are ignored by the function
- * xlat_change_mem_attributes_ctx().
- */
-static unsigned int smc_attr_to_mmap_attr(unsigned int attributes)
-{
- unsigned int perm = attributes & SPRT_MEMORY_PERM_ATTR_MASK;
-
- if (perm == SPRT_MEMORY_PERM_ATTR_RW) {
- return MT_RW | MT_EXECUTE_NEVER | MT_USER;
- } else if (perm == SPRT_MEMORY_PERM_ATTR_RO) {
- return MT_RO | MT_EXECUTE_NEVER | MT_USER;
- } else if (perm == SPRT_MEMORY_PERM_ATTR_RO_EXEC) {
- return MT_RO | MT_USER;
- } else {
- return UINT_MAX;
- }
-}
-
-/*
- * This function converts attributes from the Trusted Firmware format into the
- * SMC interface format.
- */
-static unsigned int mmap_attr_to_smc_attr(unsigned int attr)
-{
- unsigned int perm;
-
- /* No access from EL0. */
- if ((attr & MT_USER) == 0U)
- return UINT_MAX;
-
- if ((attr & MT_RW) != 0) {
- assert(MT_TYPE(attr) != MT_DEVICE);
- perm = SPRT_MEMORY_PERM_ATTR_RW;
- } else {
- if ((attr & MT_EXECUTE_NEVER) != 0U) {
- perm = SPRT_MEMORY_PERM_ATTR_RO;
- } else {
- perm = SPRT_MEMORY_PERM_ATTR_RO_EXEC;
- }
- }
-
- return perm << SPRT_MEMORY_PERM_ATTR_SHIFT;
-}
-
-static int32_t sprt_memory_perm_attr_get(sp_context_t *sp_ctx, uintptr_t base_va)
-{
- uint32_t attributes;
-
- spin_lock(&(sp_ctx->xlat_ctx_lock));
-
- int ret = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle,
- base_va, &attributes);
-
- spin_unlock(&(sp_ctx->xlat_ctx_lock));
-
- /* Convert error codes of xlat_get_mem_attributes_ctx() into SPM. */
- assert((ret == 0) || (ret == -EINVAL));
-
- if (ret != 0)
- return SPRT_INVALID_PARAMETER;
-
- unsigned int perm = mmap_attr_to_smc_attr(attributes);
-
- if (perm == UINT_MAX)
- return SPRT_INVALID_PARAMETER;
-
- return SPRT_SUCCESS | perm;
-}
-
-static int32_t sprt_memory_perm_attr_set(sp_context_t *sp_ctx,
- u_register_t page_address, u_register_t pages_count,
- u_register_t smc_attributes)
-{
- int ret;
- uintptr_t base_va = (uintptr_t) page_address;
- size_t size = pages_count * PAGE_SIZE;
-
- VERBOSE(" Start address : 0x%lx\n", base_va);
- VERBOSE(" Number of pages: %i (%zi bytes)\n", (int) pages_count, size);
- VERBOSE(" Attributes : 0x%lx\n", smc_attributes);
-
- uint32_t mmap_attr = smc_attr_to_mmap_attr(smc_attributes);
-
- if (mmap_attr == UINT_MAX) {
- WARN("%s: Invalid memory attributes: 0x%lx\n", __func__,
- smc_attributes);
- return SPRT_INVALID_PARAMETER;
- }
-
- /*
- * Perform some checks before actually trying to change the memory
- * attributes.
- */
-
- spin_lock(&(sp_ctx->xlat_ctx_lock));
-
- uint32_t attributes;
-
- ret = xlat_get_mem_attributes_ctx(sp_ctx->xlat_ctx_handle,
- base_va, &attributes);
-
- if (ret != 0) {
- spin_unlock(&(sp_ctx->xlat_ctx_lock));
- return SPRT_INVALID_PARAMETER;
- }
-
- if ((attributes & MT_USER) == 0U) {
- /* Prohibit changing attributes of S-EL1 regions */
- spin_unlock(&(sp_ctx->xlat_ctx_lock));
- return SPRT_INVALID_PARAMETER;
- }
-
- ret = xlat_change_mem_attributes_ctx(sp_ctx->xlat_ctx_handle,
- base_va, size, mmap_attr);
-
- spin_unlock(&(sp_ctx->xlat_ctx_lock));
-
- /* Convert error codes of xlat_change_mem_attributes_ctx() into SPM. */
- assert((ret == 0) || (ret == -EINVAL));
-
- return (ret == 0) ? SPRT_SUCCESS : SPRT_INVALID_PARAMETER;
-}
-
-/*******************************************************************************
- * This function handles all SMCs in the range reserved for SPRT.
- ******************************************************************************/
-static uintptr_t sprt_smc_handler(uint32_t smc_fid, u_register_t x1,
- u_register_t x2, u_register_t x3,
- u_register_t x4, void *cookie, void *handle,
- u_register_t flags)
-{
- /* SPRT only supported from the Secure world */
- if (is_caller_non_secure(flags) == SMC_FROM_NON_SECURE) {
- SMC_RET1(handle, SMC_UNK);
- }
-
- assert(handle == cm_get_context(SECURE));
-
- /*
- * Only S-EL0 partitions are supported for now. Make the next ERET into
- * the partition jump directly to S-EL0 instead of S-EL1.
- */
- cm_set_elr_spsr_el3(SECURE, read_elr_el1(), read_spsr_el1());
-
- switch (smc_fid) {
- case SPRT_VERSION:
- SMC_RET1(handle, SPRT_VERSION_COMPILED);
-
- case SPRT_PUT_RESPONSE_AARCH64:
- spm_sp_synchronous_exit(SPRT_PUT_RESPONSE_AARCH64);
-
- case SPRT_YIELD_AARCH64:
- spm_sp_synchronous_exit(SPRT_YIELD_AARCH64);
-
- case SPRT_MEMORY_PERM_ATTR_GET_AARCH64:
- {
- /* Get context of the SP in use by this CPU. */
- unsigned int linear_id = plat_my_core_pos();
- sp_context_t *sp_ctx = spm_cpu_get_sp_ctx(linear_id);
-
- SMC_RET1(handle, sprt_memory_perm_attr_get(sp_ctx, x1));
- }
-
- case SPRT_MEMORY_PERM_ATTR_SET_AARCH64:
- {
- /* Get context of the SP in use by this CPU. */
- unsigned int linear_id = plat_my_core_pos();
- sp_context_t *sp_ctx = spm_cpu_get_sp_ctx(linear_id);
-
- SMC_RET1(handle, sprt_memory_perm_attr_set(sp_ctx, x1, x2, x3));
- }
-
- default:
- break;
- }
-
- WARN("SPRT: Unsupported call 0x%08x\n", smc_fid);
- SMC_RET1(handle, SPRT_NOT_SUPPORTED);
-}
-
-DECLARE_RT_SVC(
- sprt_handler,
- OEN_SPRT_START,
- OEN_SPRT_END,
- SMC_TYPE_FAST,
- NULL,
- sprt_smc_handler
-);
diff --git a/services/std_svc/spm_mm/aarch64/spm_helpers.S b/services/std_svc/spm_mm/aarch64/spm_mm_helpers.S
similarity index 96%
rename from services/std_svc/spm_mm/aarch64/spm_helpers.S
rename to services/std_svc/spm_mm/aarch64/spm_mm_helpers.S
index aa35811..2c3aaf7 100644
--- a/services/std_svc/spm_mm/aarch64/spm_helpers.S
+++ b/services/std_svc/spm_mm/aarch64/spm_mm_helpers.S
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
-#include "../spm_private.h"
+#include "../spm_mm_private.h"
.global spm_secure_partition_enter
.global spm_secure_partition_exit
diff --git a/services/std_svc/spm_mm/aarch64/spm_shim_exceptions.S b/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S
similarity index 100%
rename from services/std_svc/spm_mm/aarch64/spm_shim_exceptions.S
rename to services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S
diff --git a/services/std_svc/spm_mm/spm.mk b/services/std_svc/spm_mm/spm.mk
deleted file mode 100644
index 3aa10ee..0000000
--- a/services/std_svc/spm_mm/spm.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifneq (${SPD},none)
- $(error "Error: SPD and SPM are incompatible build options.")
-endif
-ifneq (${ARCH},aarch64)
- $(error "Error: SPM is only supported on aarch64.")
-endif
-
-SPM_SOURCES := $(addprefix services/std_svc/spm_mm/, \
- ${ARCH}/spm_helpers.S \
- ${ARCH}/spm_shim_exceptions.S \
- spm_main.c \
- spm_setup.c \
- spm_xlat.c)
-
-
-# Let the top-level Makefile know that we intend to include a BL32 image
-NEED_BL32 := yes
-
-# required so that SPM code executing at S-EL0 can access the timer registers
-NS_TIMER_SWITCH := 1
diff --git a/services/std_svc/spm_mm/spm_mm.mk b/services/std_svc/spm_mm/spm_mm.mk
new file mode 100644
index 0000000..656488b
--- /dev/null
+++ b/services/std_svc/spm_mm/spm_mm.mk
@@ -0,0 +1,26 @@
+#
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifneq (${SPD},none)
+ $(error "Error: SPD and SPM_MM are incompatible build options.")
+endif
+ifneq (${ARCH},aarch64)
+ $(error "Error: SPM_MM is only supported on aarch64.")
+endif
+
+SPM_SOURCES := $(addprefix services/std_svc/spm_mm/, \
+ ${ARCH}/spm_mm_helpers.S \
+ ${ARCH}/spm_mm_shim_exceptions.S \
+ spm_mm_main.c \
+ spm_mm_setup.c \
+ spm_mm_xlat.c)
+
+
+# Let the top-level Makefile know that we intend to include a BL32 image
+NEED_BL32 := yes
+
+# required so that SPM code executing at S-EL0 can access the timer registers
+NS_TIMER_SWITCH := 1
diff --git a/services/std_svc/spm_mm/spm_main.c b/services/std_svc/spm_mm/spm_mm_main.c
similarity index 88%
rename from services/std_svc/spm_mm/spm_main.c
rename to services/std_svc/spm_mm/spm_mm_main.c
index 706b69d..14c0038 100644
--- a/services/std_svc/spm_mm/spm_main.c
+++ b/services/std_svc/spm_mm/spm_mm_main.c
@@ -18,12 +18,11 @@
#include <lib/utils.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
-#include <services/mm_svc.h>
-#include <services/secure_partition.h>
-#include <services/spm_svc.h>
+#include <services/spm_mm_partition.h>
+#include <services/spm_mm_svc.h>
#include <smccc_helpers.h>
-#include "spm_private.h"
+#include "spm_mm_private.h"
/*******************************************************************************
* Secure Partition context information.
@@ -157,7 +156,7 @@
/*******************************************************************************
* Initialize contexts of all Secure Partitions.
******************************************************************************/
-int32_t spm_setup(void)
+int32_t spm_mm_setup(void)
{
sp_context_t *ctx;
@@ -185,7 +184,7 @@
/*******************************************************************************
* Function to perform a call to a Secure Partition.
******************************************************************************/
-uint64_t spm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3)
+uint64_t spm_mm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3)
{
uint64_t rc;
sp_context_t *sp_ptr = &sp_ctx;
@@ -223,12 +222,12 @@
/* Cookie. Reserved for future use. It must be zero. */
if (mm_cookie != 0U) {
ERROR("MM_COMMUNICATE: cookie is not zero\n");
- SMC_RET1(handle, SPM_INVALID_PARAMETER);
+ SMC_RET1(handle, SPM_MM_INVALID_PARAMETER);
}
if (comm_buffer_address == 0U) {
ERROR("MM_COMMUNICATE: comm_buffer_address is zero\n");
- SMC_RET1(handle, SPM_INVALID_PARAMETER);
+ SMC_RET1(handle, SPM_MM_INVALID_PARAMETER);
}
if (comm_size_address != 0U) {
@@ -251,8 +250,8 @@
/* Save the Normal world context */
cm_el1_sysregs_context_save(NON_SECURE);
- rc = spm_sp_call(smc_fid, comm_buffer_address, comm_size_address,
- plat_my_core_pos());
+ rc = spm_mm_sp_call(smc_fid, comm_buffer_address, comm_size_address,
+ plat_my_core_pos());
/* Restore non-secure state */
cm_el1_sysregs_context_restore(NON_SECURE);
@@ -270,7 +269,7 @@
/*******************************************************************************
* Secure Partition Manager SMC handler.
******************************************************************************/
-uint64_t spm_smc_handler(uint32_t smc_fid,
+uint64_t spm_mm_smc_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
@@ -295,29 +294,29 @@
switch (smc_fid) {
- case SPM_VERSION_AARCH32:
- SMC_RET1(handle, SPM_VERSION_COMPILED);
+ case SPM_MM_VERSION_AARCH32:
+ SMC_RET1(handle, SPM_MM_VERSION_COMPILED);
- case SP_EVENT_COMPLETE_AARCH64:
+ case MM_SP_EVENT_COMPLETE_AARCH64:
spm_sp_synchronous_exit(x1);
- case SP_MEMORY_ATTRIBUTES_GET_AARCH64:
- INFO("Received SP_MEMORY_ATTRIBUTES_GET_AARCH64 SMC\n");
+ case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64:
+ INFO("Received MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 SMC\n");
if (sp_ctx.state != SP_STATE_RESET) {
- WARN("SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n");
- SMC_RET1(handle, SPM_NOT_SUPPORTED);
+ WARN("MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n");
+ SMC_RET1(handle, SPM_MM_NOT_SUPPORTED);
}
SMC_RET1(handle,
spm_memory_attributes_get_smc_handler(
&sp_ctx, x1));
- case SP_MEMORY_ATTRIBUTES_SET_AARCH64:
- INFO("Received SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n");
+ case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64:
+ INFO("Received MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n");
if (sp_ctx.state != SP_STATE_RESET) {
- WARN("SP_MEMORY_ATTRIBUTES_SET_AARCH64 is available at boot time only\n");
- SMC_RET1(handle, SPM_NOT_SUPPORTED);
+ WARN("MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 is available at boot time only\n");
+ SMC_RET1(handle, SPM_MM_NOT_SUPPORTED);
}
SMC_RET1(handle,
spm_memory_attributes_set_smc_handler(
@@ -340,10 +339,10 @@
case MM_COMMUNICATE_AARCH64:
return mm_communicate(smc_fid, x1, x2, x3, handle);
- case SP_MEMORY_ATTRIBUTES_GET_AARCH64:
- case SP_MEMORY_ATTRIBUTES_SET_AARCH64:
+ case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64:
+ case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64:
/* SMC interfaces reserved for secure callers. */
- SMC_RET1(handle, SPM_NOT_SUPPORTED);
+ SMC_RET1(handle, SPM_MM_NOT_SUPPORTED);
default:
break;
diff --git a/services/std_svc/spm_mm/spm_private.h b/services/std_svc/spm_mm/spm_mm_private.h
similarity index 92%
rename from services/std_svc/spm_mm/spm_private.h
rename to services/std_svc/spm_mm/spm_mm_private.h
index ba94a4d..45b4789 100644
--- a/services/std_svc/spm_mm/spm_private.h
+++ b/services/std_svc/spm_mm/spm_mm_private.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef SPM_PRIVATE_H
-#define SPM_PRIVATE_H
+#ifndef SPM_MM_PRIVATE_H
+#define SPM_MM_PRIVATE_H
#include <context.h>
@@ -68,4 +68,4 @@
#endif /* __ASSEMBLER__ */
-#endif /* SPM_PRIVATE_H */
+#endif /* SPM_MM_PRIVATE_H */
diff --git a/services/std_svc/spm_mm/spm_setup.c b/services/std_svc/spm_mm/spm_mm_setup.c
similarity index 90%
rename from services/std_svc/spm_mm/spm_setup.c
rename to services/std_svc/spm_mm/spm_mm_setup.c
index aae6cd5..ccb2f90 100644
--- a/services/std_svc/spm_mm/spm_setup.c
+++ b/services/std_svc/spm_mm/spm_mm_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,10 +16,10 @@
#include <platform_def.h>
#include <plat/common/common_def.h>
#include <plat/common/platform.h>
-#include <services/secure_partition.h>
+#include <services/spm_mm_partition.h>
-#include "spm_private.h"
-#include "spm_shim_private.h"
+#include "spm_mm_private.h"
+#include "spm_mm_shim_private.h"
/* Setup context of the Secure Partition */
void spm_sp_setup(sp_context_t *sp_ctx)
@@ -192,22 +192,22 @@
void *shared_buf_ptr = (void *) PLAT_SPM_BUF_BASE;
/* Copy the boot information into the shared buffer with the SP. */
- assert((uintptr_t)shared_buf_ptr + sizeof(secure_partition_boot_info_t)
+ assert((uintptr_t)shared_buf_ptr + sizeof(spm_mm_boot_info_t)
<= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE));
assert(PLAT_SPM_BUF_BASE <= (UINTPTR_MAX - PLAT_SPM_BUF_SIZE + 1));
- const secure_partition_boot_info_t *sp_boot_info =
+ const spm_mm_boot_info_t *sp_boot_info =
plat_get_secure_partition_boot_info(NULL);
assert(sp_boot_info != NULL);
memcpy((void *) shared_buf_ptr, (const void *) sp_boot_info,
- sizeof(secure_partition_boot_info_t));
+ sizeof(spm_mm_boot_info_t));
/* Pointer to the MP information from the platform port. */
- secure_partition_mp_info_t *sp_mp_info =
- ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info;
+ spm_mm_mp_info_t *sp_mp_info =
+ ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info;
assert(sp_mp_info != NULL);
@@ -215,15 +215,15 @@
* Point the shared buffer MP information pointer to where the info will
* be populated, just after the boot info.
*/
- ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info =
- (secure_partition_mp_info_t *) ((uintptr_t)shared_buf_ptr
- + sizeof(secure_partition_boot_info_t));
+ ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info =
+ (spm_mm_mp_info_t *) ((uintptr_t)shared_buf_ptr
+ + sizeof(spm_mm_boot_info_t));
/*
* Update the shared buffer pointer to where the MP information for the
* payload will be populated
*/
- shared_buf_ptr = ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info;
+ shared_buf_ptr = ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info;
/*
* Copy the cpu information into the shared buffer area after the boot
@@ -242,7 +242,7 @@
* Calculate the linear indices of cores in boot information for the
* secure partition and flag the primary CPU
*/
- sp_mp_info = (secure_partition_mp_info_t *) shared_buf_ptr;
+ sp_mp_info = (spm_mm_mp_info_t *) shared_buf_ptr;
for (unsigned int index = 0; index < sp_boot_info->num_cpus; index++) {
u_register_t mpidr = sp_mp_info[index].mpidr;
diff --git a/services/std_svc/spm_mm/spm_shim_private.h b/services/std_svc/spm_mm/spm_mm_shim_private.h
similarity index 76%
rename from services/std_svc/spm_mm/spm_shim_private.h
rename to services/std_svc/spm_mm/spm_mm_shim_private.h
index 7fe9692..0c8d894 100644
--- a/services/std_svc/spm_mm/spm_shim_private.h
+++ b/services/std_svc/spm_mm/spm_mm_shim_private.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef SPM_SHIM_PRIVATE_H
-#define SPM_SHIM_PRIVATE_H
+#ifndef SPM_MM_SHIM_PRIVATE_H
+#define SPM_MM_SHIM_PRIVATE_H
#include <stdint.h>
@@ -23,4 +23,4 @@
#define SPM_SHIM_EXCEPTIONS_SIZE \
(SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START)
-#endif /* SPM_SHIM_PRIVATE_H */
+#endif /* SPM_MM_SHIM_PRIVATE_H */
diff --git a/services/std_svc/spm_mm/spm_xlat.c b/services/std_svc/spm_mm/spm_mm_xlat.c
similarity index 78%
rename from services/std_svc/spm_mm/spm_xlat.c
rename to services/std_svc/spm_mm/spm_mm_xlat.c
index f54168e..6c02f07 100644
--- a/services/std_svc/spm_mm/spm_xlat.c
+++ b/services/std_svc/spm_mm/spm_mm_xlat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,11 +11,11 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <platform_def.h>
#include <plat/common/platform.h>
-#include <services/secure_partition.h>
-#include <services/spm_svc.h>
+#include <services/spm_mm_partition.h>
+#include <services/spm_mm_svc.h>
-#include "spm_private.h"
-#include "spm_shim_private.h"
+#include "spm_mm_private.h"
+#include "spm_mm_shim_private.h"
/* Place translation tables by default along with the ones used by BL31. */
#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME
@@ -50,21 +50,21 @@
{
unsigned int tf_attr = 0U;
- unsigned int access = (attributes & SP_MEMORY_ATTRIBUTES_ACCESS_MASK)
- >> SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT;
+ unsigned int access = (attributes & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK)
+ >> MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT;
- if (access == SP_MEMORY_ATTRIBUTES_ACCESS_RW) {
+ if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW) {
tf_attr |= MT_RW | MT_USER;
- } else if (access == SP_MEMORY_ATTRIBUTES_ACCESS_RO) {
+ } else if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO) {
tf_attr |= MT_RO | MT_USER;
} else {
/* Other values are reserved. */
- assert(access == SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS);
+ assert(access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS);
/* The only requirement is that there's no access from EL0 */
tf_attr |= MT_RO | MT_PRIVILEGED;
}
- if ((attributes & SP_MEMORY_ATTRIBUTES_NON_EXEC) == 0) {
+ if ((attributes & MM_SP_MEMORY_ATTRIBUTES_NON_EXEC) == 0) {
tf_attr |= MT_EXECUTE;
} else {
tf_attr |= MT_EXECUTE_NEVER;
@@ -85,21 +85,21 @@
if ((attr & MT_USER) == 0) {
/* No access from EL0. */
- data_access = SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS;
+ data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS;
} else {
if ((attr & MT_RW) != 0) {
assert(MT_TYPE(attr) != MT_DEVICE);
- data_access = SP_MEMORY_ATTRIBUTES_ACCESS_RW;
+ data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW;
} else {
- data_access = SP_MEMORY_ATTRIBUTES_ACCESS_RO;
+ data_access = MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO;
}
}
- smc_attr |= (data_access & SP_MEMORY_ATTRIBUTES_ACCESS_MASK)
- << SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT;
+ smc_attr |= (data_access & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK)
+ << MM_SP_MEMORY_ATTRIBUTES_ACCESS_SHIFT;
if ((attr & MT_EXECUTE_NEVER) != 0U) {
- smc_attr |= SP_MEMORY_ATTRIBUTES_NON_EXEC;
+ smc_attr |= MM_SP_MEMORY_ATTRIBUTES_NON_EXEC;
}
return smc_attr;
@@ -123,7 +123,7 @@
if (rc == 0) {
return (int32_t) smc_mmap_to_smc_attr(attributes);
} else {
- return SPM_INVALID_PARAMETER;
+ return SPM_MM_INVALID_PARAMETER;
}
}
@@ -151,5 +151,5 @@
/* Convert error codes of xlat_change_mem_attributes_ctx() into SPM. */
assert((ret == 0) || (ret == -EINVAL));
- return (ret == 0) ? SPM_SUCCESS : SPM_INVALID_PARAMETER;
+ return (ret == 0) ? SPM_MM_SUCCESS : SPM_MM_INVALID_PARAMETER;
}
diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c
index 1d80fa3..7787a2f 100644
--- a/services/std_svc/std_svc_setup.c
+++ b/services/std_svc/std_svc_setup.c
@@ -14,7 +14,7 @@
#include <lib/psci/psci.h>
#include <lib/runtime_instr.h>
#include <services/sdei.h>
-#include <services/spm_svc.h>
+#include <services/spm_mm_svc.h>
#include <services/std_svc.h>
#include <smccc_helpers.h>
#include <tools_share/uuid.h>
@@ -45,8 +45,8 @@
ret = 1;
}
-#if ENABLE_SPM
- if (spm_setup() != 0) {
+#if SPM_MM
+ if (spm_mm_setup() != 0) {
ret = 1;
}
#endif
@@ -103,14 +103,14 @@
SMC_RET1(handle, ret);
}
-#if ENABLE_SPM && SPM_MM
+#if SPM_MM
/*
* Dispatch SPM calls to SPM SMC handler and return its return
* value
*/
- if (is_spm_fid(smc_fid)) {
- return spm_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
- handle, flags);
+ if (is_spm_mm_fid(smc_fid)) {
+ return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
+ handle, flags);
}
#endif