Merge "Simplify PMF helper macro definitions across header files" into integration
diff --git a/docs/getting_started/initial-build.rst b/docs/getting_started/initial-build.rst
index 41cd4d1..893aba2 100644
--- a/docs/getting_started/initial-build.rst
+++ b/docs/getting_started/initial-build.rst
@@ -8,13 +8,13 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
For AArch32:
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
+ export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-none-eabi-
It is possible to build TF-A using Clang or Arm Compiler 6. To do so
``CC`` needs to point to the clang or armclang binary, which will
@@ -32,7 +32,7 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
Clang will be selected when the base name of the path assigned to ``CC``
@@ -43,7 +43,7 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
make CC=<path-to-clang>/bin/clang PLAT=<platform> all
- Change to the root directory of the TF-A source tree and build.
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 27ad0ed..3e0c8ff 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -26,7 +26,7 @@
|TF-A| can be built with any of the following *cross-compiler* toolchains that
target the Armv7-A or Armv8-A architectures:
-- GCC >= 8.3-2019.03 (from the `Arm Developer website`_)
+- GCC >= 9.2-2019.12 (from the `Arm Developer website`_)
- Clang >= 4.0
- Arm Compiler >= 6.0
diff --git a/docs/plat/allwinner.rst b/docs/plat/allwinner.rst
index a1e0659..5c905d8 100644
--- a/docs/plat/allwinner.rst
+++ b/docs/plat/allwinner.rst
@@ -26,13 +26,13 @@
.. code:: shell
- make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=sun50i_a64 DEBUG=1 bl31
To build for machines with an H6 SoC:
.. code:: shell
- make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=sun50i_h6 DEBUG=1 bl31
.. _U-Boot documentation: http://git.denx.de/?p=u-boot.git;f=board/sunxi/README.sunxi64;hb=HEAD
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index b6396b9..37010e1 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -223,7 +223,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- \
+ CROSS_COMPILE=aarch64-none-elf- \
make PLAT=fvp DEBUG=1 \
RESET_TO_BL31=1 \
ARM_LINUX_KERNEL_AS_BL33=1 \
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
index 6429ede..cf328fa 100644
--- a/docs/plat/arm/juno/index.rst
+++ b/docs/plat/arm/juno/index.rst
@@ -136,7 +136,7 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
- The following parameters should be used to build BL1 and BL2 in AArch64
and point to the BL32 file.
diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst
index 372d388..d7a01a8 100644
--- a/docs/plat/hikey.rst
+++ b/docs/plat/hikey.rst
@@ -78,7 +78,7 @@
EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey/${BUILD_OPTION}_${AARCH64_TOOLCHAIN}
# Build fastboot for Trusted Firmware-A. It's used for recovery mode.
cd ${BUILD_PATH}/atf-fastboot
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=hikey DEBUG=1
+ CROSS_COMPILE=aarch64-none-elf- make PLAT=hikey DEBUG=1
# Convert DEBUG/RELEASE to debug/release
FASTBOOT_BUILD_OPTION=$(echo ${BUILD_OPTION} | tr '[A-Z]' '[a-z]')
cd ${EDK2_DIR}
diff --git a/docs/plat/imx8.rst b/docs/plat/imx8.rst
index 49ba374..cec1a39 100644
--- a/docs/plat/imx8.rst
+++ b/docs/plat/imx8.rst
@@ -40,7 +40,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=<Target_SoC> bl31
+ CROSS_COMPILE=aarch64-none-elf- make PLAT=<Target_SoC> bl31
Target_SoC should be "imx8qm" for i.MX8QM SoC.
Target_SoC should be "imx8qx" for i.MX8QX SoC.
diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst
index 8acd13c..0116b34 100644
--- a/docs/plat/imx8m.rst
+++ b/docs/plat/imx8m.rst
@@ -28,7 +28,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=<Target_SoC> bl31
+ CROSS_COMPILE=aarch64-none-elf- make PLAT=<Target_SoC> bl31
Target_SoC should be "imx8mq" for i.MX8MQ SoC.
Target_SoC should be "imx8mm" for i.MX8MM SoC.
diff --git a/docs/plat/intel-agilex.rst b/docs/plat/intel-agilex.rst
index ff27b6b..f60bf14 100644
--- a/docs/plat/intel-agilex.rst
+++ b/docs/plat/intel-agilex.rst
@@ -41,7 +41,7 @@
.. code:: bash
- make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=agilex
+ make CROSS_COMPILE=aarch64-none-elf- bl2 fip PLAT=agilex
BL33=PEI.ROM
Install Procedure
diff --git a/docs/plat/intel-stratix10.rst b/docs/plat/intel-stratix10.rst
index 7f8d18e..5f33d12 100644
--- a/docs/plat/intel-stratix10.rst
+++ b/docs/plat/intel-stratix10.rst
@@ -41,7 +41,7 @@
.. code:: bash
- make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=stratix10
+ make CROSS_COMPILE=aarch64-none-elf- bl2 fip PLAT=stratix10
BL33=PEI.ROM
Install Procedure
diff --git a/docs/plat/ls1043a.rst b/docs/plat/ls1043a.rst
index 72a51f3..5a8f755 100644
--- a/docs/plat/ls1043a.rst
+++ b/docs/plat/ls1043a.rst
@@ -59,13 +59,13 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 bl1
+ CROSS_COMPILE=aarch64-none-elf- make PLAT=ls1043 bl1
Build fip:
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 fip \
+ CROSS_COMPILE=aarch64-none-elf- make PLAT=ls1043 fip \
BL33=u-boot.bin NEED_BL32=yes BL32=tee.bin SPD=opteed
Deploy TF-A Images
diff --git a/docs/plat/marvell/build.rst b/docs/plat/marvell/build.rst
index c10bcff..d0e37c6 100644
--- a/docs/plat/marvell/build.rst
+++ b/docs/plat/marvell/build.rst
@@ -9,7 +9,7 @@
.. code:: shell
- > export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu-
+ > export CROSS_COMPILE=/path/to/toolchain/aarch64-none-elf-
(2) Set path for FIP images:
diff --git a/docs/plat/meson-g12a.rst b/docs/plat/meson-g12a.rst
index 7cd1bf7..8b06cc2 100644
--- a/docs/plat/meson-g12a.rst
+++ b/docs/plat/meson-g12a.rst
@@ -17,7 +17,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=g12a
+ CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=g12a
This port has been tested on a SEI510 board. After building it, follow the
instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the
diff --git a/docs/plat/meson-gxbb.rst b/docs/plat/meson-gxbb.rst
index 2cd8342..f891ecd 100644
--- a/docs/plat/meson-gxbb.rst
+++ b/docs/plat/meson-gxbb.rst
@@ -17,7 +17,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxbb bl31
+ CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=gxbb bl31
This port has been tested in a ODROID-C2. After building it, follow the
instructions in the `U-Boot repository`_, replacing the mentioned **bl31.bin**
diff --git a/docs/plat/meson-gxl.rst b/docs/plat/meson-gxl.rst
index c6d8504..170d7c7 100644
--- a/docs/plat/meson-gxl.rst
+++ b/docs/plat/meson-gxl.rst
@@ -17,7 +17,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxl
+ CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=gxl
This port has been tested on a Lepotato. After building it, follow the
instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the
diff --git a/docs/plat/mt8183.rst b/docs/plat/mt8183.rst
index c639be1..7a0830f 100644
--- a/docs/plat/mt8183.rst
+++ b/docs/plat/mt8183.rst
@@ -17,4 +17,4 @@
.. code:: shell
- make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8183 DEBUG=1
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=mt8183 DEBUG=1
diff --git a/docs/plat/poplar.rst b/docs/plat/poplar.rst
index 215f551..040b593 100644
--- a/docs/plat/poplar.rst
+++ b/docs/plat/poplar.rst
@@ -68,7 +68,7 @@
.. code:: bash
- make CROSS_COMPILE=aarch64-linux-gnu- all fip SPD=none PLAT=poplar
+ make CROSS_COMPILE=aarch64-none-elf- all fip SPD=none PLAT=poplar
BL33=u-boot.bin
- Build l-loader (generated the final fastboot.bin)
diff --git a/docs/plat/qemu-sbsa.rst b/docs/plat/qemu-sbsa.rst
index 51fe414..5e8535c 100644
--- a/docs/plat/qemu-sbsa.rst
+++ b/docs/plat/qemu-sbsa.rst
@@ -27,7 +27,7 @@
git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa
cd tfa
- export CROSS_COMPILE=aarch64-linux-gnu-
+ export CROSS_COMPILE=aarch64-none-elf-
make PLAT=qemu_sbsa all fip
Images will be placed at build/qemu_sbsa/release (bl1.bin and fip.bin).
diff --git a/docs/plat/rockchip.rst b/docs/plat/rockchip.rst
index b7c43fb..2c3c38f 100644
--- a/docs/plat/rockchip.rst
+++ b/docs/plat/rockchip.rst
@@ -35,7 +35,7 @@
For AARCH64 architectures the build command looks like
- make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl32
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=rk3399 bl32
while AARCH32 needs a slightly different command
diff --git a/docs/plat/rpi3.rst b/docs/plat/rpi3.rst
index 38c3dfa..5c7b6d5 100644
--- a/docs/plat/rpi3.rst
+++ b/docs/plat/rpi3.rst
@@ -315,7 +315,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \
+ CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \
RPI3_BL33_IN_AARCH32=1 \
BL33=../rpi3-arm-tf-bootstrap/aarch32/el2-bootstrap.bin
@@ -323,7 +323,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \
+ CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \
BL33=../rpi3-arm-tf-bootstrap/aarch64/el2-bootstrap.bin
However, enabling PSCI support in a 64-bit kernel is really easy. In the
@@ -340,7 +340,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \
+ CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \
PRELOADED_BL33_BASE=0x02000000 \
RPI3_PRELOADED_DTB_BASE=0x01000000 \
RPI3_DIRECT_LINUX_BOOT=1
@@ -349,7 +349,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi3 \
+ CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi3 \
PRELOADED_BL33_BASE=0x02000000 \
RPI3_PRELOADED_DTB_BASE=0x01000000 \
RPI3_DIRECT_LINUX_BOOT=1 \
diff --git a/docs/plat/rpi4.rst b/docs/plat/rpi4.rst
index 0f529c1..e87aef7 100644
--- a/docs/plat/rpi4.rst
+++ b/docs/plat/rpi4.rst
@@ -22,7 +22,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi4 DEBUG=1
+ CROSS_COMPILE=aarch64-none-elf- make PLAT=rpi4 DEBUG=1
Copy the generated build/rpi4/debug/bl31.bin to the SD card, either
renaming it to ``armstub8.bin`` or adding an entry starting with ``armstub=``,
diff --git a/docs/plat/ti-k3.rst b/docs/plat/ti-k3.rst
index 4843227..2626e67 100644
--- a/docs/plat/ti-k3.rst
+++ b/docs/plat/ti-k3.rst
@@ -27,7 +27,7 @@
.. code:: shell
- make CROSS_COMPILE=aarch64-linux-gnu- PLAT=k3 SPD=opteed all
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=k3 SPD=opteed all
OP-TEE:
diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts
index fc8783d..31d635a 100644
--- a/fdts/a5ds.dts
+++ b/fdts/a5ds.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -64,13 +64,20 @@
arm,tag-latency = <1 1 1>;
};
- refclk100mhz: refclk100mhz {
+ refclk7500khz: refclk7500khz {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <100000000>;
+ clock-frequency = <7500000>;
clock-output-names = "apb_pclk";
};
+ refclk24mhz: refclk24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "apb_pclk";
+ };
+
smbclk: refclk24mhzx2 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -82,7 +89,7 @@
rtc@1a220000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x1a220000 0x1000>;
- clocks = <&refclk100mhz>;
+ clocks = <&refclk24mhz>;
interrupts = <0 6 0xf04>;
clock-names = "apb_pclk";
};
@@ -102,7 +109,7 @@
reg = <0x1a200000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 8 0xf04>;
- clocks = <&refclk100mhz>;
+ clocks = <&refclk7500khz>;
clock-names = "apb_pclk";
};
@@ -111,7 +118,7 @@
reg = <0x1a210000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 9 0xf04>;
- clocks = <&refclk100mhz>;
+ clocks = <&refclk7500khz>;
clock-names = "apb_pclk";
};
diff --git a/plat/arm/board/a5ds/a5ds_common.c b/plat/arm/board/a5ds/a5ds_common.c
index e462fa1..a4a0cff 100644
--- a/plat/arm/board/a5ds/a5ds_common.c
+++ b/plat/arm/board/a5ds/a5ds_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,18 +23,18 @@
#ifdef IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
- MAP_FLASH1_RW,
MAP_PERIPHBASE,
MAP_A5_PERIPHERALS,
+ MAP_BOOT_RW,
{0}
};
#endif
#ifdef IMAGE_BL2
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
- MAP_FLASH1_RW,
MAP_PERIPHBASE,
MAP_A5_PERIPHERALS,
+ MAP_BOOT_RW,
ARM_MAP_NS_DRAM1,
{0}
};
diff --git a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
index 9ab2d96..7b3aa11 100644
--- a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
+++ b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,7 @@
/* Platform Config */
plat_arm_bl2 {
compatible = "arm,tb_fw";
- hw_config_addr = <0x0 0x82000000>;
+ hw_config_addr = <0x0 0x83000000>;
hw_config_max_size = <0x01000000>;
/* Disable authentication for development */
disable_auth = <0x0>;
diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h
index d200af6..4c87c22 100644
--- a/plat/arm/board/a5ds/include/platform_def.h
+++ b/plat/arm/board/a5ds/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,14 +21,6 @@
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - 1)
-#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
-/*
- * The last 2MB is meant to be NOLOAD and will not be zero
- * initialized.
- */
-#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
- 0x00200000)
-
#define SRAM_BASE 0x2000000
#define SRAM_SIZE 0x200000
@@ -47,7 +39,7 @@
#define A5_PERIPHERALS_BASE 0x1c000000
#define A5_PERIPHERALS_SIZE 0x10000
-#define ARM_CACHE_WRITEBACK_SHIFT 6
+#define ARM_CACHE_WRITEBACK_SHIFT 5
#define ARM_IRQ_SEC_PHY_TIMER 29
@@ -101,16 +93,22 @@
#define A5DS_PRIMARY_CPU 0x0
-#define FLASH1_BASE UL(0x8000000)
-#define FLASH1_SIZE UL(0x2800000)
+#define BOOT_BASE ARM_DRAM1_BASE
+#define BOOT_SIZE UL(0x2800000)
-#define MAP_FLASH1_RW MAP_REGION_FLAT(FLASH1_BASE,\
- FLASH1_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+#define ARM_NS_DRAM1_BASE (ARM_DRAM1_BASE + BOOT_SIZE)
+/*
+ * The last 2MB is meant to be NOLOAD and will not be zero
+ * initialized.
+ */
+#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
+ BOOT_SIZE - \
+ 0x00200000)
-#define MAP_FLASH1_RO MAP_REGION_FLAT(FLASH1_BASE,\
- FLASH1_SIZE, \
- MT_RO_DATA | MT_SECURE)
+#define MAP_BOOT_RW MAP_REGION_FLAT( \
+ BOOT_BASE, \
+ BOOT_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
A5DS_SHARED_RAM_BASE, \
@@ -122,9 +120,9 @@
ARM_NS_DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
-#define ARM_MAP_SRAM MAP_REGION_FLAT( \
- SRAM_BASE, \
- SRAM_SIZE, \
+#define ARM_MAP_SRAM MAP_REGION_FLAT( \
+ SRAM_BASE, \
+ SRAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
/*
@@ -162,7 +160,7 @@
ARM_BL_REGIONS)
/* Memory mapped Generic timer interfaces */
-#define A5DS_TIMER_BASE_FREQUENCY UL(24000000)
+#define A5DS_TIMER_BASE_FREQUENCY UL(7500000)
#define ARM_CONSOLE_BAUDRATE 115200
@@ -300,25 +298,25 @@
#define MAX_IO_HANDLES 4
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE FLASH1_BASE
-#define PLAT_ARM_FIP_MAX_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FIP_BASE BOOT_BASE
+#define PLAT_ARM_FIP_MAX_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
-#define PLAT_ARM_NVM_BASE FLASH1_BASE
-#define PLAT_ARM_NVM_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_NVM_BASE BOOT_BASE
+#define PLAT_ARM_NVM_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
/*
* PL011 related constants
*/
#define PLAT_ARM_BOOT_UART_BASE 0x1A200000
-#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 24000000
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ UL(7500000)
#define PLAT_ARM_RUN_UART_BASE 0x1A210000
-#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ UL(7500000)
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
-#define A5DS_TIMER_BASE_FREQUENCY UL(24000000)
+#define A5DS_TIMER_BASE_FREQUENCY UL(7500000)
/* System timer related constants */
#define PLAT_ARM_NSTIMER_FRAME_ID 1
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index 1dd1f51..536ed57 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -165,7 +165,7 @@
/* sanity check the core ID value */
if (core > (uint32_t)PLATFORM_CORE_COUNT) {
ERROR("%s: unknown core id (%d)\n", __func__, core);
- ret = EINVAL;
+ ret = -EINVAL;
} else {
/* get a core online */
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE,
@@ -183,15 +183,15 @@
*/
int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
{
- int32_t ret;
+ int32_t ret = 0;
/* sanity check GSC ID */
if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) {
ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx);
- ret = EINVAL;
+ ret = -EINVAL;
} else {
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,
- (uint64_t)gsc_idx);
+ (uint64_t)gsc_idx);
}
return ret;
@@ -209,11 +209,12 @@
ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
if (nvg_cache_clean() == 0U) {
ERROR("%s: failed\n", __func__);
- ret = EINVAL;
+ ret = -ENODEV;
}
} else {
- ret = EINVAL;
+ ret = -ENOTSUP;
}
+
return ret;
}
@@ -229,11 +230,12 @@
ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
if (nvg_cache_clean_inval() == 0U) {
ERROR("%s: failed\n", __func__);
- ret = EINVAL;
+ ret = -ENODEV;
}
} else {
- ret = EINVAL;
+ ret = -ENOTSUP;
}
+
return ret;
}
@@ -249,11 +251,12 @@
ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
if (nvg_cache_inval_all() == 0U) {
ERROR("%s: failed\n", __func__);
- ret = EINVAL;
+ ret = -ENODEV;
}
} else {
- ret = EINVAL;
+ ret = -ENOTSUP;
}
+
return ret;
}
@@ -271,8 +274,8 @@
(state != (uint32_t)TEGRA_NVG_CORE_C6) &&
(state != (uint32_t)TEGRA_NVG_CORE_C7))
{
- ERROR("%s: unknown cstate (%d)\n", __func__, state);
- ret = EINVAL;
+ ERROR("%s: unknown cstate (%u)\n", __func__, state);
+ ret = -EINVAL;
} else {
/* time (TSC ticks) until the core is expected to get a wake event */
nvg_set_wake_time(wake_time);