plat/arm: use Aff3 bits also to validate mpidr
There are some platforms which uses MPIDR Affinity level 3 for storing
extra affinity information e.g. N1SDP uses it for keeping chip id in a
multichip setup, for such platforms MPIDR validation should not fail.
This patch adds Aff3 bits also as part of mpidr validation mask, for
platforms which does not uses Aff3 will not have any impact as these
bits will be all zeros.
Change-Id: Ia8273972fa7948fdb11708308d0239d2dc4dfa85
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
diff --git a/plat/arm/common/arm_topology.c b/plat/arm/common/arm_topology.c
index 37047bc..c9993a7 100644
--- a/plat/arm/common/arm_topology.c
+++ b/plat/arm/common/arm_topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,7 +24,8 @@
valid_mask = ~(MPIDR_AFFLVL_MASK |
(MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) |
- (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT));
+ (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) |
+ (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT));
cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK;
cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;