diff --git a/plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h b/plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h
new file mode 100644
index 0000000..92bf484
--- /dev/null
+++ b/plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FVP_R_ARCH_HELPERS_H
+#define FVP_R_ARCH_HELPERS_H
+
+#include <arch_helpers.h>
+
+/*******************************************************************************
+ * MPU register definitions
+ ******************************************************************************/
+#define MPUIR_EL2		S3_4_C0_C0_4
+#define PRBAR_EL2		S3_4_C6_C8_0
+#define PRLAR_EL2		S3_4_C6_C8_1
+#define PRSELR_EL2		S3_4_C6_C2_1
+#define PRENR_EL2		S3_4_C6_C1_1
+
+/* v8-R64 MPU registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(mpuir_el2, MPUIR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(prenr_el2, PRENR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(prselr_el2, PRSELR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(prbar_el2, PRBAR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(prlar_el2, PRLAR_EL2)
+
+#endif /* FVP_R_ARCH_HELPERS_H */
diff --git a/plat/arm/board/fvp_r/include/platform_def.h b/plat/arm/board/fvp_r/include/platform_def.h
index 4586681..725d131 100644
--- a/plat/arm/board/fvp_r/include/platform_def.h
+++ b/plat/arm/board/fvp_r/include/platform_def.h
@@ -4,19 +4,37 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
+#ifndef FVP_R_PLATFORM_DEF_H
+#define FVP_R_PLATFORM_DEF_H
+
+#define PLAT_V2M_OFFSET			0x80000000
 
 #include "../fvp_r_def.h"
 #include <drivers/arm/tzc400.h>
 #include <lib/utils_def.h>
 #include <plat/arm/board/common/v2m_def.h>
 
+/* These are referenced by arm_def.h #included next, so #define first. */
+#define PLAT_ARM_TRUSTED_ROM_BASE	UL(0x80000000)
+#define PLAT_ARM_TRUSTED_SRAM_BASE	UL(0x84000000)
+#define PLAT_ARM_TRUSTED_DRAM_BASE	UL(0x86000000)
+#define PLAT_ARM_DRAM1_BASE		ULL(0x0)
+#define PLAT_ARM_DRAM2_BASE		ULL(0x080000000)
+
+#define PLAT_HW_CONFIG_DTB_BASE		ULL(0x12000000)
+#define PLAT_ARM_SYS_CNTCTL_BASE	UL(0xaa430000)
+#define PLAT_ARM_SYS_CNTREAD_BASE	UL(0xaa800000)
+#define PLAT_ARM_SYS_TIMCTL_BASE	UL(0xaa810000)
+#define PLAT_ARM_SYS_CNT_BASE_S		UL(0xaa820000)
+#define PLAT_ARM_SYS_CNT_BASE_NS	UL(0xaa830000)
+#define PLAT_ARM_SP805_TWDG_BASE	UL(0xaa490000)
+
 #include <plat/arm/common/arm_def.h>
 #include <plat/common/common_def.h>
 
 
-#define NO_EL3				1
+/* Required to create plat_regions: */
+#define MIN_LVL_BLOCK_DESC	U(1)
 
 /* Required platform porting definitions */
 #define PLATFORM_CORE_COUNT  (U(FVP_R_CLUSTER_COUNT) * \
@@ -36,34 +54,35 @@
  * Required ARM standard platform porting definitions
  */
 #define PLAT_ARM_CLUSTER_COUNT		U(FVP_R_CLUSTER_COUNT)
-
-#define PLAT_ARM_DRAM1_BASE		ULL(0x0)
-
-#define PLAT_ARM_TRUSTED_ROM_BASE	UL(0x80000000)
-#define PLAT_ARM_TRUSTED_ROM_SIZE	UL(0x04000000)	/* 64 MB */
-
-#define PLAT_ARM_TRUSTED_SRAM_BASE	UL(0x84000000)
+#define PLAT_ARM_DRAM1_SIZE		ULL(0x7fffffff)
 #define PLAT_ARM_TRUSTED_SRAM_SIZE	UL(0x00040000)	/* 256 KB */
-
-#define PLAT_ARM_TRUSTED_DRAM_BASE	UL(0x86000000)
+#define PLAT_ARM_TRUSTED_ROM_SIZE	UL(0x04000000)	/* 64 MB */
 #define PLAT_ARM_TRUSTED_DRAM_SIZE	UL(0x02000000)	/* 32 MB */
 
+/* These two are defined thus in arm_def.h, but doesn't seem to see it... */
+#undef	BL1_RO_BASE
+#define	BL1_RO_BASE			PLAT_ARM_TRUSTED_ROM_BASE
+#undef	BL1_RO_LIMIT
+#define	BL1_RO_LIMIT			(BL1_RO_BASE \
+					+ PLAT_ARM_TRUSTED_ROM_SIZE)
+
 /* virtual address used by dynamic mem_protect for chunk_base */
 #define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
 
 /* No SCP in FVP_R */
 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE	UL(0x0)
 
-#define PLAT_ARM_DRAM2_BASE		ULL(0x080000000)
 #define PLAT_ARM_DRAM2_SIZE		UL(0x80000000)
 
-#define PLAT_HW_CONFIG_DTB_BASE		ULL(0x12000000)
 #define PLAT_HW_CONFIG_DTB_SIZE		ULL(0x8000)
 
 #define ARM_DTB_DRAM_NS			MAP_REGION_FLAT(		\
 					PLAT_HW_CONFIG_DTB_BASE,	\
 					PLAT_HW_CONFIG_DTB_SIZE,	\
 					MT_MEMORY | MT_RO | MT_NS)
+
+#define V2M_FVP_R_SYSREGS_BASE		UL(0x9c010000)
+
 /*
  * Load address of BL33 for this platform port
  */
@@ -80,6 +99,9 @@
 # define PLAT_ARM_MMAP_ENTRIES		12
 # define MAX_XLAT_TABLES		6
 #endif
+# define N_MPU_REGIONS			16  /* number of MPU regions */
+# define ALL_MPU_EL2_REGIONS_USED	0xffffffff
+	/* this is the PRENR_EL2 value if all MPU regions are in use */
 
 /*
  * These nominally reserve the last block of flash for PSCI MEM PROTECT flag,
@@ -228,15 +250,10 @@
 /*
  * Physical and virtual address space limits for MPU in AARCH64 & AARCH32 modes
  */
-#ifdef __aarch64__
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
-#endif
 
 #define ARM_SOC_CONTINUATION_SHIFT	U(24)
 #define ARM_SOC_IDENTIFICATION_SHIFT	U(16)
 
-#endif /* PLATFORM_DEF_H */
+#endif /* FVP_R_PLATFORM_DEF_H */