diff --git a/common/bl_common.c b/common/bl_common.c
index 4e76dd3..61f031b 100644
--- a/common/bl_common.c
+++ b/common/bl_common.c
@@ -265,7 +265,7 @@
 	 * system registers. Pointer authentication can't be enabled here or the
 	 * authentication will fail when returning from this function.
 	 */
-	assert(is_armv8_3_pauth_api_present());
+	assert(is_armv8_3_pauth_apa_api_present());
 
 	uint64_t *apiakey = plat_init_apiakey();
 
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 495ecb3..6af1d03 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -34,10 +34,12 @@
 	return (read_id_aa64isar1_el1() & mask) != 0U;
 }
 
-static inline bool is_armv8_3_pauth_api_present(void)
+static inline bool is_armv8_3_pauth_apa_api_present(void)
 {
-	return ((read_id_aa64isar1_el1() >> ID_AA64ISAR1_API_SHIFT) &
-		ID_AA64ISAR1_API_MASK) != 0U;
+	uint64_t mask = (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) |
+			(ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT);
+
+	return (read_id_aa64isar1_el1() & mask) != 0U;
 }
 
 static inline bool is_armv8_4_ttst_present(void)
diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c
index d7d8c22..0e6a6fa 100644
--- a/lib/xlat_tables_v2/xlat_tables_core.c
+++ b/lib/xlat_tables_v2/xlat_tables_core.c
@@ -231,8 +231,100 @@
 
 } action_t;
 
+/*
+ * Function that returns the first VA of the table affected by the specified
+ * mmap region.
+ */
+static uintptr_t xlat_tables_find_start_va(mmap_region_t *mm,
+				   const uintptr_t table_base_va,
+				   const unsigned int level)
+{
+	uintptr_t table_idx_va;
+
+	if (mm->base_va > table_base_va) {
+		/* Find the first index of the table affected by the region. */
+		table_idx_va = mm->base_va & ~XLAT_BLOCK_MASK(level);
+	} else {
+		/* Start from the beginning of the table. */
+		table_idx_va = table_base_va;
+	}
+
+	return table_idx_va;
+}
+
+/*
+ * Function that returns table index for the given VA and level arguments.
+ */
+static inline unsigned int  xlat_tables_va_to_index(const uintptr_t table_base_va,
+						const uintptr_t va,
+						const unsigned int level)
+{
+	return (unsigned int)((va - table_base_va) >> XLAT_ADDR_SHIFT(level));
+}
+
 #if PLAT_XLAT_TABLES_DYNAMIC
 
+/*
+ * From the given arguments, it decides which action to take when unmapping the
+ * specified region.
+ */
+static action_t xlat_tables_unmap_region_action(const mmap_region_t *mm,
+		const uintptr_t table_idx_va, const uintptr_t table_idx_end_va,
+		const unsigned int level, const uint64_t desc_type)
+{
+	action_t action;
+	uintptr_t region_end_va = mm->base_va + mm->size - 1U;
+
+	if ((mm->base_va <= table_idx_va) &&
+	    (region_end_va >= table_idx_end_va)) {
+		/* Region covers all block */
+
+		if (level == 3U) {
+			/*
+			 * Last level, only page descriptors allowed,
+			 * erase it.
+			 */
+			assert(desc_type == PAGE_DESC);
+
+			action = ACTION_WRITE_BLOCK_ENTRY;
+		} else {
+			/*
+			 * Other levels can have table descriptors. If
+			 * so, recurse into it and erase descriptors
+			 * inside it as needed. If there is a block
+			 * descriptor, just erase it. If an invalid
+			 * descriptor is found, this table isn't
+			 * actually mapped, which shouldn't happen.
+			 */
+			if (desc_type == TABLE_DESC) {
+				action = ACTION_RECURSE_INTO_TABLE;
+			} else {
+				assert(desc_type == BLOCK_DESC);
+				action = ACTION_WRITE_BLOCK_ENTRY;
+			}
+		}
+
+	} else if ((mm->base_va <= table_idx_end_va) ||
+		   (region_end_va >= table_idx_va)) {
+		/*
+		 * Region partially covers block.
+		 *
+		 * It can't happen in level 3.
+		 *
+		 * There must be a table descriptor here, if not there
+		 * was a problem when mapping the region.
+		 */
+		assert(level < 3U);
+		assert(desc_type == TABLE_DESC);
+
+		action = ACTION_RECURSE_INTO_TABLE;
+	} else {
+		/* The region doesn't cover the block at all */
+		action = ACTION_NONE;
+	}
+
+	return action;
+}
 /*
  * Recursive function that writes to the translation tables and unmaps the
  * specified region.
@@ -255,19 +347,8 @@
 
 	unsigned int table_idx;
 
-	if (mm->base_va > table_base_va) {
-		/* Find the first index of the table affected by the region. */
-		table_idx_va = mm->base_va & ~XLAT_BLOCK_MASK(level);
-
-		table_idx = (unsigned int)((table_idx_va - table_base_va) >>
-			    XLAT_ADDR_SHIFT(level));
-
-		assert(table_idx < table_entries);
-	} else {
-		/* Start from the beginning of the table. */
-		table_idx_va = table_base_va;
-		table_idx = 0;
-	}
+	table_idx_va = xlat_tables_find_start_va(mm, table_base_va, level);
+	table_idx = xlat_tables_va_to_index(table_base_va, table_idx_va, level);
 
 	while (table_idx < table_entries) {
 
@@ -276,55 +357,9 @@
 		desc = table_base[table_idx];
 		uint64_t desc_type = desc & DESC_MASK;
 
-		action_t action;
-
-		if ((mm->base_va <= table_idx_va) &&
-		    (region_end_va >= table_idx_end_va)) {
-			/* Region covers all block */
-
-			if (level == 3U) {
-				/*
-				 * Last level, only page descriptors allowed,
-				 * erase it.
-				 */
-				assert(desc_type == PAGE_DESC);
-
-				action = ACTION_WRITE_BLOCK_ENTRY;
-			} else {
-				/*
-				 * Other levels can have table descriptors. If
-				 * so, recurse into it and erase descriptors
-				 * inside it as needed. If there is a block
-				 * descriptor, just erase it. If an invalid
-				 * descriptor is found, this table isn't
-				 * actually mapped, which shouldn't happen.
-				 */
-				if (desc_type == TABLE_DESC) {
-					action = ACTION_RECURSE_INTO_TABLE;
-				} else {
-					assert(desc_type == BLOCK_DESC);
-					action = ACTION_WRITE_BLOCK_ENTRY;
-				}
-			}
-
-		} else if ((mm->base_va <= table_idx_end_va) ||
-			   (region_end_va >= table_idx_va)) {
-			/*
-			 * Region partially covers block.
-			 *
-			 * It can't happen in level 3.
-			 *
-			 * There must be a table descriptor here, if not there
-			 * was a problem when mapping the region.
-			 */
-			assert(level < 3U);
-			assert(desc_type == TABLE_DESC);
-
-			action = ACTION_RECURSE_INTO_TABLE;
-		} else {
-			/* The region doesn't cover the block at all */
-			action = ACTION_NONE;
-		}
+		action_t action = xlat_tables_unmap_region_action(mm,
+				table_idx_va, table_idx_end_va, level,
+				desc_type);
 
 		if (action == ACTION_WRITE_BLOCK_ENTRY) {
 
@@ -525,19 +560,8 @@
 
 	unsigned int table_idx;
 
-	if (mm->base_va > table_base_va) {
-		/* Find the first index of the table affected by the region. */
-		table_idx_va = mm->base_va & ~XLAT_BLOCK_MASK(level);
-
-		table_idx = (unsigned int)((table_idx_va - table_base_va) >>
-			    XLAT_ADDR_SHIFT(level));
-
-		assert(table_idx < table_entries);
-	} else {
-		/* Start from the beginning of the table. */
-		table_idx_va = table_base_va;
-		table_idx = 0U;
-	}
+	table_idx_va = xlat_tables_find_start_va(mm, table_base_va, level);
+	table_idx = xlat_tables_va_to_index(table_base_va, table_idx_va, level);
 
 #if PLAT_XLAT_TABLES_DYNAMIC
 	if (level > ctx->base_level)
diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h
index e9b96dd..c75f213 100644
--- a/plat/arm/css/sgi/include/sgi_variant.h
+++ b/plat/arm/css/sgi/include/sgi_variant.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,9 +10,9 @@
 /* SSC_VERSION values for SGI575 */
 #define SGI575_SSC_VER_PART_NUM		0x0783
 
-/* SID Version values for SGI-Clark */
-#define SGI_CLARK_SID_VER_PART_NUM		0x0786
-#define SGI_CLARK_HELIOS_CONFIG_ID		0x2
+/* SID Version values for RD-N1E1-Edge */
+#define RD_N1E1_EDGE_SID_VER_PART_NUM		0x0786
+#define RD_E1_EDGE_CONFIG_ID			0x2
 
 /* Structure containing SGI platform variant information */
 typedef struct sgi_platform_info {
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index bfcb521..8fa5b01 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,7 +27,7 @@
 		.ring_doorbell = &mhu_ring_doorbell,
 };
 
-static scmi_channel_plat_info_t sgi_clark_scmi_plat_info = {
+static scmi_channel_plat_info_t rd_n1e1_edge_scmi_plat_info = {
 		.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
 		.db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
 		.db_preserve_mask = 0xfffffffe,
@@ -37,8 +37,8 @@
 
 scmi_channel_plat_info_t *plat_css_get_scmi_info()
 {
-	if (sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM)
-		return &sgi_clark_scmi_plat_info;
+	if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM)
+		return &rd_n1e1_edge_scmi_plat_info;
 	else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM)
 		return &sgi575_scmi_plat_info;
 	else
@@ -65,9 +65,9 @@
 
 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
 {
-	/* For SGI-Clark.Helios platform only CPU ON/OFF is supported */
-	if ((sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM) &&
-	    (sgi_plat_info.config_id == SGI_CLARK_HELIOS_CONFIG_ID)) {
+	/* For RD-E1-Edge platform only CPU ON/OFF is supported */
+	if ((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
+	    (sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)) {
 		ops->cpu_standby = NULL;
 		ops->system_off = NULL;
 		ops->system_reset = NULL;
diff --git a/plat/arm/css/sgi/sgi_topology.c b/plat/arm/css/sgi/sgi_topology.c
index dafaf40..f9dbdef 100644
--- a/plat/arm/css/sgi/sgi_topology.c
+++ b/plat/arm/css/sgi/sgi_topology.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,8 +21,8 @@
 	CSS_SGI_MAX_CPUS_PER_CLUSTER
 };
 
-/* SGI-Clark.Helios platform consists of 16 physical CPUS and 32 threads */
-const unsigned char sgi_clark_helios_pd_tree_desc[] = {
+/* RD-E1-Edge platform consists of 16 physical CPUS and 32 threads */
+const unsigned char rd_e1_edge_pd_tree_desc[] = {
 	PLAT_ARM_CLUSTER_COUNT,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	CSS_SGI_MAX_CPUS_PER_CLUSTER,
@@ -49,9 +49,9 @@
  ******************************************************************************/
 const unsigned char *plat_get_power_domain_tree_desc(void)
 {
-	if (sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM &&
-	    sgi_plat_info.config_id == SGI_CLARK_HELIOS_CONFIG_ID)
-		return sgi_clark_helios_pd_tree_desc;
+	if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM &&
+	    sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)
+		return rd_e1_edge_pd_tree_desc;
 	else
 		return sgi_pd_tree_desc;
 }
diff --git a/plat/imx/common/plat_imx8_gic.c b/plat/imx/common/plat_imx8_gic.c
index 27c525b..3a7dcfe 100644
--- a/plat/imx/common/plat_imx8_gic.c
+++ b/plat/imx/common/plat_imx8_gic.c
@@ -9,6 +9,8 @@
 #include <common/bl_common.h>
 #include <common/interrupt_props.h>
 #include <drivers/arm/gicv3.h>
+#include <drivers/arm/arm_gicv3_common.h>
+#include <lib/mmio.h>
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 
@@ -52,8 +54,27 @@
 #endif
 }
 
+static __inline void plat_gicr_exit_sleep(void)
+{
+	unsigned int val = mmio_read_32(PLAT_GICR_BASE + GICR_WAKER);
+
+	/*
+	 * ProcessorSleep bit can ONLY be set to zero when
+	 * Quiescent bit and Sleep bit are both zero, so
+	 * need to make sure Quiescent bit and Sleep bit
+	 * are zero before clearing ProcessorSleep bit.
+	 */
+	if (val & WAKER_QSC_BIT) {
+		mmio_write_32(PLAT_GICR_BASE + GICR_WAKER, val & ~WAKER_SL_BIT);
+		/* Wait till the WAKER_QSC_BIT changes to 0 */
+		while ((mmio_read_32(PLAT_GICR_BASE + GICR_WAKER) & WAKER_QSC_BIT) != 0U)
+			;
+	}
+}
+
 void plat_gic_init(void)
 {
+	plat_gicr_exit_sleep();
 	gicv3_distif_init();
 	gicv3_rdistif_init(plat_my_core_pos());
 	gicv3_cpuif_enable(plat_my_core_pos());
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
index b18edd9..99fa980 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
@@ -84,6 +84,11 @@
 		mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff);
 	}
 
+	/* config CAAM JRaMID set MID to Cortex A */
+	mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
+	mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
+	mmio_write_32(CAAM_JR2MID, CAAM_NS_MID);
+
 #if DEBUG_CONSOLE
 	static console_uart_t console;
 
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index 4957582..5c5b0a5 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -119,3 +119,8 @@
 #define DEBUG_CONSOLE			0
 #define IMX_WDOG_B_RESET
 #define PLAT_IMX8M			1
+
+#define CAAM_JR0MID			U(0x30900010)
+#define CAAM_JR1MID			U(0x30900018)
+#define CAAM_JR2MID			U(0x30900020)
+#define CAAM_NS_MID			U(0x1)