Merge "feat(bl): add interface to query TF-A semantic ver" into integration
diff --git a/Makefile b/Makefile
index dd46f95..2f426ee 100644
--- a/Makefile
+++ b/Makefile
@@ -400,6 +400,8 @@
-ffreestanding -fno-builtin -fno-common \
-Os -std=gnu99
+$(eval $(call add_define,SVE_VECTOR_LEN))
+
ifeq (${SANITIZE_UB},on)
TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover
endif
@@ -1086,6 +1088,7 @@
RAS_EXTENSION \
TWED_DELAY \
ENABLE_FEAT_TWED \
+ SVE_VECTOR_LEN \
)))
ifdef KEY_SIZE
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index fa6ede8..5e53ab4 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -84,10 +85,6 @@
b 2f
1:
- /* Test for EA bit in the instruction syndrome */
- mrs x30, esr_el3
- tbz x30, #ESR_ISS_EABORT_EA_BIT, 3f
-
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
@@ -114,7 +111,6 @@
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
-3:
/* Synchronous exceptions other than the above are assumed to be EA */
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
no_ret report_unhandled_exception
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index b291d62..dc18941 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -834,6 +834,14 @@
to mask these events. Platforms that enable FIQ handling in SP_MIN shall
implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
+- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3.
+ Platforms can configure this if they need to lower the hardware
+ limit, for example due to asymmetric configuration or limitations of
+ software run at lower ELs. The default is the architectural maximum
+ of 2048 which should be suitable for most configurations, the
+ hardware will limit the effective VL to the maximum physically supported
+ VL.
+
- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
Boot feature. When set to '1', BL1 and BL2 images include support to load
and verify the certificates and images in a FIP, and BL1 includes support
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
index 8b9d453..91e681f 100644
--- a/docs/plat/arm/juno/index.rst
+++ b/docs/plat/arm/juno/index.rst
@@ -241,13 +241,13 @@
--------------
-*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
.. _Linaro release software stack: http://releases.linaro.org/members/arm/platforms/
.. _Juno platform software user guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/juno/user-guide.rst
.. _TF-A downloads page: https://downloads.trustedfirmware.org/tf-a/css_scp_2.8.0/juno/
.. _build the binaries from source: https://github.com/ARM-software/SCP-firmware/blob/master/user_guide.md#scp-firmware-user-guide
.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
-.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
+.. _Juno Getting Started Guide: https://developer.arm.com/documentation/den0928/f/?lang=en
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
diff --git a/drivers/partition/gpt.c b/drivers/partition/gpt.c
index ee0bddf..4fe8322 100644
--- a/drivers/partition/gpt.c
+++ b/drivers/partition/gpt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -59,6 +59,7 @@
gpt_entry->first_lba + 1) *
PLAT_PARTITION_BLOCK_SIZE;
guidcpy(&entry->part_guid, &gpt_entry->unique_uuid);
+ guidcpy(&entry->type_guid, &gpt_entry->type_uuid);
return 0;
}
diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c
index c84816f..1881c91 100644
--- a/drivers/partition/partition.c
+++ b/drivers/partition/partition.c
@@ -266,6 +266,19 @@
return NULL;
}
+const partition_entry_t *get_partition_entry_by_type(const uuid_t *type_uuid)
+{
+ int i;
+
+ for (i = 0; i < list.entry_count; i++) {
+ if (guidcmp(type_uuid, &list.list[i].type_guid) == 0) {
+ return &list.list[i];
+ }
+ }
+
+ return NULL;
+}
+
const partition_entry_t *get_partition_entry_by_uuid(const uuid_t *part_uuid)
{
int i;
diff --git a/include/drivers/partition/partition.h b/include/drivers/partition/partition.h
index 11e5acf..6cb59c3 100644
--- a/include/drivers/partition/partition.h
+++ b/include/drivers/partition/partition.h
@@ -36,6 +36,7 @@
uint64_t length;
char name[EFI_NAMELEN];
struct efi_guid part_guid;
+ struct efi_guid type_guid;
} partition_entry_t;
typedef struct partition_entry_list {
@@ -45,6 +46,7 @@
int load_partition_table(unsigned int image_id);
const partition_entry_t *get_partition_entry(const char *name);
+const partition_entry_t *get_partition_entry_by_type(const uuid_t *type_guid);
const partition_entry_t *get_partition_entry_by_uuid(const uuid_t *part_uuid);
const partition_entry_list_t *get_partition_entry_list(void);
void partition_init(unsigned int image_id);
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index 7838304..0e0388b 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -16,6 +16,8 @@
#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
+ .globl cortex_a55_reset_func
+ .globl cortex_a55_core_pwr_dwn
/* --------------------------------------------------
* Errata Workaround for Cortex A55 Errata #768277.
* This applies only to revision r0p0 of Cortex A55.
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 50bd8cd..6d4017a 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -17,6 +17,9 @@
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A76 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
+ .globl cortex_a76_reset_func
+ .globl cortex_a76_core_pwr_dwn
+ .globl cortex_a76_disable_wa_cve_2018_3639
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index be94e91..dd3487a 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -17,6 +17,9 @@
#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
+.globl cortex_a78_reset_func
+.globl cortex_a78_core_pwr_dwn
+
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78
#endif /* WORKAROUND_CVE_2022_23960 */
diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c
index aa8904b..f7dcc76 100644
--- a/lib/extensions/sve/sve.c
+++ b/lib/extensions/sve/sve.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,9 +8,14 @@
#include <arch.h>
#include <arch_helpers.h>
+#include <lib/cassert.h>
#include <lib/el3_runtime/pubsub.h>
#include <lib/extensions/sve.h>
+CASSERT(SVE_VECTOR_LEN <= 2048, assert_sve_vl_too_long);
+CASSERT(SVE_VECTOR_LEN >= 128, assert_sve_vl_too_short);
+CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule);
+
/*
* Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation.
* VECTOR_SIZE = (LEN+1) * 128
@@ -39,9 +44,9 @@
cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT);
write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3);
- /* Restrict maximum SVE vector length (SVE_VECTOR_LENGTH+1) * 128. */
+ /* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */
write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3,
- (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(512)));
+ (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN)));
}
void sve_disable(cpu_context_t *context)
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index fab6bf6..d957a4b 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -373,6 +373,9 @@
endif
ENABLE_SVE_FOR_SWD := 0
+# Default SVE vector length to maximum architected value
+SVE_VECTOR_LEN := 2048
+
# SME defaults to disabled
ENABLE_SME_FOR_NS := 0
ENABLE_SME_FOR_SWD := 0
@@ -415,6 +418,13 @@
# Build option to provide openssl directory path
OPENSSL_DIR := /usr
+# Select the openssl binary provided in OPENSSL_DIR variable
+ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "")
+ OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps
+else
+ OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin
+endif
+
# Build option to use the SP804 timer instead of the generic one
USE_SP804_TIMER := 0
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index b11811c..1d0eb13 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -53,8 +53,8 @@
ifndef ROT_KEY
$(error Cannot generate hash: no ROT_KEY defined)
endif
- openssl ${CRYPTO_ALG} -in $< -pubout -outform DER | openssl dgst \
- -sha256 -binary > $@
+ ${OPENSSL_BIN_PATH}/openssl ${CRYPTO_ALG} -in $< -pubout -outform DER | \
+ ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@
# Certificate NV-Counters. Use values corresponding to tied off values in
# ARM development platforms
diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk
index 3e1771c..2bfc582 100644
--- a/plat/hisilicon/hikey/platform.mk
+++ b/plat/hisilicon/hikey/platform.mk
@@ -154,12 +154,12 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
@echo " OPENSSL $@"
- $(Q)openssl genrsa 2048 > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
@echo " OPENSSL $@"
- $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
- openssl dgst -sha256 -binary > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
# Enable workarounds for selected Cortex-A53 errata.
diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk
index 608fe09..c8ad66c 100644
--- a/plat/hisilicon/hikey960/platform.mk
+++ b/plat/hisilicon/hikey960/platform.mk
@@ -146,12 +146,12 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
@echo " OPENSSL $@"
- $(Q)openssl genrsa 2048 > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
@echo " OPENSSL $@"
- $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
- openssl dgst -sha256 -binary > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
# Enable workarounds for selected Cortex-A53 errata.
diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk
index fdde9a9..f4f5bfc 100644
--- a/plat/imx/imx7/common/imx7.mk
+++ b/plat/imx/imx7/common/imx7.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -80,13 +80,13 @@
$(ROT_KEY): | $(BUILD_PLAT)
@echo " OPENSSL $@"
@if [ ! -f $(ROT_KEY) ]; then \
- openssl genrsa 2048 > $@ 2>/dev/null; \
+ ${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
fi
$(ROTPK_HASH): $(ROT_KEY)
@echo " OPENSSL $@"
- $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
- openssl dgst -sha256 -binary > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
# Add the build options to pack BLx images and kernel device tree
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 1c6c9f8..e3e5c0c 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -132,13 +132,13 @@
$(ROT_KEY): | $(BUILD_PLAT)
@echo " OPENSSL $@"
@if [ ! -f $(ROT_KEY) ]; then \
- openssl genrsa 2048 > $@ 2>/dev/null; \
+ ${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
fi
$(ROTPK_HASH): $(ROT_KEY)
@echo " OPENSSL $@"
- $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
- openssl dgst -sha256 -binary > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
USE_COHERENT_MEM := 1
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 45f2972..e8669e5 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -129,13 +129,13 @@
$(ROT_KEY): | $(BUILD_PLAT)
@echo " OPENSSL $@"
@if [ ! -f $(ROT_KEY) ]; then \
- openssl genrsa 2048 > $@ 2>/dev/null; \
+ ${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
fi
$(ROTPK_HASH): $(ROT_KEY)
@echo " OPENSSL $@"
- $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
- openssl dgst -sha256 -binary > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
USE_COHERENT_MEM := 1
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
index d0e8688..5547201 100644
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -205,12 +205,12 @@
@$(ECHO_BLANK_LINE)
$(Q)cp $(BUILD_PLAT)/wtmi.bin $(BUILD_PLAT)/wtmi-align.bin
$(Q)truncate -s %16 $(BUILD_PLAT)/wtmi-align.bin
- $(Q)openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/wtmi-align.bin \
+ $(Q)${OPENSSL_BIN_PATH}/openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/wtmi-align.bin \
-out $(BUILD_PLAT)/$(WTMI_ENC_IMG) \
-K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \
-iv `cat $(IMAGESPATH)/iv.txt` -p
$(Q)truncate -s %16 $(BUILD_PLAT)/$(BOOT_IMAGE);
- $(Q)openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) \
+ $(Q)${OPENSSL_BIN_PATH}/openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) \
-out $(BUILD_PLAT)/$(BOOT_ENC_IMAGE) \
-K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \
-iv `cat $(IMAGESPATH)/iv.txt` -p
diff --git a/plat/nxp/common/tbbr/tbbr.mk b/plat/nxp/common/tbbr/tbbr.mk
index 7edcfbc..4aac9d6 100644
--- a/plat/nxp/common/tbbr/tbbr.mk
+++ b/plat/nxp/common/tbbr/tbbr.mk
@@ -133,13 +133,13 @@
$(ROT_KEY): | $(BUILD_PLAT)
@echo " OPENSSL $@"
@if [ ! -f $(ROT_KEY) ]; then \
- openssl genrsa 2048 > $@ 2>/dev/null; \
+ ${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
fi
$(ROTPK_HASH): $(ROT_KEY)
@echo " OPENSSL $@"
- $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
- openssl dgst -sha256 -binary > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif #MBEDTLS_DIR
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 8e7f7c8..e0b5271 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -88,12 +88,12 @@
$(ROT_KEY): | $(BUILD_PLAT)
@echo " OPENSSL $@"
- $(Q)openssl genrsa 2048 > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
@echo " OPENSSL $@"
- $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
- openssl dgst -sha256 -binary > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
# Include Measured Boot makefile before any Crypto library makefile.
diff --git a/plat/qti/common/inc/qti_plat.h b/plat/qti/common/inc/qti_plat.h
index 4d9d320..d616efe 100644
--- a/plat/qti/common/inc/qti_plat.h
+++ b/plat/qti/common/inc/qti_plat.h
@@ -25,13 +25,14 @@
/*
* Utility functions common to ARM standard platforms
*/
-void qti_setup_page_tables(uintptr_t total_base,
+void qti_setup_page_tables(
+ uintptr_t total_base,
size_t total_size,
uintptr_t code_start,
uintptr_t code_limit,
uintptr_t rodata_start,
- uintptr_t rodata_limit,
- uintptr_t coh_start, uintptr_t coh_limit);
+ uintptr_t rodata_limit
+ );
/*
* Mandatory functions required in ARM standard platforms
diff --git a/plat/qti/common/src/aarch64/qti_helpers.S b/plat/qti/common/src/aarch64/qti_helpers.S
index c1ea7b3..d34b530 100644
--- a/plat/qti/common/src/aarch64/qti_helpers.S
+++ b/plat/qti/common/src/aarch64/qti_helpers.S
@@ -72,17 +72,10 @@
/* save the lr */
mov x18, x30
- /* Serialize CPUSS boot setup. Multi core enter simultaneously. */
- ldr x0, =g_qti_cpuss_boot_lock
- bl spin_lock
-
/* pass cold boot status. */
ldr w0, g_qti_bl31_cold_booted
/* Execuete CPUSS boot set up on every core. */
bl qtiseclib_cpuss_reset_asm
- ldr x0, =g_qti_cpuss_boot_lock
- bl spin_unlock
-
ret x18
endfunc plat_reset_handler
diff --git a/plat/qti/common/src/aarch64/qti_kryo4_gold.S b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
index a1b40c8..9bcdf54 100644
--- a/plat/qti/common/src/aarch64/qti_kryo4_gold.S
+++ b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
@@ -28,19 +28,11 @@
mov x19, x30
bl qtiseclib_kryo4_gold_reset_asm
-
- ret x19
+ mov x30, x19
+ b cortex_a76_reset_func
endfunc qti_kryo4_gold_reset_func
-/* ----------------------------------------------------
- * The CPU Ops core power down function for Kryo-3 Gold
- * ----------------------------------------------------
- */
-func qti_kryo4_gold_core_pwr_dwn
- ret
-endfunc qti_kryo4_gold_core_pwr_dwn
-
/* -------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Gold
* -------------------------------------------------------
@@ -77,7 +69,9 @@
ret
endfunc qti_kryo4_gold_cpu_reg_dump
-declare_cpu_ops qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \
+declare_cpu_ops_wa qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \
qti_kryo4_gold_reset_func, \
- qti_kryo4_gold_core_pwr_dwn, \
+ CPU_NO_EXTRA1_FUNC, \
+ cortex_a76_disable_wa_cve_2018_3639, \
+ cortex_a76_core_pwr_dwn, \
qti_kryo4_gold_cluster_pwr_dwn
diff --git a/plat/qti/common/src/aarch64/qti_kryo4_silver.S b/plat/qti/common/src/aarch64/qti_kryo4_silver.S
index 183eeb0..36374b7 100644
--- a/plat/qti/common/src/aarch64/qti_kryo4_silver.S
+++ b/plat/qti/common/src/aarch64/qti_kryo4_silver.S
@@ -22,19 +22,11 @@
mov x19, x30
bl qtiseclib_kryo4_silver_reset_asm
-
- ret x19
+ mov x30, x19
+ b cortex_a55_reset_func
endfunc qti_kryo4_silver_reset_func
-/* ------------------------------------------------------
- * The CPU Ops core power down function for Kryo-3 Silver
- * ------------------------------------------------------
- */
-func qti_kryo4_silver_core_pwr_dwn
- ret
-endfunc qti_kryo4_silver_core_pwr_dwn
-
/* ---------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Silver
* ---------------------------------------------------------
@@ -75,5 +67,5 @@
declare_cpu_ops qti_kryo4_silver, QTI_KRYO4_SILVER_MIDR, \
qti_kryo4_silver_reset_func, \
- qti_kryo4_silver_core_pwr_dwn, \
+ cortex_a55_core_pwr_dwn, \
qti_kryo4_silver_cluster_pwr_dwn
diff --git a/plat/qti/common/src/aarch64/qti_kryo6_gold.S b/plat/qti/common/src/aarch64/qti_kryo6_gold.S
index db1a304..577e7ff 100644
--- a/plat/qti/common/src/aarch64/qti_kryo6_gold.S
+++ b/plat/qti/common/src/aarch64/qti_kryo6_gold.S
@@ -28,19 +28,11 @@
mov x19, x30
bl qtiseclib_kryo6_gold_reset_asm
-
- ret x19
+ mov x30, x19
+ b cortex_a78_reset_func
endfunc qti_kryo6_gold_reset_func
-/* ----------------------------------------------------
- * The CPU Ops core power down function for Kryo-3 Gold
- * ----------------------------------------------------
- */
-func qti_kryo6_gold_core_pwr_dwn
- ret
-endfunc qti_kryo6_gold_core_pwr_dwn
-
/* -------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Gold
* -------------------------------------------------------
@@ -79,5 +71,5 @@
declare_cpu_ops qti_kryo6_gold, QTI_KRYO6_GOLD_MIDR, \
qti_kryo6_gold_reset_func, \
- qti_kryo6_gold_core_pwr_dwn, \
+ cortex_a78_core_pwr_dwn, \
qti_kryo6_gold_cluster_pwr_dwn
diff --git a/plat/qti/common/src/aarch64/qti_kryo6_silver.S b/plat/qti/common/src/aarch64/qti_kryo6_silver.S
index 2d189f2..6ad0bca 100644
--- a/plat/qti/common/src/aarch64/qti_kryo6_silver.S
+++ b/plat/qti/common/src/aarch64/qti_kryo6_silver.S
@@ -22,19 +22,11 @@
mov x19, x30
bl qtiseclib_kryo6_silver_reset_asm
-
- ret x19
+ mov x30, x19
+ b cortex_a55_reset_func
endfunc qti_kryo6_silver_reset_func
-/* ------------------------------------------------------
- * The CPU Ops core power down function for Kryo-3 Silver
- * ------------------------------------------------------
- */
-func qti_kryo6_silver_core_pwr_dwn
- ret
-endfunc qti_kryo6_silver_core_pwr_dwn
-
/* ---------------------------------------------------------
* The CPU Ops cluster power down function for Kryo-3 Silver
* ---------------------------------------------------------
@@ -75,5 +67,5 @@
declare_cpu_ops qti_kryo6_silver, QTI_KRYO6_SILVER_MIDR, \
qti_kryo6_silver_reset_func, \
- qti_kryo6_silver_core_pwr_dwn, \
+ cortex_a55_core_pwr_dwn, \
qti_kryo6_silver_cluster_pwr_dwn
diff --git a/plat/qti/common/src/qti_bl31_setup.c b/plat/qti/common/src/qti_bl31_setup.c
index b2bc543..dac0253 100644
--- a/plat/qti/common/src/qti_bl31_setup.c
+++ b/plat/qti/common/src/qti_bl31_setup.c
@@ -36,16 +36,10 @@
static uint64_t g_qti_cpu_cntfrq;
/*
- * Lock variable to serialize cpuss reset execution.
- */
-spinlock_t g_qti_cpuss_boot_lock __attribute__ ((section("tzfw_coherent_mem"),
- aligned(CACHE_WRITEBACK_GRANULE))) = {0x0};
-
-/*
* Variable to hold bl31 cold boot status. Default value 0x0 means yet to boot.
* Any other value means cold booted.
*/
-uint32_t g_qti_bl31_cold_booted __attribute__ ((section("tzfw_coherent_mem"))) = 0x0;
+uint32_t g_qti_bl31_cold_booted;
/*******************************************************************************
* Perform any BL31 early platform setup common to ARM standard platforms.
@@ -91,13 +85,14 @@
******************************************************************************/
void bl31_plat_arch_setup(void)
{
- qti_setup_page_tables(BL_CODE_BASE,
- BL_COHERENT_RAM_END - BL_CODE_BASE,
+ qti_setup_page_tables(
+ BL31_START,
+ BL31_END-BL31_START,
BL_CODE_BASE,
BL_CODE_END,
BL_RO_DATA_BASE,
- BL_RO_DATA_END,
- BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
+ BL_RO_DATA_END
+ );
enable_mmu_el3(0);
}
diff --git a/plat/qti/common/src/qti_common.c b/plat/qti/common/src/qti_common.c
index da0eaec..8821731 100644
--- a/plat/qti/common/src/qti_common.c
+++ b/plat/qti/common/src/qti_common.c
@@ -77,13 +77,14 @@
* - Read-only data section;
* - Coherent memory region, if applicable.
*/
-void qti_setup_page_tables(uintptr_t total_base,
+void qti_setup_page_tables(
+ uintptr_t total_base,
size_t total_size,
uintptr_t code_start,
uintptr_t code_limit,
uintptr_t rodata_start,
- uintptr_t rodata_limit,
- uintptr_t coh_start, uintptr_t coh_limit)
+ uintptr_t rodata_limit
+ )
{
/*
* Map the Trusted SRAM with appropriate memory attributes.
@@ -106,12 +107,6 @@
mmap_add_region(rodata_start, rodata_start,
rodata_limit - rodata_start, MT_RO_DATA | MT_SECURE);
- /* Re-map the coherent memory region */
- VERBOSE("Coherent region: %p - %p\n",
- (void *)coh_start, (void *)coh_limit);
- mmap_add_region(coh_start, coh_start,
- coh_limit - coh_start, MT_DEVICE | MT_RW | MT_SECURE);
-
/* Now (re-)map the platform-specific memory regions */
mmap_add(plat_qti_mmap);
diff --git a/plat/qti/qtiseclib/src/qtiseclib_interface_stub.c b/plat/qti/qtiseclib/src/qtiseclib_interface_stub.c
index 9c93d51..cdaa0a7 100644
--- a/plat/qti/qtiseclib/src/qtiseclib_interface_stub.c
+++ b/plat/qti/qtiseclib/src/qtiseclib_interface_stub.c
@@ -50,6 +50,21 @@
}
/*
+ * Execute CPU (Kryo4 gold) specific reset handler / system initialization.
+ * This takes care of executing required CPU errata's.
+ *
+ * Clobbers: x0 - x16
+ */
+void qtiseclib_kryo6_gold_reset_asm(void)
+{
+}
+
+
+void qtiseclib_kryo6_silver_reset_asm(void)
+{
+}
+
+/*
* C Api's
*/
void qtiseclib_bl31_platform_setup(void)
diff --git a/plat/qti/sc7180/platform.mk b/plat/qti/sc7180/platform.mk
index 141e2c3..41a08ca 100644
--- a/plat/qti/sc7180/platform.mk
+++ b/plat/qti/sc7180/platform.mk
@@ -12,12 +12,17 @@
# Turn On Separate code & data.
SEPARATE_CODE_AND_RODATA := 1
-USE_COHERENT_MEM := 1
+USE_COHERENT_MEM := 0
WARMBOOT_ENABLE_DCACHE_EARLY := 1
+HW_ASSISTED_COHERENCY := 1
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
+#Enable errata for cortex_a55 and cortex_a76
+ERRATA_A55_1530923 := 1
+ERRATA_A76_1165522 := 1
+
# Enable PSCI v1.0 extended state ID format
PSCI_EXTENDED_STATE_ID := 1
ARM_RECOM_STATE_ID_ENC := 1
@@ -93,10 +98,14 @@
GIC_SOURCES := plat/common/plat_gicv3.c \
${GICV3_SOURCES} \
-BL31_SOURCES += ${QTI_BL31_SOURCES} \
- ${PSCI_SOURCES} \
- ${GIC_SOURCES} \
- ${TIMER_SOURCES} \
+CPU_SOURCES := lib/cpus/aarch64/cortex_a76.S \
+ lib/cpus/aarch64/cortex_a55.S \
+
+BL31_SOURCES += ${QTI_BL31_SOURCES} \
+ ${PSCI_SOURCES} \
+ ${GIC_SOURCES} \
+ ${TIMER_SOURCES} \
+ ${CPU_SOURCES} \
LIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET}
diff --git a/plat/qti/sc7280/platform.mk b/plat/qti/sc7280/platform.mk
index bc2c221..df07bc4 100644
--- a/plat/qti/sc7280/platform.mk
+++ b/plat/qti/sc7280/platform.mk
@@ -12,8 +12,15 @@
# Turn On Separate code & data.
SEPARATE_CODE_AND_RODATA := 1
-USE_COHERENT_MEM := 1
+USE_COHERENT_MEM := 0
WARMBOOT_ENABLE_DCACHE_EARLY := 1
+HW_ASSISTED_COHERENCY := 1
+
+#Enable errata configs for cortex_a78 and cortex_a55
+ERRATA_A55_1530923 := 1
+ERRATA_A78_1941498 := 1
+ERRATA_A78_1951500 := 1
+ERRATA_A78_2132060 := 1
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
@@ -93,10 +100,14 @@
GIC_SOURCES := plat/common/plat_gicv3.c \
${GICV3_SOURCES} \
-BL31_SOURCES += ${QTI_BL31_SOURCES} \
- ${PSCI_SOURCES} \
- ${GIC_SOURCES} \
- ${TIMER_SOURCES} \
+CPU_SOURCES := lib/cpus/aarch64/cortex_a78.S \
+ lib/cpus/aarch64/cortex_a55.S \
+
+BL31_SOURCES += ${QTI_BL31_SOURCES} \
+ ${PSCI_SOURCES} \
+ ${GIC_SOURCES} \
+ ${TIMER_SOURCES} \
+ ${CPU_SOURCES} \
LIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET}
diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index 6c23923..53c97e2 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@@ -212,10 +212,10 @@
$(ROT_KEY): | $(BUILD_PLAT)
@echo " OPENSSL $@"
- $(Q)openssl genrsa 2048 > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
@echo " OPENSSL $@"
- $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
- openssl dgst -sha256 -binary > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk
index 3eab3d6..b76ae88 100644
--- a/plat/socionext/synquacer/platform.mk
+++ b/plat/socionext/synquacer/platform.mk
@@ -73,12 +73,12 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
@echo " OPENSSL $@"
- $(Q)openssl genrsa 2048 > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
@echo " OPENSSL $@"
- $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
- openssl dgst -sha256 -binary > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif # TRUSTED_BOARD_BOOT
endif
diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index 6edd181..378497a 100644
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk
@@ -107,12 +107,12 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
@echo " OPENSSL $@"
- $(Q)openssl genrsa 2048 > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
@echo " OPENSSL $@"
- $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
- openssl dgst -sha256 -binary > $@ 2>/dev/null
+ $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index 94c36d9..49f6465 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -37,6 +37,7 @@
#include <platform_def.h>
#include <stm32cubeprogrammer.h>
+#include <stm32mp_efi.h>
#include <stm32mp_fconf_getter.h>
#include <stm32mp_io_storage.h>
#include <usb_dfu.h>
@@ -451,13 +452,20 @@
*/
#if !PSA_FWU_SUPPORT
const partition_entry_t *entry;
+ const struct efi_guid img_type_guid = STM32MP_FIP_GUID;
+ uuid_t img_type_uuid;
+ guidcpy(&img_type_uuid, &img_type_guid);
partition_init(GPT_IMAGE_ID);
- entry = get_partition_entry(FIP_IMAGE_NAME);
+ entry = get_partition_entry_by_type(&img_type_uuid);
if (entry == NULL) {
- ERROR("Could NOT find the %s partition!\n",
- FIP_IMAGE_NAME);
- return -ENOENT;
+ entry = get_partition_entry(FIP_IMAGE_NAME);
+ if (entry == NULL) {
+ ERROR("Could NOT find the %s partition!\n",
+ FIP_IMAGE_NAME);
+
+ return -ENOENT;
+ }
}
image_block_spec.offset = entry->start;
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index a903a16..b425fa5 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -86,34 +86,28 @@
WORKAROUND_CVE_2017_5715:= 0
WORKAROUND_CVE_2022_23960:= 0
+# Number of TF-A copies in the device
+STM32_TF_A_COPIES := 2
+
+# PLAT_PARTITION_MAX_ENTRIES must take care of STM32_TF-A_COPIES and other partitions
+# such as metadata (2) to find all the FIP partitions (default is 2).
+PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 4)))
+
ifeq (${PSA_FWU_SUPPORT},1)
ifneq (${STM32MP_USE_STM32IMAGE},1)
# Number of banks of updatable firmware
NR_OF_FW_BANKS := 2
NR_OF_IMAGES_IN_FW_BANK := 1
-# Number of TF-A copies in the device
-STM32_TF_A_COPIES := 2
-STM32_BL33_PARTS_NUM := 2
-STM32_RUNTIME_PARTS_NUM := 4
-else
-$(error FWU Feature enabled only with FIP images)
+FWU_MAX_PART = $(shell echo $$(($(STM32_TF_A_COPIES) + 2 + $(NR_OF_FW_BANKS))))
+ifeq ($(shell test $(FWU_MAX_PART) -gt $(PLAT_PARTITION_MAX_ENTRIES); echo $$?),0)
+$(error "Required partition number is $(FWU_MAX_PART) where PLAT_PARTITION_MAX_ENTRIES is only \
+$(PLAT_PARTITION_MAX_ENTRIES)")
endif
else
-# Number of TF-A copies in the device
-STM32_TF_A_COPIES := 2
-STM32_BL33_PARTS_NUM := 1
-ifeq ($(AARCH32_SP),optee)
-STM32_RUNTIME_PARTS_NUM := 3
-else ifeq ($(STM32MP_USE_STM32IMAGE),1)
-STM32_RUNTIME_PARTS_NUM := 0
-else
-STM32_RUNTIME_PARTS_NUM := 1
+$(error FWU Feature enabled only with FIP images)
endif
endif
-PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + \
- $(STM32_BL33_PARTS_NUM) + \
- $(STM32_RUNTIME_PARTS_NUM))))
# Boot devices
STM32MP_EMMC ?= 0
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 593cdc4..b8db4a6 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -73,7 +73,7 @@
if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) {
static console_t versal_runtime_console;
/* Initialize the console to provide early debug support */
- int32_t rc = console_pl011_register((unsigned long)VERSAL_UART_BASE,
+ int32_t rc = console_pl011_register((uintptr_t)VERSAL_UART_BASE,
(uint32_t)VERSAL_UART_CLOCK,
(uint32_t)VERSAL_UART_BAUDRATE,
&versal_runtime_console);
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index 766cafa..4b0b311 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -81,15 +81,15 @@
# define VERSAL_UART_BAUDRATE 115200
# define VERSAL_CPU_CLOCK 100000000
#elif VERSAL_PLATFORM_IS(spp_itr6)
-# define PLATFORM_NAME "SPP ITR6"
-# define VERSAL_UART_CLOCK 25000000
-# define VERSAL_UART_BAUDRATE 115200
-# define VERSAL_CPU_CLOCK 2720000
+# define PLATFORM_NAME "SPP ITR6"
+# define VERSAL_UART_CLOCK 25000000
+# define VERSAL_UART_BAUDRATE 115200
+# define VERSAL_CPU_CLOCK 2720000
#elif VERSAL_PLATFORM_IS(emu_itr6)
-# define PLATFORM_NAME "EMU ITR6"
-# define VERSAL_UART_CLOCK 212000
-# define VERSAL_UART_BAUDRATE 9600
-# define VERSAL_CPU_CLOCK 212000
+# define PLATFORM_NAME "EMU ITR6"
+# define VERSAL_UART_CLOCK 212000
+# define VERSAL_UART_BAUDRATE 9600
+# define VERSAL_CPU_CLOCK 212000
#endif
/* Access control register defines */
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index acecbb1..6787f31 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -238,7 +238,7 @@
/*******************************************************************************
* Export the platform specific power ops.
******************************************************************************/
-int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint,
const struct plat_psci_ops **psci_ops)
{
versal_sec_entry = sec_entrypoint;
diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c
index e464d32..8fa8a44 100644
--- a/plat/xilinx/versal/pm_service/pm_api_sys.c
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.c
@@ -462,7 +462,7 @@
}
gicd_write_irouter(gicv3_driver_data->gicd_base,
(uint32_t)PLAT_VERSAL_IPI_IRQ, MODE);
- ret = PM_RET_SUCCESS;
+ ret = PM_RET_SUCCESS;
break;
default:
return PM_RET_ERROR_NOTSUPPORTED;
diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h
index 6fa65c2..121ec1a 100644
--- a/plat/xilinx/versal/pm_service/pm_api_sys.h
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.h
@@ -16,8 +16,8 @@
#define LIBPM_MODULE_ID 0x2U
#define LOADER_MODULE_ID 0x7U
-#define MODE 0x80000000U
-#define MODULE_ID_MASK 0x0000ff00
+#define MODE 0x80000000U
+#define MODULE_ID_MASK 0x0000ff00U
/**********************************************************
* PM API function declarations
**********************************************************/
diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h
index 5491555..2922b5d 100644
--- a/plat/xilinx/versal/pm_service/pm_defs.h
+++ b/plat/xilinx/versal/pm_service/pm_defs.h
@@ -39,9 +39,7 @@
/* PM API Versions */
#define PM_API_BASE_VERSION 1U
-#define PM_API_VERSION_2 2U
-
-#define PM_API_QUERY_DATA_VERSION 2U
+#define PM_API_VERSION_2 2U
/* PM API ids */
#define PM_REGISTER_NOTIFIER 5U
diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c
index 4b0f5e0..fef21f7 100644
--- a/plat/xilinx/versal/pm_service/pm_svc_main.c
+++ b/plat/xilinx/versal/pm_service/pm_svc_main.c
@@ -59,7 +59,7 @@
* Update the SGI number to be used.
*
*/
-int pm_register_sgi(uint32_t sgi_num, uint32_t reset)
+int32_t pm_register_sgi(uint32_t sgi_num, uint32_t reset)
{
if (reset == 1U) {
sgi = INVALID_SGI;
@@ -91,7 +91,7 @@
* Called from sip_svc_setup initialization function with the
* rt_svc_init signature.
*/
-int pm_setup(void)
+int32_t pm_setup(void)
{
int32_t status, ret = 0;
@@ -146,7 +146,7 @@
if (ret == PM_RET_ERROR_NOTSUPPORTED)
return (uintptr_t)0;
- SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
}
case PM_QUERY_DATA:
@@ -154,10 +154,10 @@
uint32_t data[PAYLOAD_ARG_CNT] = { 0 };
ret = pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
- pm_arg[3], data, security_flag);
+ pm_arg[3], data, security_flag);
- SMC_RET2(handle, (uint64_t)ret | ((uint64_t)data[0] << 32U),
- (uint64_t)data[1] | ((uint64_t)data[2] << 32U));
+ SMC_RET2(handle, (uint64_t)ret | ((uint64_t)data[0] << 32U),
+ (uint64_t)data[1] | ((uint64_t)data[2] << 32U));
}
case PM_FEATURE_CHECK:
@@ -201,24 +201,24 @@
case PM_SELF_SUSPEND:
ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], security_flag);
- SMC_RET1(handle, (uint64_t)ret);
+ SMC_RET1(handle, (u_register_t)ret);
case PM_FORCE_POWERDOWN:
ret = pm_force_powerdown(pm_arg[0], pm_arg[1], security_flag);
- SMC_RET1(handle, (uint64_t)ret);
+ SMC_RET1(handle, (u_register_t)ret);
case PM_REQ_SUSPEND:
ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], security_flag);
- SMC_RET1(handle, (uint64_t)ret);
+ SMC_RET1(handle, (u_register_t)ret);
case PM_ABORT_SUSPEND:
ret = pm_abort_suspend(pm_arg[0], security_flag);
- SMC_RET1(handle, (uint64_t)ret);
+ SMC_RET1(handle, (u_register_t)ret);
case PM_SYSTEM_SHUTDOWN:
ret = pm_system_shutdown(pm_arg[0], pm_arg[1], security_flag);
- SMC_RET1(handle, (uint64_t)ret);
+ SMC_RET1(handle, (u_register_t)ret);
default:
return (uintptr_t)0;
@@ -297,13 +297,13 @@
if ((pm_arg[0] == XPM_QID_CLOCK_GET_NAME ||
pm_arg[0] == XPM_QID_PINCTRL_GET_FUNCTION_NAME) &&
ret == PM_RET_SUCCESS) {
- SMC_RET2(handle, (uint64_t)buf[0] | ((uint64_t)buf[1] << 32),
- (uint64_t)buf[2] | ((uint64_t)buf[3] << 32));
+ SMC_RET2(handle, (uint64_t)buf[0] | ((uint64_t)buf[1] << 32U),
+ (uint64_t)buf[2] | ((uint64_t)buf[3] << 32U));
}
}
- SMC_RET2(handle, (uint64_t)ret | ((uint64_t)buf[0] << 32),
- (uint64_t)buf[1] | ((uint64_t)buf[2] << 32));
+ SMC_RET2(handle, (uint64_t)ret | ((uint64_t)buf[0] << 32U),
+ (uint64_t)buf[1] | ((uint64_t)buf[2] << 32U));
}
/**
@@ -345,9 +345,9 @@
}
pm_arg[0] = (uint32_t)x1;
- pm_arg[1] = (uint32_t)(x1 >> 32);
+ pm_arg[1] = (uint32_t)(x1 >> 32U);
pm_arg[2] = (uint32_t)x2;
- pm_arg[3] = (uint32_t)(x2 >> 32);
+ pm_arg[3] = (uint32_t)(x2 >> 32U);
pm_arg[4] = (uint32_t)x3;
(void)(x4);
api_id = smc_fid & FUNCID_NUM_MASK;
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index ea8a5d1..dd82bc0 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -21,7 +21,7 @@
WORKAROUND_CVE_2017_5715 := 0
-ARM_XLAT_TABLES_LIB_V1 := 1
+ARM_XLAT_TABLES_LIB_V1 := 1
$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
@@ -60,6 +60,10 @@
$(eval $(call add_define,IPI_CRC_CHECK))
endif
+ifdef ZYNQMP_SECURE_EFUSES
+ $(eval $(call add_define,ZYNQMP_SECURE_EFUSES))
+endif
+
PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
-Iinclude/plat/arm/common/aarch64/ \
-Iplat/xilinx/common/include/ \
diff --git a/plat/xilinx/zynqmp/pm_service/pm_defs.h b/plat/xilinx/zynqmp/pm_service/pm_defs.h
index d48df55..bf5ecfe 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_defs.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_defs.h
@@ -245,6 +245,7 @@
* @PM_RET_SUCCESS: success
* @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated)
* @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated)
+ * @PM_RET_ERROR_NOT_ENABLED: feature is not enabled
* @PM_RET_ERROR_INTERNAL: internal error
* @PM_RET_ERROR_CONFLICT: conflict
* @PM_RET_ERROR_ACCESS: access rights violation
@@ -258,6 +259,7 @@
PM_RET_SUCCESS,
PM_RET_ERROR_ARGS = 1,
PM_RET_ERROR_NOTSUPPORTED = 4,
+ PM_RET_ERROR_NOT_ENABLED = 29,
PM_RET_ERROR_INTERNAL = 2000,
PM_RET_ERROR_CONFLICT = 2001,
PM_RET_ERROR_ACCESS = 2002,
diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
index a136ebc..f24387a 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
@@ -520,6 +520,13 @@
{
uint32_t value;
+#if defined(ZYNQMP_SECURE_EFUSES)
+ if (is_caller_non_secure(flags)) {
+ SMC_RET1(handle,
+ (((uint64_t)PM_RET_ERROR_NOT_ENABLED) << 32) |
+ (uint64_t)PM_RET_ERROR_ACCESS);
+ }
+#endif
ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}